CN113219747B - Array substrate, liquid crystal display panel and liquid crystal display - Google Patents
Array substrate, liquid crystal display panel and liquid crystal display Download PDFInfo
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- CN113219747B CN113219747B CN202110444451.4A CN202110444451A CN113219747B CN 113219747 B CN113219747 B CN 113219747B CN 202110444451 A CN202110444451 A CN 202110444451A CN 113219747 B CN113219747 B CN 113219747B
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- 239000000758 substrate Substances 0.000 title claims abstract description 74
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 50
- 239000010409 thin film Substances 0.000 claims abstract description 96
- 239000003990 capacitor Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000002161 passivation Methods 0.000 claims description 15
- 239000010408 film Substances 0.000 claims description 8
- 238000004891 communication Methods 0.000 claims description 6
- 239000002052 molecular layer Substances 0.000 claims description 3
- 238000004088 simulation Methods 0.000 description 28
- 238000010586 diagram Methods 0.000 description 26
- 208000028659 discharge Diseases 0.000 description 8
- 241001270131 Agaricus moelleri Species 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000003860 storage Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
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Abstract
The invention provides an array substrate, a liquid crystal display panel and a liquid crystal display, wherein a voltage division capacitor is arranged in a first sub-pixel area of the array substrate, and the voltage division capacitor is composed of a first voltage division electrode and a second voltage division electrode which are arranged in an overlapped mode; the grid electrodes of the first thin film transistor, the second thin film transistor and the fourth thin film transistor are respectively connected with the main scanning line, the grid electrode of the third thin film transistor is connected with the auxiliary scanning line, the source and drain electrodes of the first thin film transistor are respectively connected with the data line and the first sub-pixel electrode, the source and drain electrodes of the second thin film transistor are respectively connected with the data line and the second sub-pixel electrode, the source and drain electrodes of the third thin film transistor are respectively connected with the second sub-pixel electrode and the second voltage division electrode, and the source and drain electrodes of the fourth thin film transistor are respectively connected with the first voltage division electrode and the second voltage division electrode. The invention provides an array substrate, a liquid crystal display panel and a liquid crystal display, which can improve the wide-viewing-angle taste of the liquid crystal display panel.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to an array substrate, a liquid crystal display panel and a liquid crystal display.
Background
The liquid crystal display panel generally includes an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate. A plurality of Thin Film Transistors (TFTs) are provided in the liquid crystal display panel, and are used as switches for electric signals for driving the liquid crystal, and the state of light is controlled by the electric signals to realize image display.
In the prior art, in a pixel design based on a voltage division type shared capacitor, two sub-pixel electrodes are respectively controlled by two thin film transistors connected with a main scanning line to be charged, another thin film transistor is connected with a sub-scanning line, a voltage division capacitor and one of the sub-pixel electrodes, and the voltage division capacitor is formed by two metal electrodes.
Because the metal electrode of the voltage division capacitor connected with the thin film transistor can not discharge, when the voltage is refreshed from different gray scales to another fixed gray scale, the voltage difference of the two sub-pixel electrodes is different due to different initial potentials of the metal electrode, thereby influencing the color cast of the liquid crystal display panel under the oblique viewing angle and reducing the wide viewing angle taste of the liquid crystal display panel.
Disclosure of Invention
The invention provides an array substrate, a liquid crystal display panel and a liquid crystal display, which can improve the wide-viewing-angle taste of the liquid crystal display panel.
The invention provides an array substrate, comprising: the pixel comprises a scanning line, a data line, a common electrode main line, a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor, wherein the scanning line and the data line are arranged in a staggered mode and define a pixel area, the common electrode main line is located in the pixel area and divides the pixel area into a first sub-pixel area and a second sub-pixel area, a first sub-pixel electrode and a voltage division capacitor are arranged in the first sub-pixel area, a second sub-pixel electrode is arranged in the second sub-pixel area, the voltage division capacitor is composed of a first voltage division electrode and a second voltage division electrode which are arranged in an overlapped mode, and the first voltage division electrode is communicated with the common electrode main line;
the scanning line comprises a main scanning line and an auxiliary scanning line which are arranged in a close proximity mode, the grids of the first thin film transistor, the second thin film transistor and the fourth thin film transistor are respectively connected with the main scanning line, the grid of the third thin film transistor is connected with the auxiliary scanning line, the source drain of the first thin film transistor is respectively connected with the data line and the first sub-pixel electrode, the source drain of the second thin film transistor is respectively connected with the data line and the second sub-pixel electrode, the source drain of the third thin film transistor is respectively connected with the second sub-pixel electrode and the second voltage dividing electrode, and the source drain of the fourth thin film transistor is respectively connected with the first voltage dividing electrode and the second voltage dividing electrode.
In the array substrate, the second voltage-dividing electrode, the data line, and the source/drain electrode of the fourth thin film transistor are formed by a second metal layer disposed on the same layer, the first voltage-dividing electrode, the scan line, and the common electrode main line are formed by a first metal layer disposed on the same layer, the second metal layer is located above the first metal layer, the first metal layer and the second metal layer are separated by a gate insulating layer, and the second metal layer is covered by a passivation layer.
According to the array substrate, the gate insulating layer is provided with a first via hole, and the source or the drain of the fourth thin film transistor is communicated with the second voltage division electrode through the first via hole.
The array substrate as described above, the passivation layer is provided with a second via hole, the second via hole is located above the second metal layer communicated with the source or the drain of the fourth thin film transistor, the passivation layer and the gate insulating layer are provided with a third via hole, the third via hole is located above the first metal layer communicated with the first voltage dividing electrode, and the second via hole and the third via hole are conducted through a conductive layer covering the passivation layer.
In the array substrate, the conductive layer is in the same layer as but not connected to the first subpixel electrode and the second subpixel electrode.
In the array substrate, the conductive layer, the first subpixel electrode, and the second subpixel electrode are ITO.
In the array substrate, the first subpixel electrode and the second subpixel electrode have different areas.
In the array substrate, the array substrate is further provided with a common electrode branch line, and the common electrode branch line is communicated with the common electrode main line.
The invention further provides a liquid crystal display panel, which comprises a color film substrate and the array substrate, wherein the color film substrate and the array substrate are arranged oppositely, and a liquid crystal molecular layer is arranged between the color film substrate and the array substrate.
Still another aspect of the present invention provides a liquid crystal display including the liquid crystal display panel as described above.
The invention provides an array substrate, a liquid crystal display panel and a liquid crystal display.A thin film transistor is additionally arranged on the array substrate, a grid electrode of the thin film transistor is connected with a sub-scanning line, a source electrode and a drain electrode are respectively connected with a first voltage division electrode and a second voltage division electrode, so that the second voltage division electrode of the voltage division capacitor is discharged to the potential of the first voltage division electrode, namely the potential of a common electrode before the second sub-pixel electrode charges and discharges the voltage division capacitor, and the initial potential of the second voltage division electrode of the voltage division capacitor is consistent before refreshing from different gray scales to another fixed gray scale, so that the voltage difference between the first sub-pixel electrode and the second sub-pixel electrode is consistent, and the wide-viewing angle taste of the liquid crystal display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.
Fig. 1 is a schematic structural diagram of an array substrate provided in the prior art;
fig. 2 is a simplified circuit diagram of an array substrate provided in the prior art;
fig. 3 is a schematic voltage variation diagram of an array substrate provided in the prior art under simulation condition 1;
FIG. 4 is a timing diagram corresponding to FIG. 3;
fig. 5 is a schematic voltage variation diagram of an array substrate provided in the prior art under simulation condition 2;
FIG. 6 is a timing diagram corresponding to FIG. 5;
fig. 7 is a simplified circuit diagram of an array substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
FIG. 9 is a schematic cross-sectional view of the first via in FIG. 8;
fig. 10 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;
FIG. 11 is a schematic cross-sectional view of the second and third vias of FIG. 10;
fig. 12 is a schematic voltage variation diagram of an array substrate provided in this embodiment under simulation condition 1;
FIG. 13 is a timing diagram corresponding to FIG. 12;
fig. 14 is a schematic voltage variation diagram of the array substrate provided in this embodiment under simulation condition 2;
fig. 15 is a timing diagram corresponding to fig. 14.
Reference numerals:
11-main scanning line; 12-sub scan line; 13-a data line; 14-a first subpixel electrode; 15-a second subpixel electrode; 16-a common electrode main line; 17-common electrode branch line; 18-a first voltage-dividing electrode; 19-a second voltage-dividing electrode;
21-a first metal layer; 22-a second metal layer;
31-an insulating layer; 32-a passivation layer; 33-a conductive layer; 34-a first via; 35-a second via; 36-a third via;
t1-a first thin film transistor; t2-a second thin film transistor; t3-a third thin film transistor; t4-a fourth thin film transistor;
clc-liquid crystal capacitance; cst — storage capacitance; a Cbuf-voltage dividing capacitor; vcom — common electrode voltage.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of an array substrate provided in the prior art, and fig. 2 is a simplified circuit diagram of the array substrate provided in the prior art. Referring to fig. 1 and 2, it should be understood that an array substrate provided by the prior art includes: a scan line, a data line 13, a common electrode main line 16, a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3. The scanning lines and the data lines 13 are arranged in a staggered mode to define a pixel area, the common electrode main line 16 is located in the pixel area and divides the pixel area into a first sub-pixel area and a second sub-pixel area, a first sub-pixel electrode 14 and a voltage division capacitor Cbuf are arranged in the first sub-pixel area, a second sub-pixel electrode 15 is arranged in the second sub-pixel area, and the voltage division capacitor is composed of a first voltage division electrode 18 and a second voltage division electrode 19 which are arranged in an overlapped mode.
The scanning line comprises a main scanning line 11 and a sub-scanning line 12 which are arranged in close proximity, the grids of a first thin film transistor T1 and a second thin film transistor T2 are respectively connected with the main scanning line 11, the grid of a third thin film transistor T3 is connected with the sub-scanning line 12, the source drain of the first thin film transistor T1 is respectively connected with a data line 13 and a first sub-pixel electrode 14, the source drain of the second thin film transistor T2 is respectively connected with the data line 13 and a second sub-pixel electrode 15, and the source drain of the third thin film transistor T3 is respectively connected with the second sub-pixel electrode 15 and a second sub-pixel electrode 19.
The working principle of the array substrate is that when the sub-scanning line 12 is disconnected and the main scanning line 11 is opened, the first thin film transistor T1 and the second thin film transistor T2 work to respectively charge the first sub-pixel electrode 14 and the second sub-pixel electrode 15; after the main scanning line 11 is powered off, the sub-scanning line 12 is turned on, and the electric quantity stored in the second subpixel electrode 15 is discharged to the voltage dividing capacitor Cbuf under the action of the third thin film transistor T3. Therefore, the voltage of the first sub-pixel electrode 14 is greater than the voltage of the second sub-pixel electrode 15, and the voltage difference between the two electrodes enables the liquid crystal panel to realize multi-domain display, thereby realizing wide-viewing-angle display of the liquid crystal display panel.
Fig. 3 is a schematic diagram of voltage variation of an array substrate under simulation condition 1 according to the prior art, and fig. 4 is a timing diagram corresponding to fig. 3. The simulation condition 1 is a refresh from an L255 negative frame (0.2V) to an L255 positive frame (15.2V), and the charging simulation of the scheme in the prior art described above is performed under the simulation condition 1 to obtain the voltage value changes of the first subpixel electrode 14, the second subpixel electrode 15, and the second subpixel electrode 19 shown in fig. 3, and the timing chart shown in fig. 4 can be obtained from fig. 3. Note that, in fig. 3, a solid line represents the second voltage dividing electrode 19, a dot-dash line represents the first sub-pixel electrode 14, and a broken line represents the second sub-pixel electrode 15. In FIG. 3, the voltage at A1 is 0.2V, the voltage at A2 is 14.61V, the time difference between A3 and A4 is 0, and the voltage difference is 2.02V. As a result of the simulation under simulation condition 1, the holding voltage difference between the first subpixel electrode 14 and the second subpixel electrode 15 was 2.02V.
Fig. 5 is a schematic diagram of voltage variation of an array substrate under simulation condition 2 according to the prior art, and fig. 6 is a timing diagram corresponding to fig. 5. The simulation condition 2 is from L0 (7.04V) refresh to L255 positive frame (15.2V), and the charging simulation of the scheme in the prior art is performed under the simulation condition 2, so that the voltage value changes of the first subpixel electrode 14, the second subpixel electrode 15, and the second voltage-dividing electrode 19 shown in fig. 5 are obtained, and the timing chart shown in fig. 6 can be obtained from fig. 5. Note that, in fig. 5, a solid line represents the second voltage dividing electrode 19, a dot-dash line represents the first sub-pixel electrode 14, and a broken line represents the second sub-pixel electrode 15. In FIG. 5, the voltage at B1 is 7.04V, the voltage at B2 is 14.62V, the time difference between B3 and B4 is 0, and the voltage difference is 1.0V. As a result of simulation under simulation condition 2, the holding voltage difference between the first subpixel electrode 14 and the second subpixel electrode 15 was 1.0V.
As can be seen from the analysis of fig. 3 to fig. 6, the second voltage-dividing electrode 19 of the voltage-dividing capacitor Cbuf cannot discharge, and when the refresh is performed from a different gray level to another fixed gray level, the difference in the holding voltages of the first sub-pixel electrode 14 and the second sub-pixel electrode 15 cannot be kept consistent due to the different initial potentials of the second voltage-dividing electrode 19 of the voltage-dividing capacitor Cbuf, so that the color shift of the liquid crystal display panel at the oblique viewing angle is affected, and the wide viewing angle quality of the liquid crystal display panel is reduced.
Based on the above problems, the present invention provides an array substrate, a liquid crystal display panel and a liquid crystal display, wherein a thin film transistor is additionally disposed to discharge a second voltage dividing electrode of a voltage dividing capacitor to a potential of a first voltage dividing electrode, that is, a potential of a common electrode, before a second sub-pixel electrode charges and discharges the voltage dividing capacitor, so that initial potentials of the second voltage dividing electrode of the voltage dividing capacitor are consistent before refreshing from a different gray scale to another fixed gray scale, and thus voltage difference between the first sub-pixel electrode and the second sub-pixel electrode is consistent, thereby improving wide-viewing angle quality of the liquid crystal display panel.
The structure of the array substrate provided by the present invention is specifically described below with reference to the accompanying drawings and specific embodiments.
Fig. 7 is a simplified circuit diagram of an array substrate according to an embodiment of the present disclosure, fig. 8 is a schematic structural diagram of the array substrate according to the embodiment of the present disclosure, and fig. 9 is a schematic cross-sectional diagram of a first via in fig. 8. Referring to fig. 7 to 9, the present invention provides an array substrate, including: the pixel structure comprises a scanning line, a data line 13, a common electrode main line 16, a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3 and a fourth thin film transistor T4, wherein the scanning line and the data line 13 are arranged in a staggered mode and define a pixel area, the common electrode main line 16 is located in the pixel area and divides the pixel area into a first sub-pixel area and a second sub-pixel area, a first sub-pixel electrode 14 and a voltage division capacitor Cbuf are arranged in the first sub-pixel area, a second sub-pixel electrode 15 is arranged in the second sub-pixel area, the voltage division capacitor is composed of a first voltage division electrode 18 and a second voltage division electrode 19 which are arranged in an overlapped mode, and the first voltage division electrode 18 is communicated with the common electrode main line 16.
The scanning line comprises a main scanning line 11 and a sub-scanning line 12 which are arranged in close proximity, the grids of a first thin film transistor T1, a second thin film transistor T2 and a fourth thin film transistor T4 are respectively connected with the main scanning line 11, the grid of a third thin film transistor T3 is connected with the sub-scanning line 12, the source and drain of the first thin film transistor T1 are respectively connected with a data line 13 and a first sub-pixel electrode 14, the source and drain of the second thin film transistor T2 are respectively connected with the data line 13 and a second sub-pixel electrode 15, the source and drain of the third thin film transistor T3 are respectively connected with the second sub-pixel electrode 15 and a second voltage dividing electrode 19, and the source and drain of the fourth thin film transistor T4 are respectively connected with the first voltage dividing electrode 18 and the second voltage dividing electrode 19.
The areas of the first subpixel electrode 14 and the second subpixel electrode 15 affect the size of the liquid crystal capacitor Clc, and the areas of the first subpixel electrode 14 and the second subpixel electrode 15 may be set to be different, so as to facilitate multi-domain display of the liquid crystal display panel. The first subpixel electrode 14 and the second subpixel electrode 15 may be made of a transparent conductive material, such as Indium Tin Oxide (ITO).
The common electrode main line 16 is used to form a storage capacitor Cst with the first and second subpixel electrodes 14 and 15. The array substrate is further provided with a common electrode branch line 17, and the common electrode branch line 17 is communicated with the common electrode main line 16 to increase the size of the storage capacitor Cst.
According to the array substrate provided by the embodiment of the application, the fourth thin film transistor T4 is additionally arranged, the grid electrode of the fourth thin film transistor T4 is connected with the sub-scanning line 12, and the source electrode and the drain electrode are respectively connected with the first voltage dividing electrode 18 and the second voltage dividing electrode 19. Note that the source and drain of the fourth thin film transistor T4 are connected to the first voltage dividing electrode 18 and the second voltage dividing electrode 19, respectively, which means that the source of the fourth thin film transistor T4 is connected to the first voltage dividing electrode 18 and the drain is connected to the second voltage dividing electrode 19, or the source of the fourth thin film transistor T4 is connected to the second voltage dividing electrode 19 and the drain is connected to the first voltage dividing electrode 18.
The working principle of the array substrate is that when the sub-scanning line 12 is disconnected and the main scanning line 11 is turned on, the first thin film transistor T1 and the second thin film transistor T2 work to respectively charge the first sub-pixel electrode 14 and the second sub-pixel electrode 15, and the fourth thin film transistor T4 works to discharge the second voltage division electrode 19, and the first voltage division electrode 18 is communicated with the common electrode main line 16 and the common electrode branch line 17, so that the second voltage division electrode 19 can be discharged to the potential of the common electrode voltage Vcom; after the main scanning line 11 is powered off, the sub-scanning line 12 is turned on, and the electric quantity stored in the second subpixel electrode 15 is discharged to the voltage dividing capacitor Cbuf under the action of the third thin film transistor T3.
When the liquid crystal display panel is refreshed from different gray scales to a certain fixed gray scale, the initial potentials of the second voltage-dividing electrodes 19 of the voltage-dividing capacitors Cbuf are consistent and are both the common electrode voltage Vcom, so that the voltage difference between the first sub-pixel electrodes 14 and the second sub-pixel electrodes 15 is always consistent, and on the basis of realizing wide-viewing-angle display of the liquid crystal display panel, the color cast at an oblique viewing angle can be improved, thereby realizing the effect of improving the wide-viewing-angle taste of the liquid crystal display panel.
In the embodiment of the present invention, the second voltage division electrode 19, the data line 13, and the source and drain electrodes of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 may be formed in the same process, and are the second metal layer 22 disposed on the same layer; the first voltage dividing electrode 18, the main scanning line 11, the sub-scanning line 12, the common electrode main line 16, the common electrode branch line 17, and the gates of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 may be formed in the same process as the first metal layer 21 disposed on the same layer.
The manufacturing process of the array substrate can be as follows, in the first step, metal wires of a grid electrode, a main scanning line 11, a sub-scanning line 12, a common electrode main line 16, a common electrode branch line 17 and a first voltage division electrode 18 are formed on a substrate; second, a gate insulating layer 31 is deposited; thirdly, forming metal wires of a source electrode, a drain electrode, a data wire 13 and a second voltage division electrode 19; fourthly, depositing a passivation layer 32, and forming a via hole above a preset position of the passivation layer 32, such as a source electrode or a drain electrode; and fifthly, covering the indium tin oxide layer to form a first sub-pixel electrode 14 and a second sub-pixel electrode 15, and communicating the source drain electrode and the pixel electrode through the through hole. The gate insulating layer 31 serves to separate the first metal layer 21 from the second metal layer 22, and the passivation layer 32 covers the second metal layer 22 to separate the second metal layer 22 from the pixel electrode layer.
The source-drain connection of the added fourth thin film transistor T4 may be implemented in various ways, and because the source-drain of the fourth thin film transistor T4 and the second voltage dividing electrode 19 are formed in the same process, one of the source-drain may be directly connected to the second voltage dividing electrode 19, and the other of the source-drain and the first voltage dividing electrode 18 are in different layers, and may be electrically connected by means of a conductive via.
With continued reference to fig. 8 and 9, in one possible embodiment, a first via 34 is disposed on the gate insulating layer 31, the first via 34 is located above the first metal layer 21 communicating with the first voltage-dividing electrode 19, and the source or drain of the fourth thin film transistor T4 communicates with the second voltage-dividing electrode 19 through the first via 34.
Fig. 10 is another schematic structural diagram of an array substrate according to an embodiment of the present application, and fig. 11 is a schematic cross-sectional diagram of a second via and a third via in fig. 10. Referring to fig. 10 and 11, in another possible embodiment, a second via 35 is disposed on the passivation layer 32, the second via 35 is located above the second metal layer 22 communicating with the source or drain of the fourth thin film transistor T4, a third via 36 is disposed on the passivation layer 32 and the gate insulating layer 31, the third via 36 is located above the first metal layer 21 communicating with the first voltage-dividing electrode 18, and the second via 35 and the third via 36 are conducted through the conductive layer 33 covering the passivation layer 32.
The conductive layer 33 is in the same layer as the first subpixel electrode 14 and the second subpixel electrode 15 but not connected to the first subpixel electrode 14 and the second subpixel electrode 15, and the conductive layer 33 may be ITO formed in the same process as the first subpixel electrode 14 and the second subpixel electrode 15.
Fig. 12 is a schematic voltage change diagram of the array substrate provided in the embodiment of the present application under a simulation condition 1, fig. 13 is a timing chart corresponding to fig. 12, where the simulation condition 1 is refreshing from an L255 negative frame (0.2V) to an L255 positive frame (15.2V), and a charging simulation is performed on the scheme in the prior art under the simulation condition 1 to obtain voltage changes of the first subpixel electrode 14, the second subpixel electrode 15, and the second subpixel electrode 19 shown in fig. 12, and the timing chart shown in fig. 13 can be obtained according to fig. 12. Note that, in fig. 12, a solid line represents the second voltage dividing electrode 19, a dot-dash line represents the first sub-pixel electrode 14, and a broken line represents the second sub-pixel electrode 15. In fig. 12, the voltage at C1 is 7.04v, the voltage at C2 is 13.67v, the time difference between C3 and C4 is 0, and the voltage difference is 1.53V. In the variation of the broken line of the second voltage dividing electrode 19 in fig. 13, the portion circled by the broken line represents the early discharge to Vcom of the second voltage dividing electrode 19. As a result of the simulation under simulation condition 1, the holding voltage difference between the first subpixel electrode 14 and the second subpixel electrode 15 was 1.53V.
Fig. 14 is a schematic voltage change diagram of the array substrate provided in the embodiment of the present application under simulation condition 2, fig. 15 is a timing chart corresponding to fig. 14, where simulation condition 2 is from L0 (7.04V) to L255 positive frame (15.2V), and the charging simulation is performed on the scheme in the prior art under simulation condition 2 to obtain voltage changes of the first subpixel electrode 14, the second subpixel electrode 15, and the second subpixel electrode 19 shown in fig. 14, and the timing chart shown in fig. 15 can be obtained according to fig. 14. Note that, in fig. 14, a solid line represents the second voltage dividing electrode 19, a dot-dash line represents the first sub-pixel electrode 14, and a broken line represents the second sub-pixel electrode 15. In FIG. 15, the voltage at D1 is 7.04V, the voltage at D2 is 13.67V, the time difference between D3 and D4 is 0, and the voltage difference is 1.53V. As a result of the simulation under simulation condition 2, the holding voltage difference between the first subpixel electrode 14 and the second subpixel electrode 15 was 1.53V.
As can be seen from the analysis of fig. 12 to fig. 15, the second voltage-dividing electrode 19 of the voltage-dividing capacitor Cbuf can discharge to Vcom in advance, and when the different gray scales are refreshed to another fixed gray scale, the initial potentials of the second voltage-dividing electrode 19 of the voltage-dividing capacitor Cbuf are the same, so that the voltage difference between the first sub-pixel electrode 14 and the second sub-pixel electrode 15 is kept consistent, thereby improving the color shift of the lcd panel at the oblique viewing angle and improving the wide viewing angle quality of the lcd panel.
The array substrate provided by the invention is additionally provided with the thin film transistor, the grid electrode of the thin film transistor is connected with the sub-scanning line, the source electrode and the drain electrode are respectively connected with the first voltage division electrode and the second voltage division electrode, so that the second voltage division electrode of the voltage division capacitor is discharged to the potential of the first voltage division electrode, namely the potential of the common electrode before the second sub-pixel electrode carries out charging and discharging on the voltage division capacitor, and the initial potential of the second voltage division electrode of the voltage division capacitor is consistent before the second sub-pixel electrode refreshes to another fixed gray scale from different gray scales, so that the voltage difference between the first sub-pixel electrode and the second sub-pixel electrode is consistent, and the wide-view-angle taste of the liquid crystal display panel is improved.
The embodiment of the invention also provides a liquid crystal display panel, which comprises a color film substrate and the array substrate, wherein the color film substrate and the array substrate are arranged oppositely, and a liquid crystal molecular layer is arranged between the color film substrate and the array substrate.
The embodiment of the invention also provides a liquid crystal display which comprises the liquid crystal display panel provided by the embodiment.
In the description of the present invention, it is to be understood that the terms "center", "length", "width", "thickness", "top", "bottom", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "inner", "outer", "axial", "circumferential", and the like, are used to indicate an orientation or positional relationship based on that shown in the drawings, merely to facilitate the description of the invention and to simplify the description, and do not indicate or imply that the position or element referred to must have a particular orientation, configuration and operation at 100, and therefore, should not be construed as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; may be mechanically coupled, may be electrically coupled, or may be in communication with each other; either directly or indirectly through intervening media, such as through internal communication or through an interaction between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless expressly stated or limited otherwise, the recitation of a first feature "on" or "under" a second feature may include the recitation of the first and second features being in direct contact, and may also include the recitation that the first and second features are not in direct contact, but are in contact via another feature between them. Also, the first feature "on," "above" and "over" the second feature may include the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. An array substrate, comprising: the pixel comprises a scanning line, a data line, a common electrode main line, a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor, wherein the scanning line and the data line are arranged in a staggered mode and define a pixel area, the common electrode main line is located in the pixel area and divides the pixel area into a first sub-pixel area and a second sub-pixel area, a first sub-pixel electrode and a voltage division capacitor are arranged in the first sub-pixel area, a second sub-pixel electrode is arranged in the second sub-pixel area, the voltage division capacitor is composed of a first voltage division electrode and a second voltage division electrode which are arranged in an overlapped mode, and the first voltage division electrode is communicated with the common electrode main line;
the scanning line comprises a main scanning line and an auxiliary scanning line which are arranged next to each other, the grids of the first thin film transistor, the second thin film transistor and the fourth thin film transistor are respectively connected with the main scanning line, the grid of the third thin film transistor is connected with the auxiliary scanning line, the source and drain of the first thin film transistor are respectively connected with the data line and the first sub-pixel electrode, the source and drain of the second thin film transistor are respectively connected with the data line and the second sub-pixel electrode, the source and drain of the third thin film transistor are respectively connected with the second sub-pixel electrode and the second voltage dividing electrode, and the source and drain of the fourth thin film transistor are respectively connected with the first voltage dividing electrode and the second voltage dividing electrode;
the second voltage division electrode, the data line and the source and drain electrodes of the fourth thin film transistor are second metal layers arranged on the same layer, the first voltage division electrode, the scanning line and the common electrode main line are first metal layers arranged on the same layer, the second metal layers are positioned above the first metal layers, the first metal layers and the second metal layers are separated through a grid electrode insulating layer, and a passivation layer covers the second metal layers;
the gate insulating layer is provided with a first through hole, the first through hole is positioned above a first metal layer communicated with the first voltage division electrode, and a source electrode or a drain electrode of the fourth thin film transistor is communicated with the second voltage division electrode through the first through hole.
2. The array substrate of claim 1, wherein a second via is disposed on the passivation layer and located above the second metal layer in communication with a source or drain of the fourth thin film transistor, and a third via is disposed on the passivation layer and the gate insulating layer and located above the first metal layer in communication with the first voltage divider electrode, the second and third vias being conducted through a conductive layer overlying the passivation layer.
3. The array substrate of claim 2, wherein the conductive layer is in the same layer as but not in communication with the first and second subpixel electrodes.
4. The array substrate of claim 3, wherein the conductive layer, the first subpixel electrode, and the second subpixel electrode are ITO.
5. The array substrate of claim 1, wherein the first subpixel electrode and the second subpixel electrode have different areas.
6. The array substrate of claim 1, wherein a common electrode branch line is further disposed on the array substrate, and the common electrode branch line is in communication with the common electrode main line.
7. A liquid crystal display panel is characterized by comprising a color film substrate and an array substrate according to any one of claims 1-6 which are arranged oppositely, wherein a liquid crystal molecular layer is arranged between the color film substrate and the array substrate.
8. A liquid crystal display comprising the liquid crystal display panel according to claim 7.
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