CN113192990A - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
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- CN113192990A CN113192990A CN202110621148.7A CN202110621148A CN113192990A CN 113192990 A CN113192990 A CN 113192990A CN 202110621148 A CN202110621148 A CN 202110621148A CN 113192990 A CN113192990 A CN 113192990A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The embodiment of the invention discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate includes: a substrate; a first gate insulating layer on one side of the substrate; the first semiconductor layer is positioned on one side, close to the substrate, of the first grid insulating layer, and the grid layer is positioned on one side, far away from the substrate, of the second grid insulating layer; or the first semiconductor layer is positioned on one side of the second grid insulating layer far away from the substrate, the grid layer is positioned on one side of the first grid insulating layer near the substrate, and the second semiconductor layer is positioned between the first grid insulating layer and the second grid insulating layer. According to the technical scheme provided by the embodiment of the invention, the distance between the first semiconductor layer and the second semiconductor layer can be greatly reduced by arranging the double-layer grid electrode insulating layer, the number of mask processes can be saved in the process of forming the thin film transistor on the array substrate, and the production cost is favorably reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display panel.
Background
With the rapid development of display technology, the trend of high integration and low cost of display devices is developed.
The Low Temperature Poly-Oxide (LTPO) technology is a new thin film transistor technology in recent years, but the LTPO technology is complex in process and has a large number of patterning processes, which is not beneficial to reducing the production cost of the array substrate.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a manufacturing method thereof and a display panel, which are used for simplifying the composition process of the array substrate so as to reduce the production cost of the array substrate.
In a first aspect, an embodiment of the present invention provides an array substrate, including:
a substrate;
a first gate insulating layer on one side of the substrate;
the second grid electrode insulating layer is positioned on one side, far away from the substrate, of the first grid electrode insulating layer and is in contact with the first grid electrode insulating layer;
the first semiconductor layer is positioned on one side, close to the substrate, of the first grid insulating layer, the first grid insulating layer covers the first semiconductor layer, and the grid layer is positioned on one side, far away from the substrate, of the second grid insulating layer and is in contact with the second grid insulating layer; alternatively, the first and second electrodes may be,
the first semiconductor layer is positioned on one side, far away from the substrate, of the second grid insulating layer, the grid layer is positioned on one side, close to the substrate, of the first grid insulating layer, and the first grid insulating layer covers the grid layer;
a second semiconductor layer between the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer covers the second semiconductor layer; wherein the first semiconductor layer and the second semiconductor layer are different in material.
Optionally, the material of the first semiconductor layer includes polysilicon, the material of the second semiconductor layer includes metal oxide, the first semiconductor layer includes a first active layer, the second semiconductor layer includes a second active layer, and an orthographic projection of the first active layer on the substrate does not overlap with an orthographic projection of the second active layer on the substrate.
Optionally, when the first semiconductor layer is located on a side of the first gate insulating layer close to the substrate, and the first gate insulating layer covers the first semiconductor layer, the gate layer is located on a side of the second gate insulating layer away from the substrate, and is in contact with the second gate insulating layer;
the array substrate further includes:
a first interlayer insulating layer; the gate layer is positioned on one side of the gate layer, which is far away from the substrate, and covers the gate layer;
the source drain layer is positioned on one side, far away from the substrate, of the first interlayer insulating layer and comprises a first source drain layer and a second source drain layer, and the first source drain layer and the second source drain layer are arranged on the same layer;
the first source drain layer is in contact with the first semiconductor layer through a first through hole penetrating through the first interlayer insulating layer; the second source drain layer is in contact with the second semiconductor layer through a second via hole penetrating through the first interlayer insulating layer.
Optionally, the gate layers include a first gate layer and a second gate layer, and the first gate layer and the second gate layer are disposed on the same layer; an orthographic projection of the first gate layer on the substrate falls within an orthographic projection of the first semiconductor layer on the substrate, and an orthographic projection of the second gate layer on the substrate falls within an orthographic projection of the second semiconductor layer on the substrate.
Optionally, the array substrate further includes a capacitor electrode layer, the capacitor electrode layer includes a first electrode layer and a second electrode layer, the first electrode layer and the second gate layer are shared, and the second electrode layer is located on one side of the first interlayer insulating layer, which is far away from the substrate, and is disposed on the same layer as the source/drain electrode layer.
Optionally, an orthographic projection of the first electrode layer on the substrate covers an orthographic projection of the second electrode layer on the substrate.
Optionally, a second interlayer insulating layer, a third interlayer insulating layer, a planarization layer, and a plurality of connection electrode layers are further included;
the second interlayer insulating layer is positioned on one side, away from the substrate, of the source drain electrode layer, the connecting electrode layer is positioned on one side, away from the substrate, of the second interlayer insulating layer, the plurality of connecting electrode layers are arranged on the same layer, and each connecting electrode layer is respectively in contact with the first source drain electrode layer and the second source drain electrode layer through third through holes penetrating through the second interlayer insulating layer;
the third interlayer insulating layer and the planarization layer are sequentially stacked on one side, away from the substrate, of the connection electrode layer.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing an array substrate, where the method for manufacturing an array substrate includes: providing a substrate;
forming a first semiconductor layer on one side of the substrate;
a first grid electrode insulating layer and a second semiconductor layer are sequentially formed on one side, away from the substrate, of the first semiconductor layer, and the first grid electrode insulating layer covers the first semiconductor layer;
forming a second gate insulating layer on one side, far away from the substrate, of the first gate insulating layer, wherein the second gate insulating layer is in contact with the first gate insulating layer, and the second gate insulating layer covers the second semiconductor layer;
and forming a gate layer on one side of the second gate insulating layer, which is far away from the substrate, wherein the gate layer is in contact with the second gate insulating layer.
Optionally, the manufacturing method of the array substrate includes:
providing a substrate;
forming a gate layer on one side of the substrate;
a first grid electrode insulating layer and a second semiconductor layer are sequentially formed on one side, away from the substrate, of the grid electrode layer, and the first grid electrode insulating layer covers the grid electrode layer;
forming a second gate insulating layer on one side, far away from the substrate, of the first gate insulating layer, wherein the second gate insulating layer is in contact with the first gate insulating layer, and the second gate insulating layer covers the second semiconductor layer;
and forming a first semiconductor layer on one side of the second grid insulating layer, which is far away from the substrate, wherein the first semiconductor layer is in contact with the second grid insulating layer.
In a third aspect, an embodiment of the present invention further provides a display panel, including the array substrate provided in any embodiment of the present invention.
According to the technical scheme provided by the embodiment of the invention, a protective layer is not required to be arranged between the first semiconductor layer and the second semiconductor layer by arranging the double-layer grid insulating layer, so that the second semiconductor layer is positioned between the first grid insulating layer and the second grid insulating layer, the first semiconductor layer and the second semiconductor layer can share the second grid insulating layer, the first thin film transistor formed by the first semiconductor layer is of a double-layer grid insulating layer structure, the second thin film transistor formed by the second semiconductor layer is of a single-layer grid insulating layer structure, the distance between the first semiconductor layer and the second semiconductor layer can be greatly reduced, and the film thickness between the two thin film transistors is also reduced. In the process of forming the thin film transistor on the array substrate, the number of the mask plates can be saved, and the production cost is favorably reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of an array substrate in the prior art;
fig. 2 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of another array substrate according to an embodiment of the invention;
fig. 4 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention;
fig. 5 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the invention;
fig. 6 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 7 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the invention;
FIGS. 8-19 are schematic diagrams of specific structures formed in response to method steps of an array substrate;
fig. 20 is a schematic cross-sectional view of another array substrate according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, the array substrate has a plurality of thin film transistors arranged in an array, the patterning process of the array substrate is complicated, and the number of masks required to form the array substrate is large, so that the production cost of the array substrate is high. Fig. 1 is a schematic cross-sectional structure of an array substrate in the prior art, and referring to fig. 1, the array substrate in the prior art includes a substrate 10, a first semiconductor layer 22 and a first insulating layer 20 on the substrate, a first gate 22 and a lower plate 41 of a capacitor are disposed on an upper surface of the first insulating layer 20, a first interlayer insulating layer 30 covers the first insulating layer 20, and a contact electrode connected to the first semiconductor layer 22 and an upper plate 42 of the capacitor are formed on a side of the first interlayer insulating layer 30 away from the substrate 10. The semiconductor device further comprises a protective layer 40 arranged on the first interlayer insulating layer 30, and a second semiconductor layer 31, a second insulating layer 32 and a second grid 33 which are sequentially stacked on one side, away from the substrate 10, of the protective layer 40, wherein the second interlayer insulating layer 50 covers the second grid 33. The first semiconductor layer 21, the first insulating layer 20, and the first gate electrode 21 constitute a first transistor, and the second semiconductor layer 31, the second insulating layer 32, and the second gate electrode 33 constitute a second transistor. In the prior art, at least 7 patterning processes are required from the substrate 10 to the second interlayer insulating layer 50, and the processes are complex, which is not favorable for reducing the production cost of the array substrate.
In view of the foregoing problems, embodiments of the present invention provide an array substrate to reduce the number of patterning processes. Fig. 2 is a schematic cross-sectional structure view of an array substrate according to an embodiment of the present invention, and referring to fig. 2, the array substrate according to the embodiment of the present invention includes: a substrate 100; a first gate insulating layer 200 on one side of the substrate 100; the second gate insulating layer 300 is located on a side of the first gate insulating layer 200 away from the substrate 100, and is in contact with the first gate insulating layer 200.
A first semiconductor layer 101 and a gate electrode layer 110, wherein the first semiconductor layer 101 is located on one side of the first gate insulating layer 200 close to the substrate 100, the first gate insulating layer 200 covers the first semiconductor layer 101, and the gate electrode layer 110 is located on one side of the second gate insulating layer 300 away from the substrate 100 and is in contact with the second gate insulating layer 300; a second semiconductor layer 201 between the first gate insulating layer 200 and the second gate insulating layer 300, and the second gate insulating layer 300 covering the second semiconductor layer 201; the materials of the first semiconductor layer 101 and the second semiconductor layer 201 are different.
Specifically, the substrate 100 may be flexible, may be formed of any insulating material having flexibility, and the substrate 100 may also be rigid, such as a glass substrate. The first semiconductor layer 101 is disposed on the substrate 100, and a first gate insulating layer 200 is disposed on a side of the first semiconductor layer 101 away from the substrate 100, and the first gate insulating layer 200 covers the first semiconductor layer 101. A second semiconductor layer 201 is formed on a side of the first gate insulating layer 200 away from the substrate 100, in this embodiment, the first semiconductor layer 101 and the second semiconductor layer 201 are formed in different etching steps due to different materials of the first semiconductor layer 101 and the second semiconductor layer 201, the first gate insulating layer 200 is used for insulating and isolating the first semiconductor layer 101 and the second semiconductor layer 201, and the second gate insulating layer 300 covers the second semiconductor layer 201. The gate layer 110 is disposed on a side of the second gate insulating layer 300 away from the substrate 100.
Doping the first semiconductor layer 101 and the second semiconductor layer 201 may form a source electrode and a drain electrode as a thin film transistor, the first semiconductor layer 101 and the gate layer 110 together form a first thin film transistor, and the second semiconductor layer 201 and the gate layer 110 together form a second thin film transistor. Therefore, the process flow for forming the thin film transistor of the present embodiment at least includes:
in process 1, a substrate 100 is formed.
In process 2, a first semiconductor layer 101 is formed.
In process 3, a first gate insulating layer 200 and a second semiconductor layer 201 are formed.
In process 4, the second gate insulating layer 300 and the gate layer 110 are formed.
It should be noted that, in the process of forming the film pattern and punching the hole in the film, a mask process is required. Therefore, in the above process flow, a mask is required to be used for forming the first semiconductor layer 101, the second semiconductor layer 201, and the gate layer 110.
Referring to fig. 1, a process flow of forming a thin film transistor in the prior art at least includes:
in process 1, a substrate 10 is formed.
In step 2, a first semiconductor layer 21 is formed.
In process 3, a first insulating layer 20 and a first gate 22 are formed.
And 4, forming a first interlayer insulating layer 30 and etching the through hole.
And 5, forming a protective layer 40 and a second semiconductor layer 31.
In process 6, a second insulating layer 32 and a second gate 33 are formed.
As shown in fig. 1 in the prior art, a mask is required to be used when forming the first semiconductor layer 21, the first gate 22, the first interlayer insulating layer, the second semiconductor layer 31, and the second gate 33, so that at least two mask processes can be saved in the process of forming the thin film transistor on the array substrate according to the technical solution provided by the embodiment of the present invention, and the number of masks is correspondingly reduced. And through the form of setting up the double-deck grid insulating layer, need not to set up the protective layer between first semiconductor layer 101 and second semiconductor layer 201, make second semiconductor layer 201 lie between first grid insulating layer 200 and second grid insulating layer 300, can make first semiconductor layer 101 and second semiconductor layer 201 share second grid insulating layer 300, the first thin film transistor that uses first semiconductor layer 101 to form is double-deck grid insulating layer structure, the second thin film transistor that uses second semiconductor layer 201 to form is single-deck grid insulating layer structure, can reduce the distance between first semiconductor layer 101 and second semiconductor layer 201 greatly, the rete thickness between two thin film transistors has also been reduced.
Fig. 3 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention, which is different from the array substrate shown in fig. 2 in that the thin film transistor in the array substrate shown in fig. 3 is a bottom gate structure, and the thin film transistor in fig. 2 is a top gate structure. The film layer structures of the two are the same, and the adopted processes are also the same, so that the thin film transistor with the bottom gate structure is not described in detail herein.
With continued reference to fig. 2, the material of the first semiconductor layer 101 includes polysilicon, the material of the second semiconductor layer 201 includes metal oxide, the first semiconductor layer 101 includes a first active layer, the second semiconductor layer 201 includes a second active layer, and there is no overlap between an orthographic projection of the first active layer on the substrate 100 and an orthographic projection of the second active layer on the substrate 100.
In general, a low temperature polysilicon thin film transistor has high mobility and small size, and a metal oxide thin film transistor has low leakage current and can realize low frequency driving, so that a part of thin film transistors in a pixel circuit of a display area adopt the metal oxide thin film transistor. The technical solution provided by the embodiment of the present invention may be applied to a scan driving circuit in a non-display area, may also be applied to a pixel circuit in a display area, and certainly may also be applied to a scan driving circuit in a non-display area and a pixel circuit in a display area at the same time.
In the embodiment, the array substrate is formed by LTPO technology, the material of the first semiconductor layer 101 includes polysilicon, and the material of the second semiconductor layer 201 includes metal oxide. Since the two materials are different, the first semiconductor layer 101 needs to be subjected to excimer laser annealing in the manufacturing process, and the second semiconductor layer 201 does not need to be subjected to excimer laser annealing, so that the first semiconductor layer 101 and the second semiconductor layer 201 are not disposed on the same layer, and need to be formed in different process steps. Wherein the first semiconductor layer 101 includes a first active layer, and the second semiconductor layer 201 includes a second active layer, which in this embodiment can be understood as the first active layer being the first semiconductor layer 101 and the second active layer being the second semiconductor layer 201; in other embodiments, the first semiconductor layer 101 and the second semiconductor layer 201 may further include a conductor region formed by ion heavily doping to form a metal connection line. The orthographic projection of the first active layer on the substrate 100 and the orthographic projection of the second active layer on the substrate 100 do not overlap, so that the interference between the two active layers is prevented, and the display effect is not facilitated.
The embodiment of the present invention is described by taking a thin film transistor with a top gate structure as an example. Fig. 4 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the present invention, and referring to fig. 4, when the first semiconductor layer 101 is located on a side of the first gate insulating layer 200 close to the substrate 100, the first gate insulating layer 200 covers the first semiconductor layer 101, and the gate layer 110 is located on a side of the second gate insulating layer 300 away from the substrate 100 and contacts with the second gate insulating layer 300, the array substrate further includes:
a first interlayer insulating layer 400; is located on the side of the gate layer 110 away from the substrate 100 and covers the gate layer 110.
The source drain layer is located on one side, far away from the substrate 100, of the first interlayer insulating layer 400, and comprises a first source drain layer 310 and a second source drain layer 320, and the first source drain layer 310 and the second source drain layer 320 are arranged in the same layer; the first source drain layer 310 is in contact with the first semiconductor layer 101 through a first via hole penetrating the first interlayer insulating layer 400; the second source drain layer 320 is in contact with the second semiconductor layer 201 through a second via hole penetrating the first interlayer insulating layer 400.
Specifically, the gate layer 110 includes a first gate layer 102 and a second gate layer 202, and the first gate layer 102 and the second gate layer 202 are disposed at the same layer; an orthogonal projection of the first gate layer 102 on the substrate 100 falls within an orthogonal projection of the first semiconductor layer 101 on the substrate 100, and an orthogonal projection of the second gate layer 202 on the substrate 100 falls within an orthogonal projection of the second semiconductor layer 101 on the substrate 100. The first interlayer insulating layer 400 covers the gate layer 110, and a first via hole and a second via hole are formed in the first interlayer insulating layer 400, and are filled with a conductive material, so that source and drain electrodes on the first semiconductor layer 101 and the second semiconductor layer 201 are led out. The first source drain layer 310 includes a source 31 and a drain 32 of the first thin film transistor, and the second source drain layer 320 includes a source 33 and a drain 34 of the second thin film transistor.
With continued reference to fig. 4, the array substrate further includes a capacitance electrode layer, the capacitance electrode layer includes a first electrode layer 203 and a second electrode layer 204, the first electrode layer 203 is shared with the second gate layer 202, and the second electrode layer 204 is located on a side of the first interlayer insulating layer 400 away from the substrate 100 and is disposed at the same layer as the source/drain electrode layer.
Specifically, the capacitor electrode layer has a first electrode layer 203 and a second electrode layer 204, the first electrode layer 203 and the second electrode layer 204, and a first interlayer insulating layer 400 interposed between the first electrode layer 203 and the second electrode layer 204, which collectively form a storage capacitor, which stores a gate voltage of a driving transistor in a pixel circuit, taking the pixel circuit of the display region as an example. The second electrode layer 204 is configured on the side of the first electrode layer 203 away from the substrate 100 (of course, in other embodiments, the second electrode layer 204 may also be configured on the side of the first electrode layer 203 close to the substrate 100), and the second electrode layer 204 is disposed in the same layer as the source/drain electrode layer. The first electrode layer 203 of the capacitor electrode layer is shared with the second gate layer 202, in other words, the second gate layer 202 is reused as the first electrode layer 203, so that the second gate layer 200 can be used as a gate of a thin film transistor and also as one electrode plate of a storage capacitor, film space on the array substrate can be greatly reduced, more pixel regions can be arranged on the array substrate, and the resolution of the display panel can be improved. Meanwhile, the manufacturing process of the array substrate can be reduced, and the production cost is reduced.
For example, taking the array substrate shown in fig. 4 as an example, the process of forming the thin film transistor and the storage capacitor on the substrate 100 at least includes the following steps:
in process 1, a substrate 100 is formed.
In process 2, a first semiconductor layer 101 is formed.
In process 3, a first gate insulating layer 200 and a second semiconductor layer 201 are formed.
In process 4, the second gate insulating layer 300 and the gate layer 110 are formed.
In process 5, a first interlayer insulating layer 400 is formed.
In the process 6, the second electrode layer 204 of the source drain layer and the capacitance electrode layer is formed.
As shown in fig. 1, the prior art process of forming a thin film transistor and a storage capacitor on a substrate at least includes the following steps:
in process 1, a substrate 10 is formed.
In step 2, a first semiconductor layer 21 is formed.
In the process 3, the first insulating layer 20, the first gate 22 and the capacitor bottom plate 41 are formed.
And 4, forming a first interlayer insulating layer 30 and etching the through hole.
And 5, forming a capacitor upper plate 42 and a first source drain layer.
And 6, forming a protective layer 40 and a second semiconductor layer 31.
Process 7, a second insulating layer 32 and a second gate 33 are formed.
And 8, forming a second source drain layer.
Therefore, compared with the prior art, in the process of forming the thin film transistor and the storage capacitor on the substrate, the technical scheme provided by the embodiment can at least reduce two mask processes, and can greatly reduce the film space on the array substrate by sharing the second gate layer 202 and the first electrode layer 203 of the capacitor electrode layer, thereby being beneficial to arranging more pixel regions and improving the resolution of the display panel.
In the present embodiment, the orthographic projection of the first electrode layer 203 on the substrate 100 covers the orthographic projection of the second electrode layer 204 on the substrate 100. Because the first electrode layer 203 is shared by the second gate layer 202, the size of the first electrode layer 203 is set to be close to the size of the second electrode layer 204 in the thickness direction perpendicular to the thin film transistor, so that the capacitance value of the storage capacitor is increased on the basis of ensuring that the second thin film transistor has good electrical property, and the storage capacity of the storage capacitor is improved.
Fig. 5 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the present invention, and referring to fig. 4 and 5, the array substrate further includes a second interlayer insulating layer 500, a third interlayer insulating layer 600, a planarization layer 700, and a plurality of connection electrode layers 401.
The second interlayer insulating layer 500 is located on one side of the source drain layer away from the substrate 100, the connection electrode layer 401 is located on one side of the second interlayer insulating layer 500 away from the substrate 100, the plurality of connection electrode layers 401 are arranged on the same layer, and each connection electrode layer 401 is respectively contacted with the first source drain layer 310 and the second source drain layer 320 through a third through hole penetrating through the second interlayer insulating layer 500; the third interlayer insulating layer 600 and the planarization layer 700 are stacked in this order on the side of the connection electrode layer 401 away from the substrate 100.
In order to facilitate the routing of metal traces, the first source drain layer 310 and the second source drain layer 320 may be respectively led out to the upper surface of the second interlayer insulating layer 500 through the connection electrode layer 401. The metal wiring includes at least one of a data signal line, a scan signal line and a power signal line.
An embodiment of the present invention further provides a manufacturing method of an array substrate, fig. 6 is a flowchart of the manufacturing method of the array substrate according to the embodiment of the present invention, and referring to fig. 6, the manufacturing method of the array substrate includes:
and S110, providing a substrate.
And S120, forming a first semiconductor layer on one side of the substrate.
S130, sequentially forming a first grid insulating layer and a second semiconductor layer on one side, away from the substrate, of the first semiconductor layer, wherein the first grid insulating layer covers the first semiconductor layer.
And S140, forming a second gate insulating layer on one side of the first gate insulating layer, which is far away from the substrate, wherein the second gate insulating layer is in contact with the first gate insulating layer and covers the second semiconductor layer.
And S150, forming a gate layer on one side, far away from the substrate, of the second gate insulating layer, wherein the gate layer is in contact with the second gate insulating layer.
Referring to fig. 2 and 3, the substrate 100 may be flexible, may be formed of any insulating material having flexibility, and the substrate 100 may also be rigid, such as a glass substrate. A first semiconductor layer 101 is formed on the substrate 100, a first gate insulating layer 200 is formed on a side of the first semiconductor layer 101 away from the substrate 100, and the first gate insulating layer 200 covers the first semiconductor layer 101. The second semiconductor layer 201 is formed on the side of the first gate insulating layer 200 away from the substrate 100, in this embodiment, the first semiconductor layer 101 and the second semiconductor layer 201 are formed in different etching steps due to different materials of the first semiconductor layer 101 and the second semiconductor layer 201, the first gate insulating layer 200 is used for insulating and isolating the first semiconductor layer 101 and the second semiconductor layer 201, the second gate insulating layer 300 covers the second semiconductor layer 201, and the gate layer 110 is formed on the side of the second gate insulating layer 300 away from the substrate 100.
Doping the first semiconductor layer 101 and the second semiconductor layer 201 may form a source electrode and a drain electrode as a thin film transistor, the first semiconductor layer 101 and the gate layer 110 together form a first thin film transistor, and the second semiconductor layer 201 and the gate layer 110 together form a second thin film transistor.
In the present embodiment, the process flow of forming the gate layer 110 on the substrate 100 is as follows:
in process 1, a substrate 100 is formed.
The process 2 is to deposit an amorphous silicon layer on the substrate 100, and polycrystallize the amorphous silicon layer by Excimer Laser Annealing (ELA) to form a polycrystalline silicon layer. The polysilicon layer is then patterned by a photolithography process (using a mask), and the amorphous silicon layer is preferably annealed between the patterning in order to prevent shrinkage dislocation of the amorphous silicon layer due to high temperature. After the patterned polysilicon layer is formed, ion implantation (e.g., phosphorous ion or boron ion) is performed on the polysilicon layer to form the first semiconductor layer 101 by doping, wherein a region of the first semiconductor layer 101 where ions are not implanted forms a first active layer, and a region where ions are implanted forms a source/drain.
In step 3, a first gate insulating layer 200 is formed on the substrate 100, and the first gate insulating layer 200 covers the first semiconductor layer 101, wherein the material of the first gate insulating layer 200 may be silicon oxide and/or silicon nitride. The first gate insulating layer 200 is used as an insulating layer of the first semiconductor layer 101, and in order to improve the film formation quality of the first gate insulating layer 200, the first gate insulating layer 200 may be annealed to achieve the purpose of dehydrogenation and increasing the film density. Then, a metal oxide layer, such as indium gallium zinc oxide, is formed on the first gate insulating layer 200 at a side away from the substrate 100, and the metal oxide layer may be formed by sputtering. After the metal oxide layer is formed, the metal oxide layer is patterned by a photolithography process (a mask is required), after the patterned metal oxide layer is formed, ion implantation (for example, phosphorus ions or boron ions) is performed on the metal oxide layer, and the second semiconductor layer 201 is formed by doping, wherein a region of the second semiconductor layer 201 where ions are not implanted forms a second active layer, and a region where ions are implanted forms a source and a drain.
In process 4, a second gate insulating layer 300 is formed on a side of the second semiconductor layer 201 away from the substrate 100, and the second gate insulating layer 300 covers the second semiconductor layer 201 and is in contact with the first gate insulating layer 200, and the material of the second gate insulating layer 300 may be silicon oxide and/or silicon nitride. The gate layer 110 is formed on a side of the second gate insulating layer 300 away from the substrate 100, and the gate layer 110 may be formed by sputtering, wherein the material of the gate layer 110 may be Mo/Al/Mo, Ti/Al/Ti, or the like.
In conjunction with the prior art of fig. 1, the embodiment of the present invention provides a technical solution by providing a dual-layer gate insulating layer, without providing a protective layer between the first semiconductor layer 101 and the second semiconductor layer 201, such that the second semiconductor layer 201 is located between the first gate insulating layer 200 and the second gate insulating layer 300, the first semiconductor layer 101 and the second semiconductor layer 201 can be made to share the second gate insulating layer 300, the first thin film transistor formed with the first semiconductor layer 101 is a double-layered gate insulating layer structure, the second thin film transistor formed by the second semiconductor layer 201 is a single-layer gate insulating layer structure, which can greatly reduce the distance between the first semiconductor layer 101 and the second semiconductor layer 201, i.e. reduce the film thickness between the two thin film transistors, in the process of forming the thin film transistor on the array substrate, at least two mask processes can be saved.
Fig. 7 is a flowchart of another manufacturing method of an array substrate according to an embodiment of the present invention, and referring to fig. 7, the manufacturing method of the array substrate includes:
s210, providing a substrate.
And S220, forming a gate layer on one side of the substrate.
And S230, sequentially forming a first gate insulating layer and a second semiconductor layer on the side, away from the substrate, of the gate layer, wherein the first gate insulating layer covers the gate layer.
And S240, forming a second gate insulating layer on one side, far away from the substrate, of the first gate insulating layer, wherein the second gate insulating layer is in contact with the first gate insulating layer, and the second gate insulating layer covers the second semiconductor layer.
And S250, forming a first semiconductor layer on one side, far away from the substrate, of the second grid insulation layer, wherein the first semiconductor layer is in contact with the second grid insulation layer.
Specifically, the manufacturing method of the array substrate shown in fig. 7 is to form a thin film transistor with a bottom gate structure, and the flow of the method for forming a thin film transistor with a top gate structure shown in fig. 6 is the same, and the adopted processes are also the same, and only the sequence of the processes is different, and the specific working principle thereof is not described herein again.
Optionally, fig. 8 to fig. 19 are schematic diagrams of specific structures formed by corresponding steps of the method of the array substrate, and on the basis of the above technical solutions, referring to fig. 8 to fig. 19, this embodiment takes a thin film transistor with a top gate structure as an example for description.
In process 1, a substrate 100 is provided, and a protective layer 810 is formed on the substrate 100, where the material of the protective layer 810 may be a polyimide film.
In the process 2, a buffer layer 820 is formed on the side of the protective layer 810 away from the substrate 100, the buffer layer 820 may be formed of an inorganic material, and the protective layer 810 and the buffer layer 820 can perform a buffer protection function on the array substrate. An amorphous silicon layer is deposited on the buffer layer 820 at a side away from the substrate 100, and polycrystalline silicon is performed by Excimer Laser Annealing (ELA) to form a polycrystalline silicon layer. The polysilicon layer is then patterned by a photolithography process (using a mask), and the amorphous silicon layer is preferably annealed between the patterning in order to prevent shrinkage dislocation of the amorphous silicon layer due to high temperature. After the patterned polysilicon layer is formed, ion implantation (e.g., phosphorous ion or boron ion) is performed on the polysilicon layer to form the first semiconductor layer 101 by doping, wherein a region of the first semiconductor layer 101 where ions are not implanted forms a first active layer, and a region where ions are implanted forms a source/drain.
In step 3, a first gate insulating layer 200 is formed on the substrate 100, and the first gate insulating layer 200 covers the first semiconductor layer 101, wherein the material of the first gate insulating layer 200 may be silicon oxide and/or silicon nitride. The first gate insulating layer 200 is used as an insulating layer of the first semiconductor layer 101, and in order to improve the film formation quality of the first gate insulating layer 200, the first gate insulating layer 200 may be annealed to achieve the purpose of dehydrogenation and increasing the film density. Then, a metal oxide layer, such as indium gallium zinc oxide, is formed on the first gate insulating layer 200 at a side away from the substrate 100, and the metal oxide layer may be formed by sputtering. After the metal oxide layer is formed, the metal oxide layer is patterned (using a mask) by a photolithography process to obtain the second semiconductor layer 201.
In process 4, a second gate insulating layer 300 is formed on a side of the second semiconductor layer 201 away from the substrate 100, and the second gate insulating layer 300 covers the second semiconductor layer 201 and is in contact with the first gate insulating layer 200, and the material of the second gate insulating layer 300 may be silicon oxide and/or silicon nitride. A metal thin film is sputtered on a side of the second gate insulating layer 300 away from the substrate 100, and the metal thin film is etched using a photolithography process to form the gate layer 110 and the metal wiring layer 410, wherein the metal wiring layer 410 includes at least one of a data signal line, a scan signal line, and a power signal line. The material of the gate layer 110 may be Mo/Al/Mo, Ti/Al/Ti, etc. The gate layer 110 is patterned by a photolithography process to form a first gate layer 102 and a second gate layer 202. The second gate layer 202 is used as a mask to perform ion implantation (e.g., phosphorous ion or boron ion) on the second semiconductor layer 201, and the second semiconductor layer 201 is formed by doping, wherein a region of the second semiconductor layer 201 where no ion is implanted forms a second active layer, and a region where ions are implanted forms a source/drain.
In the process 5, a first interlayer insulating layer 400 is formed on the side of the gate layer 110 away from the substrate 100, and the first interlayer insulating layer 400 covers the gate layer 110. The first interlayer insulating layer 400 is etched using a photolithography process to form a first via hole and a second via hole. Illustratively, a positive photoresist layer is coated on the first interlayer insulating layer 400, the first interlayer insulating layer 400 is exposed where the photoresist layer is illuminated through a mask, the first interlayer insulating layer 400 is etched, the first via hole 11, the second via hole 12 and the routing via hole 41 are formed, respectively, and the photoresist layer is removed.
In the process 6, a metal film is sputtered on the side of the first interlayer insulating layer 400 away from the substrate 100, and is filled in the first via hole and the second via hole, and the metal film is etched by using a photolithography technique to form the first source drain layer 310, the second source drain layer 320, the second electrode layer 204, and the first connecting electrode layer 510, respectively. The first connection electrode layer 510 is used for connecting the metal wiring layer 410. In this embodiment, the capacitor electrode layer has the first electrode layer 203 and the second electrode layer 204, and the first interlayer insulating layer 400 sandwiched between the first electrode layer 203 and the second electrode layer 204 to form a storage capacitor, and the first electrode layer 203 and the second gate layer 202 of the capacitor electrode layer are shared, that is, the second gate layer 202 is multiplexed as the first electrode layer 203, so that the film space on the array substrate can be greatly reduced, and more pixel regions can be disposed on the array substrate, thereby being beneficial to improving the resolution of the display panel. Meanwhile, the manufacturing process flow of the array substrate can be reduced, and the production cost is favorably reduced.
In the process 7, a second interlayer insulating layer 500 is formed on the side of the source/drain layer away from the substrate 100, and the second interlayer insulating layer 500 may be made of silicon oxide and/or silicon nitride, which plays an insulating role. The third via hole 42 penetrating the second interlayer insulating layer 500 is etched on the second interlayer insulating layer 500 using a photolithography technique.
In the process 8, the film layer in the bending region is etched by using a photolithography technique to form a groove 520, so as to expose the protection layer 810 on the substrate 100.
In the process 9, a first planarizing layer 530 is formed in the groove 520, where the material of the first planarizing layer 530 may be an organic material, and when the bending region is bent, the internal stress of the bending region is reduced, so that the bending is facilitated.
In the process 10, a metal film is sputtered on a side of the second interlayer insulating layer 500 away from the substrate 100, and the metal film is etched to form a second connection electrode layer 401, where the second connection electrode layer 401 is connected to the first source/drain electrode layer 310, the second source/drain electrode layer 320, and the first connection electrode layer 510, respectively.
In the process 11, a third interlayer insulating layer 600 is formed on the side of the second connection electrode layer 401 away from the substrate 100, and the third interlayer insulating layer 600 is etched by using a photolithography technique to prevent the third interlayer insulating layer 600 from covering the groove 520 of the bending region, so as to avoid affecting the bending effect of the bending region.
And 12, forming a second planarization layer 540 on the side, away from the substrate 100, of the third interlayer insulating layer 600, and etching the second planarization layer 540 by using a photolithography process to form a via hole 44 penetrating through the second planarization layer 540, so that the subsequent film layer is connected with the thin film transistor on the array substrate.
Therefore, in combination with the prior art shown in fig. 1, in the technical solution provided in the embodiment of the present invention, a double-layer gate insulating layer is provided, and a protection layer does not need to be provided between the first semiconductor layer 101 and the second semiconductor layer 201, which is beneficial to reducing one etching process, that is, reducing the number of masks, so that the second semiconductor layer 201 is located between the first gate insulating layer 200 and the second gate insulating layer 300, and the first semiconductor layer 101 and the second semiconductor layer 201 can share the second gate insulating layer 300, and the first thin film transistor formed by the first semiconductor layer 101 is used as a double-layer gate insulating layer structure, and the second thin film transistor formed by the second semiconductor layer 201 is used as a single-layer gate insulating layer structure, so that the distance between the first semiconductor layer 101 and the second semiconductor layer 201 can be greatly reduced, that is, the film thickness between the two thin film transistors is reduced.
Fig. 20 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention, and referring to fig. 20, the subsequent process further includes forming corresponding film structures of an anode 920 of a light emitting device, a pixel defining layer 910, and a supporting pillar 930 on a side of the second planarization layer 540 away from the substrate 100, and the processes for forming these structures may refer to the processes in the prior art and are not repeated herein.
The embodiment of the invention also provides a display panel, which comprises the array substrate provided by any embodiment of the invention, so that the display panel provided by the embodiment of the invention also has the beneficial effects described in any embodiment.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate;
a first gate insulating layer on one side of the substrate;
the second grid electrode insulating layer is positioned on one side, far away from the substrate, of the first grid electrode insulating layer and is in contact with the first grid electrode insulating layer;
the first semiconductor layer is positioned on one side, close to the substrate, of the first grid insulating layer, the first grid insulating layer covers the first semiconductor layer, and the grid layer is positioned on one side, far away from the substrate, of the second grid insulating layer and is in contact with the second grid insulating layer; alternatively, the first and second electrodes may be,
the first semiconductor layer is positioned on one side, far away from the substrate, of the second grid insulating layer, the grid layer is positioned on one side, close to the substrate, of the first grid insulating layer, and the first grid insulating layer covers the grid layer;
a second semiconductor layer between the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer covers the second semiconductor layer; wherein the first semiconductor layer and the second semiconductor layer are different in material.
2. The array substrate of claim 1, wherein the material of the first semiconductor layer comprises polysilicon, the material of the second semiconductor layer comprises metal oxide, the first semiconductor layer comprises a first active layer, the second semiconductor layer comprises a second active layer, and an orthographic projection of the first active layer on the substrate does not overlap an orthographic projection of the second active layer on the substrate.
3. The array substrate of claim 1, wherein when the first semiconductor layer is located on a side of the first gate insulating layer close to the substrate and the first gate insulating layer covers the first semiconductor layer, the gate layer is located on a side of the second gate insulating layer away from the substrate and is in contact with the second gate insulating layer;
the array substrate further includes:
a first interlayer insulating layer; the gate layer is positioned on one side of the gate layer, which is far away from the substrate, and covers the gate layer;
the source drain layer is positioned on one side, far away from the substrate, of the first interlayer insulating layer and comprises a first source drain layer and a second source drain layer, and the first source drain layer and the second source drain layer are arranged on the same layer;
the first source drain layer is in contact with the first semiconductor layer through a first through hole penetrating through the first interlayer insulating layer; the second source drain layer is in contact with the second semiconductor layer through a second via hole penetrating through the first interlayer insulating layer.
4. The array substrate of claim 3, wherein the gate layers comprise a first gate layer and a second gate layer, and the first gate layer and the second gate layer are disposed on the same layer; an orthographic projection of the first gate layer on the substrate falls within an orthographic projection of the first semiconductor layer on the substrate, and an orthographic projection of the second gate layer on the substrate falls within an orthographic projection of the second semiconductor layer on the substrate.
5. The array substrate of claim 4, further comprising a capacitor electrode layer, wherein the capacitor electrode layer comprises a first electrode layer and a second electrode layer, the first electrode layer is shared with the second gate layer, and the second electrode layer is located on a side of the first interlayer insulating layer away from the substrate and is disposed on the same layer as the source/drain electrode layer.
6. The array substrate of claim 5, wherein an orthographic projection of the first electrode layer on the substrate covers an orthographic projection of the second electrode layer on the substrate.
7. The array substrate of claim 4, further comprising a second interlayer insulating layer, a third interlayer insulating layer, a planarization layer, and a plurality of connection electrode layers;
the second interlayer insulating layer is positioned on one side, away from the substrate, of the source drain electrode layer, the connecting electrode layer is positioned on one side, away from the substrate, of the second interlayer insulating layer, the plurality of connecting electrode layers are arranged on the same layer, and each connecting electrode layer is respectively in contact with the first source drain electrode layer and the second source drain electrode layer through third through holes penetrating through the second interlayer insulating layer;
the third interlayer insulating layer and the planarization layer are sequentially stacked on one side, away from the substrate, of the connection electrode layer.
8. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming a first semiconductor layer on one side of the substrate;
a first grid electrode insulating layer and a second semiconductor layer are sequentially formed on one side, away from the substrate, of the first semiconductor layer, and the first grid electrode insulating layer covers the first semiconductor layer;
forming a second gate insulating layer on one side, far away from the substrate, of the first gate insulating layer, wherein the second gate insulating layer is in contact with the first gate insulating layer, and the second gate insulating layer covers the second semiconductor layer;
and forming a gate layer on one side of the second gate insulating layer, which is far away from the substrate, wherein the gate layer is in contact with the second gate insulating layer.
9. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming a gate layer on one side of the substrate;
a first grid electrode insulating layer and a second semiconductor layer are sequentially formed on one side, away from the substrate, of the grid electrode layer, and the first grid electrode insulating layer covers the grid electrode layer;
forming a second gate insulating layer on one side, far away from the substrate, of the first gate insulating layer, wherein the second gate insulating layer is in contact with the first gate insulating layer, and the second gate insulating layer covers the second semiconductor layer;
and forming a first semiconductor layer on one side of the second grid insulating layer, which is far away from the substrate, wherein the first semiconductor layer is in contact with the second grid insulating layer.
10. A display panel comprising the array substrate according to any one of claims 1 to 7.
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