CN111276527A - Display panel and manufacturing method thereof - Google Patents

Display panel and manufacturing method thereof Download PDF

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Publication number
CN111276527A
CN111276527A CN202010104008.8A CN202010104008A CN111276527A CN 111276527 A CN111276527 A CN 111276527A CN 202010104008 A CN202010104008 A CN 202010104008A CN 111276527 A CN111276527 A CN 111276527A
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China
Prior art keywords
electrode
layer
display panel
capacitor
active layer
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CN202010104008.8A
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Chinese (zh)
Inventor
林振国
张鹏
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to CN202010104008.8A priority Critical patent/CN111276527A/en
Publication of CN111276527A publication Critical patent/CN111276527A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The application provides a display panel and a manufacturing method thereof, wherein the display panel comprises: a substrate; the TFT device layer is arranged on the substrate and comprises a thin film transistor and a capacitor; the light emitting layer device layer is arranged on the TFT device layer; the thin film packaging layer is arranged on the luminescent layer device layer; wherein the capacitor is a transparent capacitor. The capacitor is a transparent capacitor, so that the capacitor can be directly arranged in a display area, and the problem of low pixel aperture ratio of a large-size display panel is solved.

Description

Display panel and manufacturing method thereof
Technical Field
The application relates to the technical field of display, in particular to a display panel and a manufacturing method thereof.
Background
In order to manufacture a large-size high-resolution bottom-emitting OLED or QLED display panel, the size of pixels in the display panel structure needs to be reduced, that is, Thin Film Transistors (TFTs), capacitors, and routing lines are as small as possible, so as to increase the area of the light-transmitting region of the pixels. However, each pixel requires a TFT region, a capacitor region, a light-emitting region and a wiring region. However, the TFT area, the capacitor area, the light emitting area, and the trace area need a certain size to ensure the function, so the reduction range is limited, and the TFT area, the capacitor area, the light emitting area, and the trace area still occupy a certain pixel area, thereby affecting the aperture ratio of the display panel.
Therefore, the prior art has defects which need to be solved urgently.
Disclosure of Invention
The application provides a display panel and a manufacturing method thereof, which can solve the problem that the pixel aperture ratio of the display panel with large size and high resolution is low.
In order to solve the above problems, the technical solution provided by the present application is as follows:
the application provides a display panel, including:
a substrate;
the TFT device layer is arranged on the substrate and comprises a thin film transistor and a capacitor;
the light emitting layer device layer is arranged on the TFT device layer;
the thin film packaging layer is arranged on the light-emitting layer device layer;
wherein the capacitor is a transparent capacitor.
In the display panel of the present application, the capacitor includes a first electrode and a second electrode that are disposed opposite to each other and insulated from each other, wherein the second electrode is disposed on the same layer as a source/drain of the thin film transistor and electrically connected to the source/drain, and the first electrode is disposed on the same layer as an active layer of the thin film transistor and spaced apart from the active layer.
In the display panel of the present application, the first electrode is made of the same material as the active layer, and the first electrode is formed by being made conductive.
In the display panel of the present application, the source/drain electrodes include a transparent electrode and a metal electrode stacked, the transparent electrode being in contact with the active layer, the metal electrode being located over the transparent electrode.
In the display panel of the present application, at least a part of the extension of the transparent electrode overlaps the first electrode.
In the display panel of the present application, the second electrode includes a portion where the transparent electrode extends to the outside of the metal electrode.
In the display panel of the present application, the anode of the light emitting layer device layer of the display panel includes the second electrode.
In the display panel of the application, the capacitor is located at a position of the display panel corresponding to the display area.
In the display panel of the application, the active layer comprises a channel region and ion doped regions located on two sides of the channel region, a gate insulating layer and a grid electrode are arranged on the active layer, and the gate insulating layer and the grid electrode correspond to the channel region.
The application also provides a manufacturing method of the display panel, which comprises the following steps:
step S1, forming a patterned semiconductor member on the substrate;
step S2, sequentially preparing a gate insulating film and a gate metal film on the substrate and the semiconductor component, patterning the semiconductor component, the gate insulating film and the gate metal film to form a gate and a gate insulating layer and to form an active layer and a first semiconductor pattern which are spaced apart from each other, and performing a conductor processing on the portion of the active layer exposed out of the gate insulating layer and the first semiconductor pattern to form an ion doping region and a first electrode of the active layer, respectively;
step S3, preparing a planarization layer on the gate, and patterning the planarization layer to form a via hole corresponding to the ion-doped region of the active layer;
step S4, preparing a composite conductive film including a transparent conductive film and a metal conductive film stacked in sequence on the planarization layer, and patterning the composite conductive film to form a composite conductive electrode corresponding to the via hole, wherein at least a portion of an extension of the composite conductive electrode overlaps the first electrode;
step S5, removing a portion of the metal conductive film of the composite conductive electrode corresponding to the first electrode to form a second electrode corresponding to the first electrode;
step S6, preparing a pixel defining layer on the second electrode and patterning the pixel defining layer to form a pixel hole corresponding to the second electrode;
step S7, preparing a light emitting layer in the pixel hole, and preparing a cathode on the light emitting layer and the pixel defining layer;
step S8, a thin film encapsulation layer is prepared on the cathode.
The beneficial effect of this application does: according to the display panel and the manufacturing method thereof, the capacitor is formed by the transparent material, and the capacitor can transmit light, so that the capacitor can be arranged below the light emitting layer (namely, in the display area), the aperture opening ratio of the pixel area is increased, and the resolution ratio is increased. In addition, the second electrode of the capacitor is formed simultaneously with the source electrode and the drain electrode and can be used as an anode simultaneously, so that the number of photomasks is greatly reduced, and the manufacturing cost is saved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure;
fig. 2A to 2I are schematic diagrams illustrating a process of manufacturing a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "longitudinal," "lateral," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," and the like are used in the orientation or positional relationship indicated in the drawings, which are based on the orientation or positional relationship shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore should not be considered as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise. In this application, "/" means "or".
The present application may repeat reference numerals and/or letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.
Referring to fig. 1 and fig. 2A to 2I, the present application provides a method for manufacturing a display panel, the method including the steps of:
step S1, a patterned semiconductor member is formed on the substrate.
As shown in fig. 2A, a substrate 101 may be a glass substrate or a flexible substrate, the substrate 101 is first cleaned, and then a metal layer with a thickness of 500A-2000A is deposited on the substrate 101 and patterned to form a light shielding layer 102. The material of the light-shielding layer 102 may be one of Mo (molybdenum), Al (aluminum), Cu (copper), and Ti (titanium), or an alloy of one or more of these.
And then depositing a buffer layer 103 on the light-shielding layer 102, wherein the buffer layer 103 comprises at least one single-layer or multi-layer structure of silicon oxide (SiOx) and silicon nitride (SiNx), and the thickness of the buffer layer 103 is 1000A-5000A.
And then depositing a semiconductor thin film with the thickness of 100A-1000A on the buffer layer 103, and forming a semiconductor component 104 positioned on the light shielding layer 102 after patterning. The material of the semiconductor thin film includes, but is not limited to, oxide semiconductor materials such as IGZO, IGZTO, IZTO, and the like.
Step S2, sequentially preparing a gate insulating film and a gate metal film on the substrate and the semiconductor component, patterning the semiconductor component, the gate insulating film and the gate metal film to form a gate and a gate insulating layer and to form an active layer and a first semiconductor pattern which are spaced apart from each other, and performing a conductor processing on the portion of the active layer exposed out of the gate insulating layer and the first semiconductor pattern to form an ion doped region and a first electrode of the active layer, respectively.
As shown in fig. 2B, a gate insulating film 105 and a gate metal film 106 are sequentially prepared on the semiconductor member 104. The gate insulating film 105 includes, but is not limited to, at least one of silicon oxide (SiOx) and silicon nitride (SiNx) in a single layer or a multi-layer structure, and has a thickness of 1000A to 3000A. The material of the gate metal film 106 may be one or more of Mo (molybdenum), Al (aluminum), Cu (copper), and Ti (titanium), and the thickness is 2000A to 8000A.
As shown in fig. 2C, the semiconductor component 104, the gate insulating film 105 and the gate metal film 106 are patterned by yellow light, a gate electrode 106a is etched, and then a gate insulating layer 105a is etched by using the gate electrode 106a as a self-alignment, wherein the gate insulating layer 105a is correspondingly located below the gate electrode 106 a. The semiconductor member 104 simultaneously forms an active layer 104a and a first semiconductor pattern 104b spaced apart from each other, and performs a conductive process on a portion of the active layer 104a where the gate insulating layer 105a is exposed and the first semiconductor pattern 104b, and after the conductive process, for the active layer 104a and the first semiconductor pattern 104b which are not covered with the gate insulating layer 105a and the gate electrode 106a, and the resistance is significantly reduced, an ion doped region 104a 'and a first electrode 104 b' of the active layer 104a are formed, respectively, and a portion of the active layer 104a covered with the gate insulating layer 105a is not processed to maintain a semiconductor characteristic as a channel region of the active layer 104 a.
By adopting the method, only one yellow light process is utilized, so that a photomask process for independently patterning the active layer 104a and the first semiconductor pattern 104b is reduced, and a photomask process for independently patterning the gate insulating layer 105a is also reduced, so that the use frequency of the mask plate is reduced, and the cost is reduced.
In one embodiment, the gate electrode 106a and the gate insulating layer 105a and the active layer 104a and the first semiconductor pattern 104b may be simultaneously formed through the same half-tone mask process.
Step S3, preparing a planarization layer on the gate, and patterning the planarization layer to form a via hole corresponding to the ion-doped region of the active layer.
As shown in fig. 2D, a planarization layer 107 is formed on the gate electrode 106a to improve the planarity of the substrate surface, and a via hole is formed through the planarization layer 107 and corresponding to the ion-doped region 104 a' of the active layer 104a after patterning.
Step S4, preparing a composite conductive film including a transparent conductive film and a metal conductive film stacked in sequence on the planarization layer, and patterning the composite conductive film to form a composite conductive electrode corresponding to the via hole, wherein at least a portion of an extension of the composite conductive electrode overlaps the first electrode.
As shown in fig. 2E, a composite conductive film 108 is prepared on the planarization layer 107, and specifically, a transparent conductive film 1081 and a metal conductive film 1082 are sequentially prepared on the planarization layer 107. The transparent conductive film 1081 may be a single layer or a multi-layer structure including one or more of ITO and IZO. The metal conductive thin film 1082 includes, but is not limited to, a single or multi-layer structure of one or more of Mo (molybdenum), Al (aluminum), Cu (copper), Ti (titanium).
As shown in fig. 2F, the transparent conductive film 1081 and the metal conductive film 1082 are subjected to a light irradiation and etching process using the same photomask, and patterned to form the composite conductive electrode 108a corresponding to the via hole. The composite conductive electrode 108a extends to a side near the first electrode, and at least a portion of its extension overlaps the first electrode 104 b'. Wherein a portion of the composite conductive electrode 108a corresponding to the gate electrode 106a is removed.
In one embodiment, an orthographic projection of the composite conductive electrode 108a on the substrate 101 covers an orthographic projection of the first electrode 104 b' on the substrate 101.
Step S5, removing a portion of the metal conductive film of the composite conductive electrode corresponding to the first electrode to form a second electrode corresponding to the first electrode.
As shown in fig. 2G, the metal conductive film 1082 of the composite conductive electrode 108a corresponding to the first electrode 104b ' is removed to expose a portion of the transparent conductive film, so as to form a metal electrode 1082 ' and a transparent electrode 1081 ' which are stacked; the transparent electrode 1081 ' is in contact with the active layer 104a, and the metal electrode 1082 ' is positioned above the transparent electrode 1081 '.
Wherein the metal electrode 1082 ' and the portion of the transparent electrode 1081 ' overlapping the metal electrode 1082 ' combine to form a source/drain electrode; the exposed portion of the transparent electrode 1081 ' is an extension a, the extension a forms an anode of the display panel, and the extension a simultaneously forms a second electrode opposite to the first electrode 104b ', and the first electrode 104b ' and the second electrode form a capacitor.
By adopting the preparation method, the metal electrode 1082 'and the transparent electrode 1081' are formed by adopting the same photomask process, so that one photomask process is reduced; meanwhile, the part of the transparent electrode 1081 'not covered by the metal electrode 1082' can be used as the second electrode and the anode of the capacitor at the same time, so that the mask process for separately preparing the second electrode and the anode is saved, and the use frequency of the mask plate is further reduced.
Step S6, a pixel defining layer is prepared on the second electrode and patterned to form a pixel hole corresponding to the second electrode.
As shown in fig. 2H, a pixel defining layer 109 is prepared on the metal electrode 1082', and the pixel defining layer 109 is patterned to form pixel holes 109a corresponding to the anodes.
In step S7, as shown in fig. 2I, a light emitting layer 110 is prepared in the pixel hole 109a, and a cathode 111 is prepared on the light emitting layer 110 and the pixel defining layer 109.
In step S8, as shown in fig. 2I, a thin film encapsulation layer 112 is prepared on the cathode 111.
The present application further provides a display panel prepared by the above method, as shown in fig. 3, and with reference to fig. 2A to 2I, the display panel includes: the substrate 101 may be a glass substrate or a flexible substrate; a TFT device layer disposed on the substrate 101; the TFT device layer comprises a thin film transistor and a capacitor; the light emitting layer device layer is arranged on the TFT device layer; and a thin film encapsulation layer 112 disposed on the light emitting layer device layer.
The capacitor is a transparent capacitor, so that the capacitor can be positioned at a position of the display panel corresponding to the display area, thereby increasing the pixel aperture ratio.
Specifically, a light-shielding layer 102 is disposed on the substrate 101; a buffer layer 103 is arranged on the light-shielding layer 102; an active layer 104a and a first electrode 104b 'are arranged on the buffer layer 103 at intervals, wherein the active layer 104a comprises a channel region and ion doped regions 104 a' positioned at two sides of the channel region; a gate insulating layer 105a and a gate electrode 106a are disposed on the active layer 104a, and the gate insulating layer 105a and the gate electrode 106a are both disposed corresponding to the channel region. A flat layer 107 is arranged on the gate 106a, and a via hole is arranged on the flat layer 107 at a position corresponding to the ion doped region 104 a'; a transparent electrode 1081 ' and a metal electrode 1082 ' are disposed on the planarization layer 107 corresponding to the via stack, the transparent electrode 1081 ' is in contact with the active layer 104a, and the metal electrode 1082 ' is disposed on the transparent electrode 1081 '.
Wherein the metal electrode 1082 ' and the portion of the transparent electrode 1081 ' overlapping the metal electrode 1082 ' combine to form a source/drain electrode; that is, the source/drain electrodes have a double-layered structure, i.e., the overlapped portion of the transparent electrode 1081 'and the metal electrode 1082' is the source/drain electrode. At least a portion of the extension a (i.e., the portion of the transparent electrode 1081 'not covered by the metal electrode 1082') exposed by the transparent electrode 1081 'overlaps with the first electrode 104 b'. The extension a forms an anode of the display panel, and the extension a simultaneously forms a second electrode opposite to the first electrode 104 b', i.e., the anode of the display panel simultaneously serves as the second electrode. The first electrode 104 b' forms a capacitance with the second electrode.
The first electrode 104b 'and the second electrode are disposed opposite to each other and insulated from each other, the first electrode 104 b' and the active layer 104a are made of the same material, and the second electrode and the source/drain are integrally formed.
Wherein the light emitting layer device layer includes an anode (the second electrode), a light emitting layer 110, and a cathode 111.
The capacitor is formed by adopting the transparent material, and the capacitor can transmit light, so that the capacitor can be arranged below the light emitting layer (namely, in the display area), the aperture opening ratio of the pixel area is increased, and the resolution is increased. In addition, the second electrode of the capacitor is formed simultaneously with the source electrode and the drain electrode and can be used as an anode simultaneously, so that the number of photomasks is greatly reduced, and the manufacturing cost is saved.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.

Claims (10)

1. A display panel, comprising:
a substrate;
the TFT device layer is arranged on the substrate and comprises a thin film transistor and a capacitor;
the light emitting layer device layer is arranged on the TFT device layer;
the thin film packaging layer is arranged on the light-emitting layer device layer;
wherein the capacitor is a transparent capacitor.
2. The display panel according to claim 1, wherein the capacitor comprises a first electrode and a second electrode that are opposite to each other and insulated from each other, wherein the second electrode is disposed on the same layer as and electrically connected to the source/drain of the thin film transistor, and the first electrode is disposed on the same layer as and spaced apart from the active layer of the thin film transistor.
3. The display panel according to claim 2, wherein the first electrode is made of the same material as the active layer, and wherein the first electrode is formed by being electrically conductive.
4. The display panel according to claim 2, wherein the source/drain electrode comprises a transparent electrode and a metal electrode which are stacked, the transparent electrode being in contact with the active layer, the metal electrode being located over the transparent electrode.
5. The display panel according to claim 4, wherein at least a part of the extension of the transparent electrode overlaps with the first electrode.
6. The display panel according to claim 5, wherein the second electrode includes a portion of the transparent electrode extending to the outside of the metal electrode.
7. The display panel according to claim 2, wherein an anode of a light emitting layer device layer of the display panel comprises the second electrode.
8. The display panel according to claim 1, wherein the capacitor is located at a position of the display panel corresponding to the display area.
9. The display panel according to claim 8, wherein the active layer comprises a channel region and ion-doped regions located at two sides of the channel region, and wherein a gate insulating layer and a gate electrode are disposed on the active layer and both corresponding to the channel region.
10. A manufacturing method of a display panel is characterized by comprising the following steps:
step S1, forming a patterned semiconductor member on the substrate;
step S2, sequentially preparing a gate insulating film and a gate metal film on the substrate and the semiconductor component, patterning the semiconductor component, the gate insulating film and the gate metal film to form a gate and a gate insulating layer and to form an active layer and a first semiconductor pattern which are spaced apart from each other, and performing a conductor processing on the portion of the active layer exposed out of the gate insulating layer and the first semiconductor pattern to form an ion doping region and a first electrode of the active layer, respectively;
step S3, preparing a planarization layer on the gate, and patterning the planarization layer to form a via hole corresponding to the ion-doped region of the active layer;
step S4, preparing a composite conductive film including a transparent conductive film and a metal conductive film stacked in sequence on the planarization layer, and patterning the composite conductive film to form a composite conductive electrode corresponding to the via hole, wherein at least a portion of an extension of the composite conductive electrode overlaps the first electrode;
step S5, removing a portion of the metal conductive film of the composite conductive electrode corresponding to the first electrode to form a second electrode corresponding to the first electrode;
step S6, preparing a pixel defining layer on the second electrode and patterning the pixel defining layer to form a pixel hole corresponding to the second electrode;
step S7, preparing a light emitting layer in the pixel hole, and preparing a cathode on the light emitting layer and the pixel defining layer;
step S8, a thin film encapsulation layer is prepared on the cathode.
CN202010104008.8A 2020-02-20 2020-02-20 Display panel and manufacturing method thereof Pending CN111276527A (en)

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Application publication date: 20200612