CN113163553A - 18-channel high-precision constant-current LED driving chip - Google Patents
18-channel high-precision constant-current LED driving chip Download PDFInfo
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- CN113163553A CN113163553A CN202110268325.8A CN202110268325A CN113163553A CN 113163553 A CN113163553 A CN 113163553A CN 202110268325 A CN202110268325 A CN 202110268325A CN 113163553 A CN113163553 A CN 113163553A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/345—Current stabilisation; Maintaining constant current
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0266—Reduction of sub-frame artefacts
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
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Abstract
The invention relates to an 18-channel high-precision constant-current LED driving chip, wherein the chip is provided with a displacement temporary storage, and the displacement temporary storage comprises: 18 constant current output pins, a serial data input pin DI, a data clock signal input pin DCK, a gray scale modulation signal input pin PDM, a serial data output pin DO, an input pin REXT, and a power ground pin VDD. The 18-channel high-precision constant-current LED driving chip adopting the built-in double-latch display patent technology can effectively improve the refresh rate and the LED utilization rate of the traditional general driving display screen, has a built-in ghost eliminating function and improves the image performance of a scanning screen.
Description
Technical Field
The invention relates to the technical field of LED driving chips, in particular to an 18-channel high-precision constant-current LED driving chip.
Background
A Light Emitting Diode (LED) is a new solid semiconductor light source, and is widely used in lighting circuits, backlight modules or display panels. The LED driving chip is a power supply adjusting electronic device for driving the LED to emit light or the LED module assembly to normally work. According to different application requirements, control chips of LED driving systems with different versions are required, such as a commonly-used 4-channel control chip and a commonly-used 8-channel control chip.
Disclosure of Invention
Technical problem to be solved
In view of the above disadvantages and shortcomings of the prior art, the present invention provides an 18-channel high-precision constant-current LED driving chip.
(II) technical scheme
In order to achieve the purpose, the invention adopts the main technical scheme that:
in a first aspect, an embodiment of the present invention provides an 18-channel high-precision constant-current LED driving chip, where the driving chip has a shift register, and the shift register includes: 18 constant current output pins, a serial data input pin DI, an input pin DCK of a data clock signal, an input pin PDM of a gray scale modulation signal, a serial data output pin DO, an input pin REXT, a power grounding pin VDD and a grounding end GND pin for controlling logic and driving current;
the 18 constant current output pins comprise 6 red current output pins, 6 green current output pins and 6 blue current output pins.
Preferably, the serial data output pin DO is used to connect in series with an external driving chip.
Preferably, the input pin REXT is used for connecting with an external resistor.
Preferably, the operating voltage of the chip is 3.3 to 5.0 volts.
Preferably, the chip has a 24-pin QFN package type.
Preferably, the QFN package type of the driver chip specifically includes: QFN24-2mmx5mm-0.4mm package type or QFN24-3mmx4mm-0.4mm package type.
Preferably, the QFN24-2mmx5mm-0.4mm packaging type of the driving chip is as follows: the length of the chip is 5mm, and the width of the chip is 2 mm; the two long sides of the chip respectively comprise 11 pins, and the two wide sides of the chip respectively comprise 2 pins; the two long edges of the chip are a bottom edge and a top edge; wherein, be provided with from the anticlockwise order on the chip base: a green current output pin, a red current output pin, a blue current output pin, a green current output pin, a GND pin, a red current output pin, a blue current output pin, a green current output pin, a red current output pin, a power ground pin VDD, an input pin DI, an input pin DCK, an input pin PDM, an output pin DO, an input pin REXT, a ground terminal GND pin, a blue current output pin, a green current output pin, a red current output pin, and a blue current output pin;
the QFN24-3mmx4mm-0.4mm packaging type of the driving chip is as follows: the QFN packaging type of the chip is that the length of the chip is 4mm, and the width of the chip is 3 mm; the two long sides of the chip respectively comprise 7 pins, and the two wide sides of the chip respectively comprise 5 pins; the two long edges of the chip are a bottom edge and a top edge; wherein, be provided with from the anticlockwise order on the chip base: a red current output pin, a power ground pin VDD, an input pin DI, an input pin DCK, an input pin PDM, an output pin DO, an input pin REXT, a blue current output pin, a green current output pin, a red current output pin, a blue current output pin, a green current output pin, a red current output pin, a blue current output pin, and a green current output pin; and the top surface of the chip is also provided with a grounding end GND pin.
Preferably, the driving chip sets a preset delay time between output currents of the red current output pin, the green current output pin and the blue current output pin.
Preferably, the chip is provided with a ghost shadow eliminating program for eliminating the up-line and down-line ghosts when the driving chip is matched with a system hardware circuit.
Preferably, the driving chip is also pre-built with a double-latch display technology.
(III) advantageous effects
The invention has the beneficial effects that: according to the 18-channel high-precision constant-current LED driving chip, the 18-channel high-precision constant-current LED driving chip of the built-in double-latch display patent technology is adopted, the refresh rate and the LED utilization rate of a traditional general driving display screen can be effectively improved, a ghost eliminating function is built in, and the image performance of a scanning screen is improved.
The 18-channel high-precision constant-current LED driving chip provides 18 open-circuit constant-current sink outputs with the maximum bearing voltage of 15 volts, and the output magnitude of the current can be set by means of an external resistor.
The 18-channel high-precision constant-current LED driving chip uses a 3-wire serial input interface, so that a controller can enable a plurality of driving chips to be connected in series for operation by three input control ports (a serial data input pin DI input to a displacement register, an input pin DCK of a data clock signal and an input pin PDM of a gray scale modulation signal) and a data output port (a serial data output pin DO).
Drawings
FIG. 1 is a pin diagram of an 18-channel high-precision constant-current LED driving chip according to the present invention;
FIG. 2 is an equivalent circuit of the input terminals of the input pin DCK, the input pin DI and the input pin PDM according to the embodiment of the present invention;
FIG. 3 is an equivalent circuit of the output terminal of the output pin DO according to the embodiment of the present invention;
FIG. 4 is a diagram illustrating the limiting parameters of the driver IC according to an embodiment of the present invention;
fig. 5 shows dc characteristics of the driving chip at VDD of 5.0V and Ta of 25 ℃ in the embodiment of the present invention;
fig. 6 shows dc characteristics of the driving chip at VDD of 3.3V and Ta of 25 ℃ in the embodiment of the present invention;
fig. 7 shows the dynamic characteristics of the driving chip at VDD of 5.0V and Ta of 25 ℃ in the embodiment of the present invention;
fig. 8 shows the dynamic characteristics of the driving chip at VDD of 3.3V and Ta of 25 ℃ in the embodiment of the present invention;
FIG. 9 is a timing diagram of DCK-DI, DO of the driver chip in the embodiment of the present invention;
FIG. 10 is a timing diagram of the DCK-DI after the control command is inputted when the control command is inputted to the driver chip DI-DO according to the embodiment of the present invention;
FIG. 11 is a timing diagram of the driving chips PDM-OUTN _ R, OUTN _ G, OUTN _ B according to the present invention;
FIG. 12 is a diagram illustrating a command data mode of the driver IC according to an embodiment of the present invention;
FIG. 13 is a diagram illustrating an embodiment of a driver chip for influencing data patterns;
FIG. 14 is a diagram illustrating a driver chip receiving a control command according to an embodiment of the present invention;
FIG. 15 is a diagram illustrating the data mode of the driver chip from the image data mode and the command data mode according to the embodiment of the present invention;
FIG. 16 is a timing diagram illustrating the complete control of the driver IC according to the embodiment of the present invention;
FIG. 17 is a diagram illustrating the definition of the shadow elimination time of the driver IC according to an embodiment of the present invention;
FIG. 18 is a schematic diagram illustrating the relationship between the current GAIN GAIN of the driver IC and the GCC according to the embodiment of the present invention;
FIG. 19 is a schematic diagram illustrating the output voltage and constant current characteristics of the driver IC according to an embodiment of the present invention;
FIG. 20 is a diagram illustrating the relationship between maximum power consumption and ambient temperature for different packages in an embodiment of the present invention;
fig. 21 is a schematic diagram of another pin of an 18-channel high-precision constant-current LED driving chip according to an embodiment of the present invention.
[ description of reference ]
1: a red current output pin; 2: a power ground pin VDD; 3: a serial data input pin DI; 4: an input pin DCK for a data clock signal; 5: a gray scale modulation signal input pin PDM; 6: a serial data output pin DO; 7: inputting a pin REXT; 8: a blue current output pin; 9: a green current output pin; 10: a red current output pin; 11: a blue current output pin; 12: a green current output pin; 13: a red current output pin; 14: a blue current output pin; 15: a green current output pin; 16: a red current output pin; 17: a blue current output pin; 18: a green current output pin; 19: a red current output pin; 20: a blue current output pin; 21: a green current output pin; 22: a red current output pin; 23: a blue current output pin; 24: a green current output pin.
Detailed Description
For the purpose of better explaining the present invention and to facilitate understanding, the present invention will be described in detail by way of specific embodiments with reference to the accompanying drawings.
In order to better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Referring to fig. 1, the present embodiment provides an 18-channel high-precision constant-current LED driving chip, where the driving chip has a shift register, and the shift register includes: 18 constant current output pins, a serial data input pin DI, an input pin DCK of a data clock signal, an input pin PDM of a gray scale modulation signal, a serial data output pin DO, an input pin REXT, a power ground pin VDD, and a ground terminal GND pin for controlling logic and driving current.
The 18 constant current output pins comprise 6 red current output pins, 6 green current output pins and 6 blue current output pins.
In this embodiment, the serial data output pin DO is used to be connected in series with a preset driver chip. The serial data output pin DO can be utilized in this embodiment to enable a plurality of driver chips to be connected in series for operation.
In this embodiment, the input pin REXT is used to connect to a preset external resistor. The REXT of the input pin in this embodiment can be used for an external resistor to set the output current.
In this embodiment, the operating voltage of the chip is 3.3 to 5.0 volts.
In this embodiment, the chip has a 24-pin QFN package type, which is suitable for different application requirements.
In this embodiment, the QFN package type of the chip with 24 pins is: QFN24-2mmx5mm-0.4mm or QFN24-3mmx4mm-0.4 mm.
In this embodiment, the 18 constant current output pins include 6 OUT _ R output pins, 6 OUT _ G output pins, and 6 OUT _ B output pins.
Preferably, the chip has a 24-pin QFN package type.
Preferably, the QFN package type of the driver chip specifically includes: QFN24-2mmx5mm-0.4mm package type or QFN24-3mmx4mm-0.4mm package type.
Referring to fig. 21, in the present embodiment, it is preferable that the QFN24-2mmx5mm-0.4mm package type of the driving chip is: the length of the chip is 5mm, and the width of the chip is 2 mm; the two long sides of the chip respectively comprise 11 pins, and the two wide sides of the chip respectively comprise 2 pins; the two long edges of the chip are a bottom edge and a top edge; wherein, be provided with from the anticlockwise order on the chip base: a green current output pin (pin name OUT-G2), a red current output pin (pin name OUT-R2), a blue current output pin (pin name OUT-B1), a green current output pin (pin name OUT-G1), a GND pin (pin name GND), a red current output pin (pin name OUT-R1), a blue current output pin (pin name OUT-B0), a green current output pin (pin name OUT-G0), a red current output pin (pin name OUT-R0), a power ground pin VDD, an input pin DI, an input pin DCK, an input pin PDM, an output pin DO, an input pin REXT, a ground pin GND pin, a blue current output pin (pin name OUT-B5), a green current output pin (pin name OUT-G5), a red current output pin (pin name OUT-R5), The LED comprises a blue current output pin (with the pin name of OUT-B4), a green current output pin (with the pin name of OUT-G4), a red current output pin (with the pin name of OUT-R4), a blue current output pin (with the pin name of OUT-B3), a green current output pin (with the pin name of OUT-G3), a red current output pin (with the pin name of OUT-R3) and a blue current output pin (with the pin name of OUT-B2).
Referring to fig. 1, the QFN24-3mmx4mm-0.4mm package type of the driver chip is: the QFN packaging type of the chip is that the length of the chip is 4mm, and the width of the chip is 3 mm; the two long sides of the chip respectively comprise 7 pins, and the two wide sides of the chip respectively comprise 5 pins; the two long edges of the chip are a bottom edge and a top edge; wherein, be provided with from the anticlockwise order on the chip base: a red current output pin (pin number 1), a power ground pin VDD (pin number 2), an input pin DI (pin number 3), an input pin DCK (pin number 4), an input pin PDM (pin number 5), an output pin DO (pin number 6), an input pin REXT (pin number 7), a blue current output pin (pin number 8), a green current output pin (pin number 9), a red current output pin (pin number 10), a blue current output pin (pin number 11), a green current output pin (pin number 12), a red current output pin (pin number 13), a blue current output pin (pin number 14), a green current output pin (pin number 15), a red current output pin (pin number 16), a blue current output pin (pin number 17), a green current output pin (pin number 18), a red current output pin (pin number 19), A blue current output pin (pin number 20), a green current output pin (pin number 21), a red current output pin (pin number 22), a blue current output pin (pin number 23), a green current output pin (pin number 24); and the top surface of the chip is also provided with a grounding end GND pin.
Preferably, the driving chip sets a preset delay time between output currents of the red current output pin, the green current output pin and the blue current output pin, that is, the driving chip has a preset delay time between output currents of the OUT _ R output pin, the OUT _ G output pin and the OUT _ B output pin.
In this embodiment, the driving chip is preset with a ghost elimination function for eliminating the up-line and down-line ghosts when the driving chip is collocated with the system hardware circuit.
In this embodiment, the driving chip is further pre-embedded with a dual latch display technology.
The equivalent circuit of the input terminals of DCK, DI, PDM in this embodiment is shown in fig. 2.
The equivalent circuit of the DO output terminal in this embodiment is shown in fig. 3.
The limiting parameters of the driving chip in this embodiment are shown in fig. 4.
In this embodiment, the driving chip has dc characteristics of VDD of 5.0V and Ta of 25 ℃.
In this embodiment, the dc characteristics of the driver chip at VDD of 3.3V and Ta of 25 ℃ are shown in fig. 6.
The dynamic characteristics of the driving chip in this embodiment at VDD of 5.0V and Ta of 25 deg.c are shown in fig. 7.
The dynamic characteristics of the driving chip at VDD of 3.3V and Ta of 25 ℃ in this embodiment are shown in fig. 8.
The timing diagram of the DCK-DI, DO driver chip in this embodiment is shown in FIG. 9.
In the embodiment, when the control command is input to the driving chip DI-DO, the timing diagram of the DCK-DI after the control command is input is shown in fig. 10.
Fig. 11 shows timing diagrams of the driving chips PDM to OUTn _ R, OUTn _ G, OUTn _ B in this embodiment.
The command data pattern diagram of the driver chip in this embodiment is shown in FIG. 12, and
FIG. 13 shows a data pattern diagram of the driver chip in this embodiment.
In the present embodiment, reference is made to fig. 14 when the driving chip receives the control command, and
FIG. 15 is a view showing an image data mode and an entry command data mode.
The complete control timing diagram of the driver chip in this embodiment is shown in fig. 16.
In the present embodiment, the driving chip may cause a large inflow current when all the current outputs are enabled together, and in order to reduce the EMI interference, the driving chip in the present embodiment designs a fixed delay time between the OUTn _ R/OUTn _ G/OUTn _ B output currents.
In the embodiment, the driving on-chip ghost elimination function can effectively eliminate the up-line and down-line ghosts by matching with the system hardware circuit, and the definition of the chip elimination time (Tghost) is shown in fig. 17.
When the control command is image data latch or enters a command data mode (image data latch is executed), an internal latch signal (LAT) is generated at the DCK falling edge, and the voltage of the output pin is raised (the maximum value is about 3.9V @ VDD ═ 5V) only between the rising edge of the internal latch signal (LAT) and the falling edge of the enable signal (PDM) for shadow elimination.
For better elimination function, the related timing is set such that the elimination time Tghost from the rising edge of the internal latch signal (LAT) to the falling edge of the PDM signal is greater than 2000 ns; the switching edge of the line feed signal SW needs to be set between the rising edge of the internal latch signal LAT and the falling edge of the PDM signal.
In the embodiment, the driving chip enables a PDM signal (OE) to cross over a LAT latch signal through a double-latch display patent technology of a bright anode semiconductor, so that the utilization rate of an LED of a traditional basic chip can be effectively improved, and the display effect and the uniformity of a display screen under low gray scale are optimized; and the display screen can greatly reduce the peak current of the driving chip under the same brightness design, and effectively improve the EMC grade of the display screen.
In this embodiment, the driver chip provides a programmable current gain function, allowing a user to use 6-bit command data.
GCC [5:0] ═ CMD [21:16]/CMD [13:8]/CMD [5:0] to adjust the output currents of the OUT _ R, OUT _ G, and OUT _ B output pins, the following equation can be used to calculate the current GAIN value (GAIN):
GAIN＝(GCC[5:0]+1)/64％～100％)。
referring to FIG. 18, the current GAIN value (GAIN) is shown schematically with GCC.
In this embodiment, the driving chip can still provide accurate constant current output under different forward voltages of the LED, and fig. 19 illustrates how to design an appropriate output voltage to achieve the optimal constant current characteristic.
In this embodiment, when the driver chip is turned on for 18 output channels, the actual power consumption of the chip is determined by the following formula:
PD(practical)＝VDD×IDD+VOUT0_R×IOUT0_R×DutyOUT0_R+
+VOUT5_B×IOUT5_B×DutyOUT5_B
in order to operate under safe conditions, the power consumption of the chip must be less than the maximum allowable power, which is determined by the ambient temperature and the package type, and the maximum power consumption is expressed as follows:
the PD (maximum value) decreases as the ambient temperature increases, so careful design operating conditions according to the package type and the ambient temperature are required, and fig. 20 illustrates the relationship between the maximum power consumption and the ambient temperature for different packages.
In the embodiment, the 18-channel high-precision constant-current LED driving chip of the double-latch display patent technology is built in the driving chip, so that the refresh rate and the LED utilization rate of the traditional general driving display screen can be effectively improved; and the ghost eliminating function is built in, and the image performance of the scanning screen is improved. The driving chip in this embodiment can normally operate at an operating voltage of 3.3 to 5.0 volts (+ -10%). In this embodiment, the driver chip provides 18 open-drain constant current sink outputs with a maximum withstand voltage of 15 volts, and the output of the current can be set by an external resistor. In the present embodiment, the driving chips use a 3-wire serial input interface, so that the controller can connect a plurality of driving chips in series via three input control ports (DI, DCK, and PDM) and a data output port (DO), and an auto-latch function is built in to implement a latch signal. The input end adopts Schmitt trigger design to effectively restrain signal noise interference. The built-in power-on reset can avoid the malfunction of the chip. The driving chip in the embodiment simplifies the control signals required by the circuit board and provides current output precision between channels of +/-4.0% (maximum value) and between chips of +/-4.0% (maximum value). The characteristics also include a stable current output capability of 0.1% and a fast current output transient response under the variation of the output voltage. The driving chip in the embodiment provides a 24-pin QFN package type to be suitable for different application requirements and can work in an external environment of-40 ℃ to +85 ℃.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium; either as communication within the two elements or as an interactive relationship of the two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, a first feature may be "on" or "under" a second feature, and the first and second features may be in direct contact, or the first and second features may be in indirect contact via an intermediate. Also, a first feature "on," "above," and "over" a second feature may be directly or obliquely above the second feature, or simply mean that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the second feature, or may simply mean that the first feature is at a lower level than the second feature.
In the description herein, the description of the terms "one embodiment," "some embodiments," "an embodiment," "an example," "a specific example" or "some examples" or the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are illustrative and not restrictive, and that those skilled in the art may make changes, modifications, substitutions and alterations to the above embodiments without departing from the scope of the present invention.
Claims (10)
1. An 18-channel high-precision constant-current LED driving chip is characterized in that the driving chip is provided with a displacement temporary storage, and the displacement temporary storage comprises: 18 constant current output pins, a serial data input pin DI, an input pin DCK of a data clock signal, an input pin PDM of a gray scale modulation signal, a serial data output pin DO, an input pin REXT, a power grounding pin VDD and a grounding end GND pin for controlling logic and driving current;
the 18 constant current output pins comprise 6 red current output pins, 6 green current output pins and 6 blue current output pins.
2. The driver chip of claim 1,
the serial data output pin DO is used for being connected in series with an external driving chip.
3. The driver chip of claim 2,
the input pin REXT is used for connecting with an external resistor.
4. The driver chip of claim 3,
the operating voltage of the chip is 3.3 to 5.0 volts.
5. The driver chip according to claim 4,
the chip has a 24-pin QFN package type.
6. The driver chip of claim 5,
the QFN packaging type of the driving chip specifically includes: QFN24-2mmx5mm-0.4mm package type or QFN24-3mmx4mm-0.4mm package type.
7. The driver chip of claim 6,
the QFN24-2mmx5mm-0.4mm packaging type of the driving chip is as follows: the length of the chip is 5mm, and the width of the chip is 2 mm; the two long sides of the chip respectively comprise 11 pins, and the two wide sides of the chip respectively comprise 2 pins; the two long edges of the chip are a bottom edge and a top edge; wherein, be provided with from the anticlockwise order on the chip base: a green current output pin, a red current output pin, a blue current output pin, a green current output pin, a GND pin, a red current output pin, a blue current output pin, a green current output pin, a red current output pin, a power ground pin VDD, an input pin DI, an input pin DCK, an input pin PDM, an output pin DO, an input pin REXT, a ground terminal GND pin, a blue current output pin, a green current output pin, a red current output pin, and a blue current output pin;
the QFN24-3mmx4mm-0.4mm packaging type of the driving chip is as follows: the QFN packaging type of the chip is that the length of the chip is 4mm, and the width of the chip is 3 mm; the two long sides of the chip respectively comprise 7 pins, and the two wide sides of the chip respectively comprise 5 pins; the two long edges of the chip are a bottom edge and a top edge; wherein, be provided with from the anticlockwise order on the chip base: a red current output pin, a power ground pin VDD, an input pin DI, an input pin DCK, an input pin PDM, an output pin DO, an input pin REXT, a blue current output pin, a green current output pin, a red current output pin, a blue current output pin, a green current output pin, a red current output pin, a blue current output pin, and a green current output pin; and the top surface of the chip is also provided with a grounding end GND pin.
8. The driver chip of claim 7,
the driving chip is provided with preset delay time among output currents of the red current output pin, the green current output pin and the blue current output pin.
9. The driver chip of claim 8,
the chip is internally provided with a ghost shadow eliminating program for eliminating the uplink ghost shadow and the downlink ghost shadow when the driving chip is matched with a system hardware circuit.
10. The driver chip of claim 9,
the driving chip is also pre-built with a double-latch display technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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