CN113156294B - Thermal control method and device for chip burn-in test - Google Patents
Thermal control method and device for chip burn-in test Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 647
- 238000000034 method Methods 0.000 title claims abstract description 70
- 238000001816 cooling Methods 0.000 claims description 51
- 230000008569 process Effects 0.000 claims description 26
- 238000010792 warming Methods 0.000 claims description 19
- 230000004044 response Effects 0.000 claims description 15
- 238000004590 computer program Methods 0.000 claims description 8
- 230000032683 aging Effects 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 abstract description 16
- 238000012545 processing Methods 0.000 description 9
- 239000002826 coolant Substances 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
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- 230000000694 effects Effects 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating
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Abstract
Disclosed herein are a thermal control method and apparatus for chip burn-in test, wherein the thermal control method for chip burn-in test includes: for each test item, determining whether the current test item is a test item executable at a specified standard test temperature; responding to the determined result, judging whether the risk level of the thermal fault in the current test item is greater than that of the thermal fault in the previous test item; if the judgment result is yes, the test temperature of the current test item is kept consistent with the test temperature of the previous test item; if the result of the judgment is negative, setting the test temperature of the current test item relative to the test temperature of the previous test item, wherein the set test temperature of the current test item is not higher than the standard test temperature, and wherein the setting comprises determining the heating amplitude of the test temperature of the current test item relative to the test temperature of the previous test item.
Description
Technical Field
The present disclosure relates to thermal control methods and apparatus for chip burn-in testing.
Background
The advanced fabrication of semiconductor chips, including the packaging stage, may introduce some minor defects that are difficult to avoid, which is becoming more common as the scale and complexity of the chip circuitry increases rapidly. These defects may be exposed shortly after the product is delivered to the user's hand. Burn-in test (burn-in test) is one of the important inspection processes before the chip leaves the factory, and aims to accelerate the exposure of defects inside the chip by the action of two factors of high temperature and high voltage so as to help ensure the reliability of the inspected chip leaves the factory.
For burn-in testing, especially for machines that burn-in test a large number of chips at a time, thermal/temperature control during testing is a significant challenge. Under high temperature and high pressure environments, the chip heating value is very high, and the control and heat dissipation capabilities of the test machine may not be sufficiently powerful and timely. Under the condition, catastrophic thermal runaway is easy to occur because the thermal control applied by the testing machine is not timely, and the testing machine cannot timely emit the heat emitted by the chip in the changing process of damage of the chip due to overheat, so that the thermal failure is caused, and the chip can be burnt. Moreover, while burning out the chip, the special slots for carrying the chip for burn-in test may also be burned out together, resulting in a greater test cost loss.
Disclosure of Invention
In the summary, some selected concepts are presented in a simplified form as further described below in the detailed description. This summary is not intended to identify any critical or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
According to one aspect of the present disclosure, there is provided a thermal control method for chip burn-in testing, the method comprising: for each of a plurality of test items included in the burn-in test, determining whether a current test item is a test item that can be performed at a prescribed standard test temperature without performing a pre-cooling process; in response to determining that the current test item is a test item executable at the standard test temperature, determining whether a risk level of occurrence of a thermal fault in the current test item is greater than a risk level of occurrence of a thermal fault in a previous test item; if the judgment result is yes, keeping the test temperature of the current test item consistent with the test temperature of the previous test item; if the result of the judgment is negative, setting the test temperature of the current test item relative to the test temperature of the previous test item, wherein the set test temperature of the current test item is not higher than the standard test temperature, and wherein the setting comprises determining the heating amplitude of the test temperature of the current test item relative to the test temperature of the previous test item.
According to another aspect of the present disclosure, there is provided a computing device comprising: at least one processor; and a memory coupled to the at least one processor and configured to store instructions, wherein the instructions, when executed by the at least one processor, cause the at least one processor to: for each of a plurality of test items included in the chip burn-in test, determining whether the current test item is a test item that can be executed at a prescribed standard test temperature without performing a pre-cooling process; in response to determining that the current test item is a test item executable at the standard test temperature, determining whether a risk level of occurrence of a thermal fault in the current test item is greater than a risk level of occurrence of a thermal fault in a previous test item; if the judgment result is yes, keeping the test temperature of the current test item consistent with the test temperature of the previous test item; if the result of the judgment is negative, setting the test temperature of the current test item relative to the test temperature of the previous test item, wherein the set test temperature of the current test item is not higher than the standard test temperature, and wherein the setting comprises determining the heating amplitude of the test temperature of the current test item relative to the test temperature of the previous test item.
According to yet another aspect of the present disclosure, a computer-readable storage medium is provided, having instructions stored thereon, which when executed by at least one processor, cause the at least one processor to perform the method described herein.
According to yet another aspect of the present disclosure, a computer program product is provided comprising instructions that, when executed by at least one processor, cause the at least one processor to perform the method described herein.
Drawings
Implementations of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to identical or similar elements and in which:
FIG. 1 shows a specific example of the prior art;
FIG. 2 illustrates a flow chart of an exemplary method according to some implementations of the present disclosure;
FIG. 3 illustrates a flow chart of exemplary operations according to some implementations of the present disclosure;
FIG. 4 illustrates one specific example of some implementations according to the present disclosure;
FIG. 5 illustrates a block diagram of an exemplary apparatus according to some implementations of the disclosure; and
Fig. 6 illustrates a block diagram of an exemplary computing device, in accordance with some implementations of the disclosure.
Detailed Description
In the following description, for purposes of explanation, numerous specific details are set forth. However, it is understood that implementations of the present disclosure may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.
References throughout this specification to "one implementation," "an implementation," "example implementations," "some implementations," "various implementations," etc., indicate that the implementations of the disclosure described may include particular features, structures, or characteristics, but every implementation may not necessarily include the particular features, structures, or characteristics. Furthermore, some implementations may have some, all, or none of the features described for other implementations.
Various operations may be described as multiple discrete acts or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, the operations may be performed out of the order presented. In other implementations, various additional operations may also be performed, and/or various operations already described may be omitted.
In the description and claims, the phrase "a and/or B" as may occur is used to denote one of the following: (A), (B), (A and B). Similarly, the phrase "A, B and/or C" as may occur is used to denote one of the following: (A), (B), (C), (A and B), (A and C), (B and C), (A and B and C).
In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. In contrast, in particular implementations, "connected" is used to indicate that two or more elements are in direct physical or electrical contact with each other, and "coupled" is used to indicate that two or more elements cooperate or interact with each other, although they may or may not be in direct physical or electrical contact.
The aging test of the chip accelerates exposing some defects possibly introduced in the chip at the early manufacturing stage including the packaging stage by placing the tested chip under the action of high temperature and high voltage, improves the reliability of the product delivered from the factory, and effectively reduces the early failure rate after the product is delivered into the hand of a user. Typically, a batch of chips are placed in respective sockets and moved into a test machine, and a round of burn-in testing is performed based on control of the test machine, which is capable of collecting and outputting statistical data associated with the round of burn-in testing for review, processing, and analysis as needed. Each round of burn-in testing often contains up to tens or even hundreds of different test items, sometimes referred to as test content or patterns (patterns), that are executed in sequence, each test item may be a few seconds in time and tens of seconds or more in time. By way of example and not limitation, for a particular chip under test, such different test items may correspond to different circuit portions of the chip, e.g., a first test item may be for a Central Processing Unit (CPU) portion of the chip, a second test item may be for an input/output (I/O) circuit portion of the chip, and so on.
In practical applications, there is a requirement on capacity/productivity per unit time for a test machine, and one test machine performs burn-in test for a batch of chips at a time, so control resources allocated to each chip are often limited. However, during the burn-in test, the chip to be tested is in a high-temperature and high-voltage environment, so that the heat productivity is very high, and the chip is damaged due to overheating. If the testing machine can not perform timely and effective heat control on the tested chip, the surface temperature of the chip is reduced as soon as possible by increasing the dosage of the coolant, so that the heat emitted by the inside of the chip is timely emitted, and the chip, even a special slot for bearing the chip, can be burnt together, so that very large loss is caused.
In order to be able to achieve optimal test effectiveness, it is desirable that all test items of the entire burn-in test be performed at a uniform standard test temperature (e.g., 100 degrees). However, from a test machine perspective, its heat dissipation system often does not accurately and timely control each test item at such standard test temperatures. Specifically, the test actions of different test items are not the same, and thus there is a great difference in the heat generating manner, for example, some test items can make the load of the chip very large and thus the heat generating amount very high, while other test items can make the load of the chip change very fast and thus heat quickly, which may cause thermal runaway and finally burn out the chip. For such and other test machines to be difficult to perform timely and accurate heat dissipation, pre-cooling treatment is required for the test items, and the surface temperature of the chip is reduced to and maintained at a lower temperature (for example, 93 degrees) by further increasing the coolant dosage at the beginning of the test items, so as to ensure the heat dissipation effect of the chip, thereby enabling the chip to smoothly undergo those test actions of the test items without overheating.
After such test items requiring pre-cooling treatment are completed, the test machine is subjected to another thermal control condition, i.e., warming. For later test projects that can be performed at the prescribed standard test temperature (which often accounts for most of the total test projects), the test machine should control its heat dissipation system so that the test temperature rises from a lower temperature (e.g., 93 degrees) in the case of the previous pre-cool down process back to the standard test temperature (e.g., 100 degrees) to ensure test effectiveness. This warming process is often accomplished by the test machine reducing or even suspending the coolant supply. In other words, both the previous cooling and the heating up are realized by controlling the opening of the coolant valve by the test machine, and the opening of the coolant valve is instructed to be increased when the cooling is needed, and the opening of the coolant valve is instructed to be decreased or even turned off when the heating up is needed. This temperature increase from the lower temperature in the case of pre-soak back to the standard test temperature also causes thermal runaway that may cause serious loss of some of the test chips to be burned out.
Reference is now first made to fig. 1, which shows a specific example of the prior art. As shown in fig. 1, the standard test temperature prescribed for the burn-in test in this example is 100 degrees and includes a plurality of test items, wherein the kth-1 test item is a test item requiring a pre-cooling treatment (here, down to 93 degrees), and the kth, k+1, k+2, k+3 … test items immediately following this are test items that can be directly executed at the standard test temperature without performing the pre-cooling treatment.
As shown in FIG. 1, the test temperature of the test item was lowered to 93 degrees by pre-cooling the (k-1) th test item. It can be seen here that there is an upward spike in the temperature profile at the beginning of the test item, which is due to the heating pattern/characteristics of the test item that requires pre-cooling, and the heat dissipation system of the test machine is often unable to react in time to the heating of the test item, so there is a brief rise in temperature at the beginning of the test item. And along with the control instruction of the test machine, the opening degree of the coolant valve is increased, so that a cooling effect is rapidly generated to lower the temperature to 93 degrees. After the test action of the kth-1 test item is completed at 93 degrees, the temperature is once raised directly back to the standard test temperature of 100 degrees to accommodate the next kth test item. However, one problem with this approach is that, as shown by the dashed line at the end of the warm-up line from 93 degrees to 100 degrees in fig. 1, the test machine would instruct the coolant valve to be as small as possible and even shut off due to the temperature difference of up to 7 degrees, the chip would warm up quickly with reduced or even absent cooling protection, the temperature would quickly break through 100 degrees and thermal runaway would occur, causing many chips to burn out during the return from 93 degrees to 100 degrees.
Although there may be a way to reduce the above risk by slowing down the temperature rise speed or the like, these ways inevitably lengthen the temperature rise time while reducing the risk. Excessive time spent in the warm-up process in turn reduces the time duty of the test item and even the truly valid test portion of the entire burn-in process, which is unacceptable for practical production environments where test throughput and test effectiveness need to be guaranteed.
Fig. 2 illustrates a flow chart of an exemplary method 200 according to some implementations of the present disclosure. The method 200 may be used to thermally control chip burn-in testing. As shown in fig. 2, the method 200 starts at step 210, in which it is determined, for one of a plurality of test items included in the burn-in test (hereinafter also referred to as a "current test item"), whether the current test item is a test item that can be executed at a prescribed standard test temperature without performing a pre-cooling process.
According to some implementations of the present disclosure, each of the plurality of test items of the burn-in test may be assigned a corresponding risk level of occurrence of a thermal fault. Whether a thermal fault is more likely to occur in a test item can be determined by the level of risk, and in some implementations, whether a test item is one that requires pre-cooling can be determined by the level of risk.
In some implementations, first, a plurality of rounds of burn-in testing is scheduled to be completed at a standard test temperature, and a risk level for thermal faults occurring in each of a plurality of test items of the burn-in testing may be determined based on collected historical statistics associated with the completed burn-in testing.
Turning first to fig. 3, a flow chart of exemplary operations 300 according to some implementations of the present disclosure is shown. The risk level of occurrence of a thermal fault in a test item may be determined by performing operation 300. First, step 310 is performed to identify thermal faults indicated in the historical statistics. As previously mentioned, the collected historical statistics are related to multiple rounds of burn-in testing that have been completed at standard test temperatures, from which various possible faults that occur during the burn-in test can be determined. Step 310 screens out those faults that are related to thermal control during the burn-in test. In some implementations, such thermal faults may be determined by the following conditions indicated in the historical statistics, including, but not limited to: shutdown (burn-out) of the on-chip integrated power management portion, supply voltage (Vcc) becoming minimum, vcc becoming maximum, and so forth. These very dangerous conditions are all a specific manifestation of thermal runaway.
Next, step 320 is performed in which, for each thermal fault identified, a test item corresponding to that thermal fault is determined. In some implementations, the time of occurrence of each thermal fault indicated in the historical statistics may be referenced against a test program log of the test machine to determine during which particular test item the thermal fault occurred.
Operation 300 then proceeds to step 330 where the occurrence of thermal faults for each of the plurality of test items is counted based on the results of the determination. In some implementations, the number of thermal faults occurring in each of the plurality of test items may be counted based on the results of step 320, and then the number of thermal faults per test item divided by the total number of chips tested for the completed multiple round burn-in test may be used to derive the incidence of thermal faults for the chips per test item.
Finally, step 340 is performed in which one of a plurality of risk levels is assigned to each of the plurality of test items based on the counted occurrence of thermal faults. It will be appreciated that the number of risk levels is less than the number of the plurality of test items. The number of risk levels may be set as desired. For example, in one example, three risk levels, high, medium, and low, each corresponding to a different range of thermal failure occurrence, may be set, thereby assigning one of the three risk levels to each of the plurality of test items. In another example, more risk levels may be set from high to low, test items with a thermal failure rate higher than a specified first threshold are classified as belonging to the highest one, test items with a thermal failure rate higher than a specified second threshold without exceeding the above-mentioned first threshold are classified as belonging to the second highest one, and so on. Those skilled in the art will appreciate that the present disclosure is not limited to the examples described above, and that other designations/divisions are possible.
Furthermore, it will be appreciated that a higher risk level for a thermal fault in a test item generally means that pre-cooling treatment is more necessary for that test item, since the completed burn-in test indicates that thermal faults are likely to occur when the test item is executed at the prescribed standard test temperature. In some implementations, the highest risk level(s) corresponds to a case where a pre-cool down process is required. Moreover, in some implementations, the target temperature for the pre-cool down process may be more than one. For example, the reduced temperature may be 93 degrees, 96 degrees with respect to 100 degrees as an example of the standard test temperature, where the lowest 93 degrees may correspond to the highest one of the risk levels, while the next lowest 96 degrees may correspond to the next highest one of the risk levels, and test items with the remaining risk levels may be considered to belong to test items that may be executed at the standard test temperature of 100 degrees. It is also to be understood that the above description is intended to be illustrative of the present disclosure and not limiting, and that other implementations are possible.
Thus, returning to FIG. 2, in some implementations, the determination in step 210 of whether the current test item is a test item that can be performed at a prescribed standard test temperature without pre-cooling processing may be made based on a risk level for thermal faults specified for the current test item.
In response to the determination at step 210 being yes, i.e., the current test item may be performed at the prescribed standard test temperature without requiring pre-cooling processing for it (e.g., which may correspond to the case of the kth, k+1, k+2, k+3 … test items in the example of fig. 1), method 200 proceeds to step 220. In step 220, a determination is made as to whether the risk level of occurrence of a thermal fault in the current test item is greater than the risk level of occurrence of a thermal fault in the previous test item, which may be accomplished by comparing the risk levels specified in the manner described above for the current test item and the previous test item.
If the determination at step 220 is yes, i.e., the risk level of the current test item is greater than the risk level of the previous test item, the method 200 proceeds to step 230. In step 230, the test temperature of the current test item is maintained consistent with the test temperature of the previous test item. As can be understood from the foregoing description, the current test item is a test item that does not need to be subjected to the pre-cooling process, and it is determined in step 220 that the risk level of the current test item is greater than that of the previous test item, which means that the previous test item is also a test item that does not need to be subjected to the pre-cooling process. In this case, the test temperature of the current test item does not need to be set to be changed from the test temperature of the previous test item, but the two are kept identical. Examples of the step 230 may be found in the description below.
On the other hand, if the determination at step 220 is negative, i.e., the risk level of the current test item is less than or equal to the risk level of the previous test item, then the method 200 proceeds to step 240. In step 240, the test temperature of the current test item is set relative to the test temperature of the previous test item, wherein the set test temperature of the current test item is not higher than the standard test temperature, and wherein the setting comprises determining a magnitude of an increase in the test temperature of the current test item relative to the test temperature of the previous test item. It will be appreciated from the foregoing description that the current test item is a test item that does not require pre-cooling, and that in step 220 it is determined that the risk level of the current test item is less than or equal to the risk level of the previous test item, meaning that the previous test item may be the same test item that does not require pre-cooling (but at least equal risk level relative to the current test item) or may be a test item that has a very high risk level that requires pre-cooling. In either case, however, the basic principle in step 240 is to set the test temperature of the current test item, and more specifically to raise the test temperature of the current test item relative to the test temperature of the previous test item.
In some implementations, the magnitude of the rise in the test temperature of the current test item relative to the test temperature of the previous test item is determined based at least in part on the degree of difference between the risk level of the current test item and the risk level of the previous test item. The greater the difference between the front and rear risk levels, the greater the corresponding temperature increase range should be. There may be a linear, or non-linear relationship defined between the two, such definition may be made by one skilled in the art depending on the actual needs or constraints. In addition, it may be further provided that if two risk levels are equal, the corresponding temperature rise amplitude is a smaller value to ensure a smooth transition, and likewise, such provision may be made depending on actual needs or constraints, and the disclosure is not particularly limited in this respect. Furthermore, it should be noted that the temperature should be ensured that the test temperature eventually set for the current test item is not higher than the standard test temperature, regardless of how the temperature is raised. In other words, assuming that the test temperature set for the previous test item is already the standard test temperature, the temperature increase amplitude thereof with respect to the test temperature of the previous test item is zero when the test temperature is set for the current test item in step 240.
Further, in some implementations, the operation of determining the temperature increase amplitude in step 240 may also be dynamically adjusted as the burn-in test is performed. More specifically, if the statistical data related to the current test item executed according to the determined temperature increase amplitude indicates that the occurrence rate of thermal faults corresponding to the current test item does not satisfy a preset criterion, the temperature increase amplitude is reduced for the current test item in the next round of the burn-in test. In one example, the preset criteria may be an appropriate fixed value, which is determined according to actual requirements or constraints; in another example, the preset criteria may refer to the occurrence of thermal faults of the current test item in the round of burn-in testing being higher than the occurrence of thermal faults of the current test item in the previous round of burn-in testing, although the disclosure is not limited thereto.
Further, if the determination at step 210 is no, i.e., the current test item is a test item requiring a pre-cool down process, the method 200 proceeds to step 250. In step 250, the test temperature of the current test item is set to a reduced temperature that is lower than the standard test temperature. In some implementations, the reduced temperature corresponds to a risk level for the test item. With reference to the previous example, if the risk levels differ, such as highest and next highest, respectively, the corresponding reduced temperatures will also differ, such as 93 degrees and 96 degrees, respectively. In other implementations, the corresponding reduced temperatures may be uniform, e.g., 93 degrees, although the risk levels may be different, e.g., highest and next highest, respectively, and both risk levels may correspond to situations where a reduced temperature treatment is desired.
According to some implementations of the present disclosure, after the processing of steps 230, 240, or 250 is completed, the method 200 proceeds to step 260 where it is determined whether there are more test items to process among the plurality of test items. If the determination is negative, the method 200 may end; if yes, then the process proceeds to the next test item in step 270 and then returns to the process beginning at step 210.
Fig. 4 illustrates one specific example of some implementations according to the present disclosure. Similar to the case shown in FIG. 1, in FIG. 4, the (k-1) th test item is a test item requiring pre-cooling down to 93 degrees, and the (k, k+1, k+2, k+3 …) th test items immediately following the (k+1) th test item are test items requiring no pre-cooling down. With an implementation according to the present disclosure, in this example, each test item is assigned one of four thermal fault risk levels, from low to high A, B, C, D, with the kth-1 test item having the highest risk level D and the risk levels of the kth, k+1, k+2, k+3 test items being A, C, B, A, respectively. And, depending on the degree of difference between these four risk levels, the possible heating amplitudes are respectively set to 4, 3, 2 degrees, i.e., 4 degrees from D to a, 3 degrees from D to B, or C to a, 2 degrees from D to C, C to B, or B to a. Looking specifically at this example, for the kth test item that does not require pre-cooling, whose risk level A is less than the risk level D of the kth-1 test item (i.e., as in the case described above with respect to step 240), its test temperature may be set to be raised by 4 degrees relative to 93 degrees of the kth-1 test item, up to 97 degrees. For the (k+1) th test item, whose risk level C is greater than the risk level A of the (k) th test item (i.e., as in the case described above with respect to step 230), its test temperature may be maintained consistent with the (k) th test item, i.e., at 97 degrees. For the k+2th test item, its risk level B is less than the risk level C of the k+1th test item, its test temperature may be set to be raised by 2 degrees up to 99 degrees with respect to 97 degrees of the k+1th test item. Then, for the k+3th test item, the risk level a thereof is smaller than the risk level B of the k+2th test item, and the test temperature thereof may be set to be raised by 2 degrees with respect to 99 degrees of the k+2th test item, however, since the standard test temperature is 100 degrees, the test temperature of the k+3th test item is set to 100 degrees at the end. For the subsequent test items after the (k+3) th test item, if it is also a test item that does not require the pre-cooling treatment, it can be kept to be performed at the standard test temperature of 100 degrees.
By utilizing the mode provided by the disclosure, better heat control can be realized for the chip aging test, smooth rising of temperature can be ensured in a heating link, thermal runaway which is easy to cause due to heating in the mode shown in fig. 1 is effectively reduced, and the occurrence rate of heat faults is reduced. Moreover, as the mode disclosed in the disclosure executes a plurality of subsequent test items in the heating link, the test time is effectively saved, and the productivity of the test machine is ensured.
Furthermore, in some implementations, the exemplary method 200 may also include an optional step 280. As shown in fig. 2, step 280 may be performed subsequent to step 260. Specifically, if it is determined in step 260 that the plurality of test items have all undergone the aforementioned processing, then step 280 may be advanced. In step 280, the execution order of the plurality of test items is adjusted such that at least one test item of the plurality of test items requiring pre-cooling is executed immediately after another test item of the plurality of test items requiring pre-cooling that was executed previously, wherein the at least one test item is not pre-conditioned on execution of other test items between the another test item and the at least one test item. By arranging a plurality of test items requiring pre-cooling treatment together in a test sequence under the allowable condition, the number of heating processes required after the test items requiring pre-cooling treatment can be effectively reduced, and the test items requiring no pre-cooling treatment can be ensured to be executed at standard test temperatures to a greater extent. In some implementations of the present disclosure, the adjusting performed in step 280 may be performed in response to determining that the average test temperature of the plurality of test items is below a specified average test temperature threshold. The specified average test temperature threshold may correspond to a minimum temperature requirement that meets test effectiveness.
Referring now to fig. 5, a block diagram of an exemplary apparatus 500 is shown in accordance with some implementations of the present disclosure. The apparatus 500 may be used to thermally control chip burn-in testing. In some implementations, the apparatus 500 may be implemented within a test machine for performing chip burn-in testing, and in other implementations, the apparatus 500 may be implemented in a computing device associated with the test machine, although the disclosure is not limited in this regard.
As shown in fig. 5, the apparatus 500 may include a module 510 for determining, for each of a plurality of test items included in the burn-in test, whether a current test item is a test item that can be performed at a prescribed standard test temperature without performing a pre-cool down process. The apparatus 500 may further include a module 520 for determining whether a risk level of occurrence of a thermal fault in the current test item is greater than a risk level of occurrence of a thermal fault in a previous test item in response to determining that the current test item is a test item executable at the standard test temperature. The apparatus 500 may further comprise a module 530 for keeping the test temperature of the current test item consistent with the test temperature of the previous test item if the determination is yes. In addition, the apparatus 500 may further comprise a module 540 for setting the test temperature of the current test item with respect to the test temperature of the previous test item if the result of the determination is no, wherein the set test temperature of the current test item is not higher than the standard test temperature, and wherein the setting comprises determining a heating amplitude of the test temperature of the current test item with respect to the test temperature of the previous test item.
In some implementations, further modules may be included in one or more of the above-described modules of apparatus 500, and/or additional modules may be included in apparatus 500 for performing other operations already described in the specification, such as described in connection with the flow chart of exemplary method 200 of fig. 2, the flow chart of exemplary operation 300 of fig. 3. Moreover, in some implementations, the various modules of apparatus 500 may also be combined or split depending on the actual needs, as well as falling within the scope of the present disclosure.
Those of skill in the art will appreciate that the exemplary apparatus 500 may be implemented in software, hardware, firmware, or any combination thereof.
Fig. 6 illustrates a block diagram of an exemplary computing device 600, in accordance with some implementations of the disclosure. The computing device 600 may be used to thermally control chip burn-in testing. In some implementations, computing device 600 may be part of a test machine for performing chip burn-in testing, and in other implementations, computing device 600 may be implemented as a stand-alone control device associated with a test machine, although the disclosure is not limited thereto.
As shown in fig. 6, computing device 600 may include at least one processor 610. The processor 610 may include any type of general purpose processing unit (e.g., CPU, GPU, etc.), special purpose processing unit, core, circuitry, controller, etc. In addition, computing device 600 may also include memory 620. Memory 620 may include any type of medium that may be used to store data. In some implementations, the memory 620 is configured to store instructions that, when executed, cause the at least one processor 610 to perform the operations described herein, e.g., described in connection with the flowchart of the exemplary method 200 of fig. 2, the flowchart of the exemplary operation 300 of fig. 3.
Furthermore, in some implementations, computing device 600 may also be coupled to or equipped with one or more peripheral components, which may include, but are not limited to, a display, speakers, a mouse, a keyboard, and the like. Additionally, in some implementations, computing device 600 may also be equipped with a communication interface, which may support various types of wired/wireless communication protocols for communicating with a communication network. Examples of communication networks may include, but are not limited to: local Area Networks (LANs), metropolitan Area Networks (MANs), wide Area Networks (WANs), public telephone networks, the internet, intranets, the internet of things, infrared networks, bluetooth networks, near Field Communication (NFC) networks, zigBee networks, and the like.
Further, in some implementations, the above and other components may communicate with each other via one or more buses/interconnects that may support any suitable bus/interconnect protocol, including Peripheral Component Interconnect (PCI), PCI express, universal Serial Bus (USB), serial Attached SCSI (SAS), serial ATA (SATA), fibre Channel (FC), system management bus (SMBus), or other suitable protocol.
Those skilled in the art will appreciate that the above description of the structure of computing device 600 is by way of example only and not by way of limitation, and that other structures of devices are possible as long as they can be used to implement the functionality described herein.
Various implementations of the present disclosure may be realized using hardware elements, software elements, or a combination thereof. Examples of hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application Specific Integrated Circuits (ASIC), programmable Logic Devices (PLD), digital Signal Processors (DSP), field Programmable Gate Array (FPGA), memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application Program Interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining an implementation to implement using hardware elements and/or software elements may vary depending on a variety of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation.
Some implementations of the present disclosure may include an article of manufacture. The article of manufacture may comprise a storage medium to store logic. Examples of a storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. Examples of logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application Program Interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. In some implementations, for example, an article of manufacture may store executable computer program instructions that, when executed by a processor, cause the processor to perform the methods and/or operations described herein. The executable computer program instructions may comprise any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The executable computer program instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a computer to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.
Some exemplary implementations of the present disclosure are described below:
Example 1 may include a thermal control method for chip burn-in testing, the method comprising: for each of a plurality of test items included in the burn-in test, determining whether a current test item is a test item that can be performed at a prescribed standard test temperature without performing a pre-cooling process; in response to determining that the current test item is a test item executable at the standard test temperature, determining whether a risk level of occurrence of a thermal fault in the current test item is greater than a risk level of occurrence of a thermal fault in a previous test item; if the judgment result is yes, keeping the test temperature of the current test item consistent with the test temperature of the previous test item; if the result of the judgment is negative, setting the test temperature of the current test item relative to the test temperature of the previous test item, wherein the set test temperature of the current test item is not higher than the standard test temperature, and wherein the setting comprises determining the heating amplitude of the test temperature of the current test item relative to the test temperature of the previous test item.
Example 2 may include the subject matter of example 1, wherein the method further comprises: for each test item of the plurality of test items for which the pre-cooling treatment is required, setting a test temperature of the test item to a reduced temperature corresponding to a risk level of the test item.
Example 3 may include the subject matter of example 1, wherein the warming magnitude is determined based at least in part on a degree of difference between risk levels of the current test item and the previous test item.
Example 4 may include the subject matter of example 1, wherein the method further comprises: and adjusting the execution sequence of the plurality of test items so that at least one test item requiring the pre-cooling treatment among the plurality of test items is executed immediately after another test item requiring the pre-cooling treatment, which is executed before, wherein the at least one test item does not have the execution of other test items between the another test item and the at least one test item as a precondition.
Example 5 may include the subject matter of example 4, wherein the adjusting is performed in response to determining that an average test temperature of the plurality of test items is below a specified average test temperature threshold.
Example 6 may include the subject matter of example 1, wherein if the statistical data related to the current test item performed according to the determined warming amplitude indicates that a thermal failure occurrence rate corresponding to the current test item does not meet a preset criterion, the warming amplitude is reduced for the current test item in the burn-in test of a next round.
Example 7 may include the subject matter of example 1, wherein the risk level of occurrence of a thermal fault in each of the plurality of test items is determined based on historical statistics related to a plurality of rounds of the burn-in test that have been completed at the standard test temperature.
Example 8 may include the subject matter of example 7, wherein the determining of the risk level comprises: identifying a thermal fault indicated in the historical statistics; determining a test item corresponding to each of the identified thermal faults; counting a thermal failure occurrence rate of each of the plurality of test items based on a result of the determining; each of the plurality of test items is assigned one of a plurality of risk levels based on the counted occurrence of thermal faults.
Example 9 may include a computing device comprising: at least one processor; and a memory coupled to the at least one processor and configured to store instructions, wherein the instructions, when executed by the at least one processor, cause the at least one processor to: for each of a plurality of test items included in the chip burn-in test, determining whether the current test item is a test item that can be executed at a prescribed standard test temperature without performing a pre-cooling process; in response to determining that the current test item is a test item executable at the standard test temperature, determining whether a risk level of occurrence of a thermal fault in the current test item is greater than a risk level of occurrence of a thermal fault in a previous test item; if the judgment result is yes, keeping the test temperature of the current test item consistent with the test temperature of the previous test item; if the result of the judgment is negative, setting the test temperature of the current test item relative to the test temperature of the previous test item, wherein the set test temperature of the current test item is not higher than the standard test temperature, and wherein the setting comprises determining the heating amplitude of the test temperature of the current test item relative to the test temperature of the previous test item.
Example 10 may include the subject matter of example 9, wherein the at least one processor is further to: for each test item of the plurality of test items for which the pre-cooling treatment is required, setting a test temperature of the test item to a reduced temperature corresponding to a risk level of the test item.
Example 11 may include the subject matter of example 9, wherein the warming magnitude is determined based at least in part on a degree of difference between risk levels of the current test item and the previous test item.
Example 12 may include the subject matter of example 9, wherein the at least one processor is further to: and adjusting the execution sequence of the plurality of test items so that at least one test item requiring the pre-cooling treatment among the plurality of test items is executed immediately after another test item requiring the pre-cooling treatment, which is executed before, wherein the at least one test item does not have the execution of other test items between the another test item and the at least one test item as a precondition.
Example 13 may include the subject matter of example 12, wherein the adjusting is performed in response to determining that an average test temperature of the plurality of test items is below a specified average test temperature threshold.
Example 14 may include the subject matter of example 9, wherein if the statistical data related to the current test item performed according to the determined warming amplitude indicates that a thermal failure occurrence rate corresponding to the current test item does not meet a preset criterion, the warming amplitude is reduced for the current test item in the next round of the burn-in test.
Example 15 may include the subject matter of example 9, wherein the risk level of occurrence of a thermal fault in each of the plurality of test items is determined based on historical statistics related to a plurality of rounds of the burn-in test that have been completed at the standard test temperature.
Example 16 may include the subject matter of example 15, wherein the determining of the risk level includes: identifying a thermal fault indicated in the historical statistics; determining a test item corresponding to each of the identified thermal faults; counting a thermal failure occurrence rate of each of the plurality of test items based on a result of the determining; each of the plurality of test items is assigned one of a plurality of risk levels based on the counted occurrence of thermal faults.
Example 17 may include a thermal control apparatus for chip burn-in testing, the apparatus comprising: means for determining, for each of a plurality of test items included in the burn-in test, whether a current test item is a test item that can be executed at a prescribed standard test temperature without performing a pre-cooling process; in response to determining that the current test item is a test item executable at the standard test temperature, determining whether a risk level of occurrence of a thermal fault in the current test item is greater than a risk level of occurrence of a thermal fault in a previous test item; if the result of the judgment is yes, the test temperature of the current test item is kept consistent with the test temperature of the previous test item; and if the result of the determination is no, setting the test temperature of the current test item with respect to the test temperature of the previous test item, wherein the set test temperature of the current test item is not higher than the standard test temperature, and wherein the setting includes determining a temperature increase amplitude of the test temperature of the current test item with respect to the test temperature of the previous test item.
Example 18 may include the subject matter of example 17, wherein the apparatus further comprises: and a module for setting, for each of the plurality of test items for which the pre-cooling process is required, a test temperature of the test item to a reduced temperature corresponding to a risk level of the test item.
Example 19 may include the subject matter of example 17, wherein the warming magnitude is determined based at least in part on a degree of difference between risk levels of the current test item and the previous test item.
Example 20 may include the subject matter of example 17, wherein the apparatus further comprises: and means for adjusting an execution order of the plurality of test items such that at least one test item of the plurality of test items requiring the pre-cooling process is executed immediately after another test item of the plurality of test items requiring the pre-cooling process that is executed previously, wherein the at least one test item is not pre-conditioned on execution of the other test item between the another test item and the at least one test item.
Example 21 may include the subject matter of example 20, wherein the adjusting is performed in response to determining that an average test temperature of the plurality of test items is below a specified average test temperature threshold.
Example 22 may include the subject matter of example 17, wherein if the statistical data related to the current test item performed according to the determined warming amplitude indicates that a thermal failure occurrence rate corresponding to the current test item does not meet a preset criterion, the warming amplitude is reduced for the current test item in the next round of the burn-in test.
Example 23 may include the subject matter of example 17, wherein the risk level of occurrence of a thermal fault in each of the plurality of test items is determined based on historical statistics related to a plurality of rounds of the burn-in test that have been completed at the standard test temperature.
Example 24 may include the subject matter of example 23, wherein the determining of the risk level comprises: identifying a thermal fault indicated in the historical statistics; determining a test item corresponding to each of the identified thermal faults; counting a thermal failure occurrence rate of each of the plurality of test items based on a result of the determining; each of the plurality of test items is assigned one of a plurality of risk levels based on the counted occurrence of thermal faults.
Example 25 may include a computer-readable storage medium having instructions stored thereon that, when executed by at least one processor, cause the at least one processor to perform any of the methods described in the present disclosure.
Example 26 may include a computer program product comprising instructions that, when executed by at least one processor, cause the at least one processor to perform any of the methods described in the present disclosure.
What has been described above includes examples of the disclosed architecture. It is, of course, not possible to describe every conceivable combination of components and/or methodologies, but one of ordinary skill in the art may recognize that many further combinations and permutations are possible. Accordingly, the novel architecture is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope of the appended claims.
Claims (16)
1. A thermal control method for chip burn-in testing, comprising:
For each of a plurality of test items included in the burn-in test, determining whether a current test item is a test item that can be performed at a prescribed standard test temperature without performing a pre-cooling process;
in response to determining that the current test item is a test item executable at the standard test temperature, determining whether a risk level of occurrence of a thermal fault in the current test item is greater than a risk level of occurrence of a thermal fault in a previous test item;
If the judgment result is yes, keeping the test temperature of the current test item consistent with the test temperature of the previous test item;
If the result of the determination is no, setting a test temperature of the current test item relative to a test temperature of the previous test item, wherein the set test temperature of the current test item is not higher than the standard test temperature, and wherein the setting comprises determining a warming magnitude of the test temperature of the current test item relative to the test temperature of the previous test item, wherein the warming magnitude is determined at least in part according to a degree of difference between risk levels of the current test item and the previous test item.
2. The method of claim 1, further comprising:
For each test item of the plurality of test items for which the pre-cooling treatment is required, setting a test temperature of the test item to a reduced temperature corresponding to a risk level of the test item.
3. The method of claim 1, further comprising:
And adjusting the execution sequence of the plurality of test items so that at least one test item requiring the pre-cooling treatment among the plurality of test items is executed immediately after another test item requiring the pre-cooling treatment, which is executed before, wherein the at least one test item does not have the execution of other test items between the another test item and the at least one test item as a precondition.
4. The method of claim 3, wherein the adjusting is performed in response to determining that an average test temperature of the plurality of test items is below a specified average test temperature threshold.
5. The method of claim 1, wherein if the statistical data related to the current test item performed according to the determined warming amplitude indicates that a thermal failure occurrence rate corresponding to the current test item does not satisfy a preset criterion, the warming amplitude is lowered for the current test item in the aging test of the next round.
6. The method of claim 1, wherein the risk level of occurrence of a thermal fault in each of the plurality of test items is determined based on historical statistics related to a plurality of rounds of the burn-in test that have been completed at the standard test temperature.
7. The method of claim 6, wherein the determining of the risk level comprises:
identifying a thermal fault indicated in the historical statistics;
determining a test item corresponding to each of the identified thermal faults;
Counting a thermal failure occurrence rate of each of the plurality of test items based on a result of the determining;
each of the plurality of test items is assigned one of a plurality of risk levels based on the counted occurrence of thermal faults.
8. A computing device, comprising:
at least one processor; and
A memory coupled to the at least one processor and configured to store instructions, wherein the instructions, when executed by the at least one processor, cause the at least one processor to:
for each of a plurality of test items included in the chip burn-in test, determining whether the current test item is a test item that can be executed at a prescribed standard test temperature without performing a pre-cooling process;
in response to determining that the current test item is a test item executable at the standard test temperature, determining whether a risk level of occurrence of a thermal fault in the current test item is greater than a risk level of occurrence of a thermal fault in a previous test item;
If the judgment result is yes, keeping the test temperature of the current test item consistent with the test temperature of the previous test item;
If the result of the determination is no, setting a test temperature of the current test item relative to a test temperature of the previous test item, wherein the set test temperature of the current test item is not higher than the standard test temperature, and wherein the setting comprises determining a warming magnitude of the test temperature of the current test item relative to the test temperature of the previous test item, wherein the warming magnitude is determined at least in part according to a degree of difference between risk levels of the current test item and the previous test item.
9. The computing device of claim 8, wherein the at least one processor is further configured to:
For each test item of the plurality of test items for which the pre-cooling treatment is required, setting a test temperature of the test item to a reduced temperature corresponding to a risk level of the test item.
10. The computing device of claim 8, wherein the at least one processor is further configured to:
And adjusting the execution sequence of the plurality of test items so that at least one test item requiring the pre-cooling treatment among the plurality of test items is executed immediately after another test item requiring the pre-cooling treatment, which is executed before, wherein the at least one test item does not have the execution of other test items between the another test item and the at least one test item as a precondition.
11. The computing device of claim 10, wherein the adjusting is performed in response to determining that an average test temperature of the plurality of test items is below a specified average test temperature threshold.
12. The computing device of claim 8, wherein, if the statistical data related to the current test item performed according to the determined warming amplitude indicates that a thermal failure occurrence rate corresponding to the current test item does not meet a preset criterion, the warming amplitude is reduced for the current test item in the next round of the burn-in test.
13. The computing device of claim 8, wherein a risk level for occurrence of a thermal fault in each of the plurality of test items is determined based on historical statistics related to a plurality of rounds of the burn-in testing that have been completed at the standard test temperature.
14. The computing device of claim 13, wherein the determination of the risk level comprises:
identifying a thermal fault indicated in the historical statistics;
determining a test item corresponding to each of the identified thermal faults;
Counting a thermal failure occurrence rate of each of the plurality of test items based on a result of the determining;
each of the plurality of test items is assigned one of a plurality of risk levels based on the counted occurrence of thermal faults.
15. A computer-readable storage medium having instructions stored thereon, which when executed by at least one processor, cause the at least one processor to perform the method of any of claims 1-7.
16. A computer program product comprising instructions which, when executed by at least one processor, cause the at least one processor to perform the method of any of claims 1-7.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008224493A (en) * | 2007-03-14 | 2008-09-25 | Fujitsu Ltd | Burn-in test method and burn-in system |
| CN103107086A (en) * | 2013-01-29 | 2013-05-15 | 淄博晨启电子有限公司 | Manufacturing technique of low-voltage chip and low-voltage chip thereof |
| CN204241639U (en) * | 2013-11-20 | 2015-04-01 | 宜硕科技(上海)有限公司 | The aging demo plant of high-power die |
| CN204807639U (en) * | 2015-06-09 | 2015-11-25 | 苏州韦德韦诺电气科技有限公司 | Simple and easy high temperature aging testing device |
| CN107894560A (en) * | 2017-11-29 | 2018-04-10 | 英特尔产品（成都）有限公司 | The chip test system and its method that oil-free air dosage reduces |
| CN108089101A (en) * | 2017-11-16 | 2018-05-29 | 云南电网有限责任公司电力科学研究院 | A kind of appraisal procedure of scene casing insulation ag(e)ing state |
| CN110399302A (en) * | 2019-07-26 | 2019-11-01 | 中国工商银行股份有限公司 | Risk Identification Method, device, electronic equipment and the medium of Software Testing Project |
| CN110716126A (en) * | 2019-10-14 | 2020-01-21 | 珠海亿智电子科技有限公司 | Chip aging test system, method and device |
| CN111722086A (en) * | 2020-06-29 | 2020-09-29 | 中国人民解放军国防科技大学 | High-power processor chip aging test method |
| CN112345873A (en) * | 2020-12-04 | 2021-02-09 | 苏州长光华芯光电技术股份有限公司 | Semiconductor laser low-temperature aging test device and low-temperature aging test method |
| CN112444718A (en) * | 2019-08-29 | 2021-03-05 | 上海原动力通信科技有限公司 | Chip aging monitoring method, device and system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7170310B2 (en) * | 2004-09-08 | 2007-01-30 | International Business Machines Corporation | System and method using locally heated island for integrated circuit testing |
| US10371745B2 (en) * | 2014-01-23 | 2019-08-06 | Micron Technology, Inc. | Overheat protection circuit and method in an accelerated aging test of an integrated circuit |
-
2021
- 2021-03-23 CN CN202110307577.7A patent/CN113156294B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008224493A (en) * | 2007-03-14 | 2008-09-25 | Fujitsu Ltd | Burn-in test method and burn-in system |
| CN103107086A (en) * | 2013-01-29 | 2013-05-15 | 淄博晨启电子有限公司 | Manufacturing technique of low-voltage chip and low-voltage chip thereof |
| CN204241639U (en) * | 2013-11-20 | 2015-04-01 | 宜硕科技(上海)有限公司 | The aging demo plant of high-power die |
| CN204807639U (en) * | 2015-06-09 | 2015-11-25 | 苏州韦德韦诺电气科技有限公司 | Simple and easy high temperature aging testing device |
| CN108089101A (en) * | 2017-11-16 | 2018-05-29 | 云南电网有限责任公司电力科学研究院 | A kind of appraisal procedure of scene casing insulation ag(e)ing state |
| CN107894560A (en) * | 2017-11-29 | 2018-04-10 | 英特尔产品（成都）有限公司 | The chip test system and its method that oil-free air dosage reduces |
| CN110399302A (en) * | 2019-07-26 | 2019-11-01 | 中国工商银行股份有限公司 | Risk Identification Method, device, electronic equipment and the medium of Software Testing Project |
| CN112444718A (en) * | 2019-08-29 | 2021-03-05 | 上海原动力通信科技有限公司 | Chip aging monitoring method, device and system |
| CN110716126A (en) * | 2019-10-14 | 2020-01-21 | 珠海亿智电子科技有限公司 | Chip aging test system, method and device |
| CN111722086A (en) * | 2020-06-29 | 2020-09-29 | 中国人民解放军国防科技大学 | High-power processor chip aging test method |
| CN112345873A (en) * | 2020-12-04 | 2021-02-09 | 苏州长光华芯光电技术股份有限公司 | Semiconductor laser low-temperature aging test device and low-temperature aging test method |
Non-Patent Citations (1)
| Title |
|---|
| 一种微处理器芯片的验证测试分析及应用;檀彦卓;韩银和;李晓维;;计算机工程;20060505(09);全文 * |
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|---|---|
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