CN113140631A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN113140631A CN113140631A CN202010046318.9A CN202010046318A CN113140631A CN 113140631 A CN113140631 A CN 113140631A CN 202010046318 A CN202010046318 A CN 202010046318A CN 113140631 A CN113140631 A CN 113140631A
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- 238000000034 method Methods 0.000 title claims abstract description 81
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 230000000903 blocking effect Effects 0.000 claims abstract description 137
- 238000005530 etching Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims description 49
- 230000000149 penetrating effect Effects 0.000 claims description 16
- 239000003989 dielectric material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 239000012530 fluid Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a forming method of a semiconductor device and the semiconductor device, the method comprises the following steps: providing a substrate; forming a first dielectric layer covering partial side wall of the grid structure on the substrate; and forming a barrier dielectric layer on the first dielectric layers of the first area and the second area, wherein the thickness of the barrier dielectric layer of the first area is greater than that of the barrier dielectric layer of the second area. And forming a first plug groove and a second plug groove which penetrate through the first dielectric layer and the blocking dielectric layer on the source-drain doped region of the first region. In the process of forming the first plug groove and the second plug groove by etching, as the blocking dielectric layer has a blocking effect and the etching rate of the blocking dielectric layer is less than that of the first dielectric layer, the etching rate of the first plug groove relative to the second plug groove can be reduced, the problem of over-fast etching when the first plug groove is formed in the first region is avoided, and finally the source-drain doped region of the first region is not damaged.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for forming a semiconductor device and a semiconductor device.
Background
In order to comply with the development of morgan's law and satisfy the requirements of people for smaller size, smaller occupied space, and more convenient carrying and operation of various electronic products, semiconductor manufacturing technologies are rapidly developing with the goal of high integration, low power consumption, and high performance. Currently, as the semiconductor industry advances to process nodes of 10nm and below, the fabrication of semiconductor devices is limited by various physical limitations.
In order to continuously improve the driving capability of current to the transistor circuit and further suppress the short channel effect, semiconductor devices have been developed from planar semiconductor devices to three-dimensional semiconductor devices such as fin field effect transistors (finfets). Finfets are advanced semiconductor devices for process nodes of 20nm and below, compared to planar semiconductor devices. Because the three-dimensional structure of the FinFET can effectively increase the actual distance between the source electrode and the grid electrode as well as between the grid electrode and the drain electrode, the FinFET can effectively shorten the channel effect, and can also effectively improve the density of the semiconductor device formed on the substrate.
While finfets have lower voltages and smaller device volumes, the challenges facing finfets are increasing as the device sizes continue to shrink. For example, when a plug groove is formed by etching a dielectric layer between gate structures, since the etching rates of the dielectric layers in regions with different distances between the gate structures are different, and the etching rate of the dielectric layer of a first region with a smaller distance between the gate structures is usually greater than the etching rate of the dielectric layer of a second region with a larger distance between the gate structures, a source-drain doped region of the first region may be damaged during the formation of the plug groove.
Disclosure of Invention
The invention aims to solve the problem that in the prior art, a source-drain doped region of a first region is damaged in the forming process of a plug groove. The invention provides a method for forming a semiconductor device, which can prevent a source-drain doped region of a first region from being damaged in the forming process of a plug groove.
In order to solve the above technical problem, an embodiment of the present invention discloses a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a first region and a second region, the substrate is provided with gate structures, the distance between the gate structures of the first region is smaller than that between the gate structures of the second region, and the substrate on two sides of the gate structures is respectively provided with a source-drain doped region;
forming a first dielectric layer covering partial side wall of the grid structure on the substrate, wherein the top surface of the first dielectric layer is lower than that of the grid structure;
forming a blocking dielectric layer on the first dielectric layers of the first area and the second area, wherein the thickness of the blocking dielectric layer of the first area is larger than that of the blocking dielectric layer of the second area;
and forming a first plug groove penetrating through the first dielectric layer and the blocking dielectric layer on the source-drain doped region of the first region, and forming a second plug groove penetrating through the first dielectric layer and the blocking dielectric layer on the source-drain doped region of the second region in the process of forming the first plug groove.
Preferably, the method for forming the first dielectric layer includes: forming a first initial dielectric layer covering the whole side wall of the grid structure on the substrate; and etching back the first initial dielectric layer to form the first initial dielectric layer.
Preferably, the blocking dielectric layer of the second region has a dielectric recess therein, and in a direction perpendicular to the top surface of the gate structure, the thickness of the blocking dielectric at the bottom of the dielectric recess is smaller than that of the blocking dielectric layer of the first region;
the method for forming the semiconductor device further comprises the following steps: filling a second dielectric layer in the dielectric recess before forming the first plug groove and the second plug groove; after the second plug groove is formed, the second plug groove also penetrates through the second dielectric layer.
Preferably, the method for forming the blocking dielectric layer and the second dielectric layer includes: forming a blocking material layer on the side wall and the top of the grid structure of the first area, the surface of the first dielectric layer of the first area, the side wall and the top of the grid structure of the second area and the surface of the first dielectric layer of the second area, wherein a first recess on the first dielectric layer is formed in the blocking material layer of the first area, a second recess on the first dielectric layer is formed in the blocking material layer of the second area, and the thickness of the blocking material layer at the bottom of the first recess is larger than that of the blocking material layer of the second recess; forming a second dielectric material layer in the first recess and the second recess and on the barrier material layer; and flattening the second dielectric material layer and the blocking material layer until the top surface of the grid structure is exposed, so that the blocking material layer forms the blocking dielectric layer, the second dielectric material layer forms the second dielectric layer, and the second recess forms a dielectric recess in the blocking dielectric layer.
Preferably, the forming process of the barrier material layer comprises an atomic layer deposition process; the forming process of the second dielectric material layer comprises a fluid chemical vapor deposition process or a plasma chemical vapor deposition process.
Preferably, in a direction perpendicular to the top surface of the gate structure, a ratio of a thickness of the blocking dielectric at the bottom of the dielectric recess to a thickness of the blocking dielectric layer of the first region is 1.4 to 2.2.
Preferably, the material of the second dielectric layer includes: silicon oxide.
Preferably, the process for forming the first plug groove and the second plug groove is an etching process; and in the process of forming the first plug groove and the second plug groove, the etching rate of the second dielectric layer is greater than that of the barrier dielectric layer.
Preferably, in the process of forming the first plug groove and the second plug groove, the etching rate of the blocking dielectric layer is less than that of the first dielectric layer; the ratio of the etching rate of the barrier dielectric layer to the etching rate of the first dielectric layer is 10 to 100.
Preferably, the material of the first dielectric layer includes: silicon oxide; the material of the blocking dielectric layer comprises silicon nitride.
Preferably, a dimension of the first plug groove in the channel length direction of the first region is smaller than a dimension of the second plug groove in the channel length direction of the second region.
Preferably, the channel length of the bottom of the gate structure of the first region is smaller than the channel length of the bottom of the gate structure of the second region.
Preferably, the method further comprises the following steps: after the blocking dielectric layer is formed and before the first plug groove and the second plug groove are formed, removing the grid structure, and forming a grid opening in the first dielectric layer and the blocking dielectric layer; and forming metal gate structures in the gate openings, wherein the distance between the metal gate structures in the first region is smaller than that between the metal gate structures in the second region.
An embodiment of the present invention also discloses a semiconductor device, including:
a substrate comprising a first region and a second region;
the target gate structures are positioned on the substrate, and the distance between the target gate structures in the first area is smaller than that between the target gate structures in the second area;
source and drain doped regions respectively located in the substrate at both sides of the target gate structure;
a first dielectric layer on the substrate covering a portion of the sidewall of the target gate structure, a top surface of the first dielectric layer being lower than a top surface of the target gate structure;
the blocking dielectric layers are positioned on the first dielectric layers of the first area and the second area, and the thickness of the blocking dielectric layer of the first area is larger than that of the blocking dielectric layer of the second area;
the first plug groove is positioned on the source-drain doped region of the first region and penetrates through the first dielectric layer and the blocking dielectric layer;
and the second plug groove is positioned on the source-drain doped region of the second region and penetrates through the first dielectric layer and the blocking dielectric layer.
Preferably, the blocking dielectric layer of the second region has a dielectric recess therein, and in a direction perpendicular to the top surface of the target gate structure, the thickness of the blocking dielectric at the bottom of the dielectric recess is smaller than that of the blocking dielectric layer of the first region; the semiconductor device further includes: a second dielectric layer located in the dielectric recess; the second plug groove also penetrates through the second medium layer.
Preferably, the material of the second dielectric layer includes: silicon oxide; the material of the first dielectric layer comprises: silicon oxide; the material of the blocking dielectric layer comprises silicon nitride.
Preferably, a dimension of the first plug groove in the channel length direction of the first region is smaller than a dimension of the second plug groove in the channel length direction of the second region.
Preferably, the channel length of the bottom of the target gate structure of the first region is smaller than the channel length of the bottom of the target gate structure of the second region.
Preferably, the method further comprises the following steps: a first plug located in the first plug slot; a second plug located in the second plug groove.
Preferably, the base comprises a semiconductor substrate and a fin portion located on the semiconductor substrate; the target gate structure spans across the fin.
The invention has the beneficial effects that:
the method for forming the semiconductor device comprises the steps of firstly forming a blocking dielectric layer on the first dielectric layer of the first area and the second dielectric layer of the second area, forming a first plug groove penetrating through the first dielectric layer and the blocking dielectric layer on the source-drain doped area of the first area, and forming a second plug groove penetrating through the first dielectric layer and the blocking dielectric layer on the source-drain doped area of the second area, wherein the thickness of the blocking dielectric layer of the first area is larger than that of the blocking dielectric layer of the second area. In the process of forming the first plug groove and the second plug groove by etching, as the blocking dielectric layer has a blocking effect and the etching rate of the blocking dielectric layer is less than that of the first dielectric layer, the etching rate of the first plug groove relative to the second plug groove can be reduced, the problem of over-fast etching when the first plug groove is formed in the first region is avoided, and finally, the source-drain doped region of the first region is not over-etched, so that the damage to the source-drain doped region is avoided.
Drawings
Fig. 1 is a flow chart of a method of forming a semiconductor device provided by an embodiment of the invention;
fig. 2 to 10 are schematic structural diagrams corresponding to a method for forming a semiconductor device according to an embodiment of the present invention.
Reference numerals:
1. a substrate; 11. a first region; 12. a second region; 2. a gate structure; 21. a metal gate structure; 22. etching the barrier layer; 23. masking; 3. a source drain doped region; 4. a first dielectric layer; 41. a first initial dielectric layer; 5. a blocking dielectric layer; 51. medium recess; 52. a layer of barrier material; 6. a second dielectric layer; 61. a second dielectric material layer; 7. a first plug groove; 8. a second plug groove; 9. and a side wall.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure. While the invention will be described in conjunction with the preferred embodiments, it is not intended that features of the invention be limited to these embodiments. On the contrary, the invention is described in connection with the embodiments for the purpose of covering alternatives or modifications that may be extended based on the claims of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The invention may be practiced without these particulars. Moreover, some of the specific details have been left out of the description in order to avoid obscuring or obscuring the focus of the present invention. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
It should be noted that in this specification, like reference numerals and letters refer to like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.
In the description of the present embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that are conventionally placed when the products of the present invention are used, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements indicated must have specific orientations, be configured in specific orientations, and operate, and thus, should not be construed as limiting the present invention.
The terms "first," "second," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present embodiment, it should be further noted that, unless explicitly stated or limited otherwise, the terms "disposed," "connected," and "connected" are to be interpreted broadly, e.g., as a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present embodiment can be understood in specific cases by those of ordinary skill in the art.
In order to solve the problem that in the prior art, due to the fact that etching rates of dielectric layers in regions with different distances between gate structures are different, the dielectric layers in the regions with smaller distances between the gate structures are over-etched, or the dielectric layers in the regions with larger distances between the gate structures are under-etched, the invention provides a method for forming a semiconductor device, and specifically, as shown in a flow chart of a method for forming a semiconductor device provided by an embodiment of the invention shown in fig. 1, the method for forming a semiconductor device provided by the embodiment of the invention specifically comprises the following steps:
step S1: providing a substrate, wherein the substrate comprises a first area and a second area, the substrate is provided with gate structures, the distance between the gate structures of the first area is smaller than that between the gate structures of the second area, and the substrate at two sides of the gate structures is respectively provided with a source-drain doped area.
Step S2: and forming a first dielectric layer covering part of the side wall of the gate structure on the substrate, wherein the top surface of the first dielectric layer is lower than that of the gate structure.
Step S3: and forming a barrier dielectric layer on the first dielectric layers of the first area and the second area, wherein the thickness of the barrier dielectric layer of the first area is greater than that of the barrier dielectric layer of the second area.
Step S4: and forming a first plug groove penetrating through the first dielectric layer and the blocking dielectric layer on the source-drain doped region of the first region, and forming a second plug groove penetrating through the first dielectric layer and the blocking dielectric layer on the source-drain doped region of the second region in the process of forming the first plug groove.
The method can prevent the problem that the dielectric layer in the region with small space between the grid structures is over-etched or the dielectric layer in the region with large space between the grid structures is under-etched due to the fact that the etching rates of the dielectric layers in the regions with different space between the grid structures are different. Specifically, in the method for forming a semiconductor device provided in this embodiment, a blocking dielectric layer is first formed on the first dielectric layer of the first region and the second region, and the thickness of the blocking dielectric layer of the first region is greater than that of the blocking dielectric layer of the second region, then a first plug groove penetrating through the first dielectric layer and the blocking dielectric layer is formed on the source-drain doped region of the first region, and a second plug groove penetrating through the first dielectric layer and the blocking dielectric layer is formed on the source-drain doped region of the second region. In the process of forming the first plug groove and the second plug groove by etching, as the blocking dielectric layer has a blocking effect and the etching rate of the blocking dielectric layer is less than that of the first dielectric layer, the etching rate of the first plug groove relative to the second plug groove can be reduced, the problem of over-fast etching when the first plug groove is formed in the first region is avoided, and finally, the source-drain doped region of the first region is not over-etched, so that the damage to the source-drain doped region is avoided.
A method of forming the semiconductor device is specifically described below with reference to fig. 1 to 10. Fig. 2 to 10 are schematic structural diagrams corresponding to a method for forming a semiconductor device according to an embodiment of the present invention.
Firstly, as shown in fig. 1 and 4, a substrate 1 is provided, the substrate 1 includes a first region 11 and a second region 12, the substrate 1 has gate structures 2, a distance between the gate structures 2 of the first region 11 is smaller than a distance between the gate structures 2 of the second region 12, and the substrate 1 on both sides of the gate structures 2 has source and drain doped regions 3 respectively.
With continued reference to fig. 4, a first dielectric layer 4 is formed on the substrate 1 covering a portion of the sidewalls of the gate structure 2, and a top surface of the first dielectric layer 4 is lower than a top surface of the gate structure 2.
It should be noted that, in this embodiment, a side wall is formed on the side wall of the gate structure, and an etching barrier layer is formed on the surface of the side wall; and before the first dielectric layer is formed, a mask is also formed on the top of the gate structure.
The following description will take the example of forming a sidewall spacer and an etch stop layer on the sidewall of the gate structure, and forming a mask on the top of the gate structure.
Specifically, the specific process of forming the structure shown in fig. 4 in this embodiment is shown in fig. 2-4.
More specifically, in this embodiment, the forming the first dielectric layer 4 includes:
first, as shown in fig. 2, a mask 23 is formed on the top of the gate structure 2, a sidewall 9 is formed covering the sidewall of the gate structure 2 and a portion of the sidewall of the mask 23, and an etch stop layer 22 is formed covering the sidewall 9 and the sidewall and the top of the mask 23. It should be noted that in this embodiment, the etch stop layer 22 is also formed on the surface of the source/drain doped region 3.
Forming a first initial dielectric layer 41 covering the entire sidewall of the gate structure 2 on the substrate 1, specifically forming the first initial dielectric layer 41 with the top not lower than the top of the etching stop layer 22, and then performing a chemical mechanical polishing process on the first initial dielectric layer 41.
Then, as shown in fig. 3, the first initial dielectric layer 41, the etch stop layer 22 and the mask 23 are chemically and mechanically polished until the tops of the first initial dielectric layer 41, the etch stop layer 22 and the mask 23 are flush with the tops of the sidewalls 9.
Next, as shown in fig. 4, the first initial dielectric layer 41 is etched back, so that the first initial dielectric 41 layer forms the first dielectric layer 4. Specifically, in the back etching process, the mask 23 is removed, the etching barrier layer 22 and the sidewall spacer 9 are etched to be flush, and the top surfaces of the finally formed etching barrier layer 22 and the sidewall spacer 9 are lower than the top surface of the gate structure 2 and higher than the top surface of the first dielectric layer 4.
Specifically, the material of the substrate 1 in this embodiment includes, but is not limited to, monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium-silicon material, carbon-silicon material, and the like, which is not specifically limited in this embodiment.
The base 1 in this embodiment includes a semiconductor substrate and a fin portion on the semiconductor substrate. Other semiconductor structures such as an isolation structure may also be formed on the substrate 1, which is not specifically limited in this embodiment.
The first region 11 in this embodiment is a region in the left half of fig. 4, in which the spacing between the gate structures 2 is small; the second region 12 in this embodiment is a region on the right half of fig. 4, in which the distance between the gate structures 2 is larger.
In this embodiment, the channel length of the bottom of the gate structure 2 in the first region 11 is smaller than the channel length of the bottom of the gate structure 2 in the second region 12. In other embodiments of the present embodiment, the channel length at the bottom of the gate structure 2 in the first region 11 and the channel length at the bottom of the gate structure 2 in the second region 12 may also be the same.
Next, as shown in fig. 7, a barrier dielectric layer 5 is formed on the first dielectric layer 4 of the first region 11 and the second region 12, and the thickness of the barrier dielectric layer 5 of the first region 11 is greater than that of the barrier dielectric layer 5 of the second region 12.
The specific process for forming the structure shown in fig. 7 in this embodiment is shown in fig. 5-7.
In this embodiment, a dielectric recess 51 is formed in the blocking dielectric layer 5 of the second region 12, and a second dielectric layer 6 is further formed in the dielectric recess 51.
The method for forming the barrier dielectric layer 5 and the second dielectric layer 6 comprises the following steps: firstly, as shown in fig. 5, a blocking material layer 52 is formed on the sidewall and the top of the gate structure 2 in the first region 11, the surface of the first dielectric layer 4 in the first region 11, the sidewall and the top of the gate structure 2 in the second region 12, and the surface of the first dielectric layer 4 in the second region 12, a first recess located on the first dielectric layer 4 is formed in the blocking material layer 52 in the first region 11, a second recess located on the first dielectric layer 4 is formed in the blocking material layer 52 in the second region 12, and the thickness of the blocking material layer 52 at the bottom of the first recess is greater than that of the blocking material layer 52 in the second recess; forming a second dielectric material layer 61 in the first and second recesses and on the barrier material layer 52; then, as shown in fig. 6, a chemical mechanical polishing process is performed on the second dielectric material layer 61. Then, as shown in fig. 7, the second dielectric material layer 61 and the blocking material layer 52 are planarized until the top surface of the gate structure 2 is exposed, so that the blocking material layer 52 forms a blocking dielectric layer, the second dielectric material layer 61 forms a second dielectric layer 6, and the second recess forms a dielectric recess 51 in the blocking dielectric layer 5.
It should be noted that the medium recess 51 is shown by a dashed line in fig. 7 and represents an actual medium recess 51, which only represents the medium recess 51 providing a space for the second medium layer 6, and the size and shape of the medium recess can be determined according to actual needs.
Preferably, in this embodiment, the material of the first dielectric layer 4 includes silicon oxide, and the material of the blocking dielectric layer 5 includes silicon nitride. In addition, in this embodiment, the material of the first dielectric layer 4 may further include silicon oxycarbide, silicon oxynitride, and the like, which may be specifically selected according to the needs.
It should be noted that, in this embodiment, as shown in fig. 7, the blocking dielectric layer 5 in the second region 12 has a dielectric recess 51, and in a direction perpendicular to the top surface of the gate structure 2, the thickness of the blocking dielectric layer 5 at the bottom of the dielectric recess 51 is smaller than the thickness of the blocking dielectric layer 5 in the first region 11.
It should be noted that in this embodiment, only the dielectric recess 51 is formed in the second region 12, and the blocking dielectric layer 5 in the first region 11 does not form the dielectric recess. However, this is only a schematic representation of this embodiment, and a person skilled in the art may choose to form a dielectric recess in the blocking dielectric layer in the first region, and also form a dielectric recess in the blocking dielectric layer in the second region, where the thickness of the blocking dielectric layer at the bottom of the dielectric recess in the first region is smaller than that at the bottom of the dielectric recess in the second region.
Preferably, the ratio of the thickness of the blocking dielectric at the bottom of the dielectric recess 51 to the thickness of the blocking dielectric layer 5 of the first region 11 in a direction perpendicular to the top surface of the gate structure 2 is 1.4 to 2.2. Specifically, the thickness of the blocking dielectric at the bottom of the dielectric recess 51 is about 700 angstroms, and the thickness of the blocking dielectric layer 5 in the first region 11 is 1000 angstroms to 1500 angstroms.
Further, the material of the second dielectric layer 6 includes at least one of silicon oxide, silicon oxynitride, and silicon oxycarbide, which can be specifically selected according to the requirement.
Preferably, in the present embodiment, the forming process of the barrier material layer 52 includes an atomic layer deposition process; the forming process of the second dielectric layer 6 includes a fluid chemical vapor deposition process or a plasma chemical vapor deposition process.
Finally, as shown in fig. 10, a first plug groove 7 penetrating through the first dielectric layer 4 and the blocking dielectric layer is formed on the source-drain doped region 3 of the first region 11, and in the process of forming the first plug groove 7, a second plug groove 8 penetrating through the first dielectric layer 4 and the blocking dielectric layer is formed on the source-drain doped region 3 of the second region 12.
After the formation of the blocking dielectric layer 5 and before the formation of the first plug groove 7 and the second plug groove 8, as shown in fig. 8, removing the gate structure 2 and forming a gate opening in the first dielectric layer 4 and the blocking dielectric layer; and then as shown in fig. 9. Metal gate structures 21 are formed in the gate openings, and the spacing between the metal gate structures 21 of the first region 11 is smaller than the spacing between the metal gate structures 21 of the second region 12. Referring next to fig. 10, the first plug groove 7 and the second plug groove 8 are formed by etching.
And the dimension of the first plug groove 7 in the channel length direction of the first region 11 is smaller than the dimension of the second plug groove 8 in the channel length direction of the second region 12.
Preferably, the process of forming the first plug groove 7 and the second plug groove 8 is an etching process; in the process of forming the first plug groove 7 and the second plug groove 8, the etching rate of the second dielectric layer 6 is greater than that of the barrier dielectric layer.
In the process of forming the first plug groove 7 and the second plug groove 8, the etching rate of the barrier dielectric layer is less than that of the first dielectric layer 4; the ratio of the etching rate of the blocking dielectric layer to the etching rate of the first dielectric layer 4 is 10 to 100, and may be 10 to 50, such as 10, 20, 30, 40, 50, etc., or may be 50 to 100, such as 60, 70, 80, 90, 100, or other values, which is not limited in this embodiment.
Note that, as shown in fig. 7, in the present embodiment, before forming the first plug groove 7 and the second plug groove 8, the dielectric recess 51 is filled with the second dielectric layer 6; after the second plug groove 8 is formed, the second plug groove 8 also penetrates the second dielectric layer 6.
According to the scheme, the blocking dielectric layer is formed on the first dielectric layer of the first area and the second dielectric layer of the second area, the thickness of the blocking dielectric layer of the first area is larger than that of the blocking dielectric layer of the second area, then a first plug groove penetrating through the first dielectric layer and the blocking dielectric layer is formed on the source-drain doped area of the first area, and a second plug groove penetrating through the first dielectric layer and the blocking dielectric layer is formed on the source-drain doped area of the second area. In the process of forming the first plug groove and the second plug groove by etching, as the blocking dielectric layer has a blocking effect and the etching rate of the blocking dielectric layer is less than that of the first dielectric layer, the etching rate of the first plug groove relative to the second plug groove can be reduced, the problem of over-fast etching when the first plug groove is formed in the first region is avoided, and finally, the source-drain doped region of the first region is not over-etched, so that the damage to the source-drain doped region is avoided.
Based on the above method for forming a semiconductor device, this embodiment further provides a semiconductor device, and specifically, as shown in fig. 10, the semiconductor device provided in this embodiment specifically includes:
a substrate 1, the substrate 1 comprising a first region 11 and a second region 12;
target gate structures located on the substrate 1, wherein the distance between the target gate structures of the first region 11 is smaller than the distance between the target gate structures of the second region 12;
source-drain doped regions 3 respectively located in the substrate 1 at both sides of the target gate structure;
the first dielectric layer 4 is positioned on the substrate 1 and covers part of the side wall of the target gate structure, and the top surface of the first dielectric layer 4 is lower than that of the target gate structure;
the barrier dielectric layer is positioned on the first dielectric layer 4 of the first area 11 and the second area 12, and the thickness of the barrier dielectric layer of the first area 11 is larger than that of the barrier dielectric layer of the second area 12;
the first plug groove 7 is positioned on the source-drain doped region 3 of the first region 11 and penetrates through the first dielectric layer 4 and the blocking dielectric layer;
and the second plug groove 8 is positioned on the source-drain doped region 3 of the second region 12 and penetrates through the first dielectric layer 4 and the blocking dielectric layer.
The first region 11 is a region of the left half shown in fig. 10 in which the pitch between the target gate structures is small; the second region 12 is a region on the right half shown in fig. 10 in which the pitch between the target gate structures is large.
In this embodiment, the target gate structure may be a dummy gate or a metal gate structure, which is not specifically limited in this embodiment.
It should be noted that, in this embodiment, the blocking dielectric layer in the second region 12 has a dielectric recess 51, and in a direction perpendicular to the top surface of the target gate structure, the thickness of the blocking dielectric at the bottom of the dielectric recess 51 is smaller than the thickness of the blocking dielectric layer in the first region 11; the semiconductor device of (1) further comprising: a second dielectric layer 6 located in the dielectric recess 51; the second plug groove 8 also extends through the second dielectric layer 6.
Preferably, the material of the second dielectric layer 6 includes: an oxide layer; the material of the first dielectric layer 4 includes: silicon oxide; the material of the blocking dielectric layer comprises silicon nitride.
It should be further noted that the dimension of the first plug groove 7 in the channel length direction of the first region 11 is smaller than the dimension of the second plug groove 8 in the channel length direction of the second region 12; the channel length at the bottom of the gate structure of the first region 11 is smaller than the channel length at the bottom of the gate structure of the second region 12.
In this embodiment, the semiconductor device further includes: a first plug located in the first plug groove 7; a second plug located in the second plug groove 8.
Preferably, in this embodiment, the base 1 includes a semiconductor substrate and a fin portion located on the semiconductor substrate; the target gate structure crosses over the fin.
Specifically, the material of the semiconductor substrate includes, but is not limited to, monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium-silicon material, carbon-silicon material, and the like, which is not specifically limited in this embodiment.
According to the semiconductor device formed by the scheme, the blocking dielectric layer is formed on the first dielectric layer of the first area and the second dielectric layer of the second area, the thickness of the blocking dielectric layer of the first area is larger than that of the blocking dielectric layer of the second area, then the first plug groove penetrating through the first dielectric layer and the blocking dielectric layer is formed on the source-drain doped area of the first area, and the second plug groove penetrating through the first dielectric layer and the blocking dielectric layer is formed on the source-drain doped area of the second area. In the process of forming the first plug groove and the second plug groove by etching, as the blocking dielectric layer has a blocking effect and the etching rate of the blocking dielectric layer is less than that of the first dielectric layer, the etching rate of the first plug groove relative to the second plug groove can be reduced, the problem of over-fast etching when the first plug groove is formed in the first region is avoided, and finally, the source-drain doped region of the first region is not over-etched, so that the damage to the source-drain doped region is avoided.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing is a more detailed description of the invention, taken in conjunction with the specific embodiments thereof, and that no limitation of the invention is intended thereby. Various changes in form and detail, including simple deductions or substitutions, may be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (20)
1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region, the substrate is provided with gate structures, the distance between the gate structures of the first region is smaller than that between the gate structures of the second region, and source and drain doped regions are respectively arranged in the substrate at two sides of the gate structures;
forming a first dielectric layer covering partial side wall of the grid structure on the substrate, wherein the top surface of the first dielectric layer is lower than that of the grid structure;
forming a blocking dielectric layer on the first dielectric layers of the first area and the second area, wherein the thickness of the blocking dielectric layer of the first area is larger than that of the blocking dielectric layer of the second area;
and forming a first plug groove penetrating through the first dielectric layer and the blocking dielectric layer on the source-drain doped region of the first region, and forming a second plug groove penetrating through the first dielectric layer and the blocking dielectric layer on the source-drain doped region of the second region in the process of forming the first plug groove.
2. The method of forming a semiconductor device of claim 1, wherein forming the first dielectric layer comprises: forming a first initial dielectric layer covering the whole side wall of the grid structure on the substrate; and etching back the first initial dielectric layer to form the first initial dielectric layer.
3. The method for forming a semiconductor device according to claim 1, wherein the blocking dielectric layer in the second region has a dielectric recess therein, and a thickness of the blocking dielectric layer at a bottom of the dielectric recess is smaller than a thickness of the blocking dielectric layer in the first region in a direction perpendicular to a top surface of the gate structure;
the method for forming the semiconductor device further comprises the following steps: filling a second dielectric layer in the dielectric recess before forming the first plug groove and the second plug groove; after the second plug groove is formed, the second plug groove also penetrates through the second dielectric layer.
4. The method of forming a semiconductor device of claim 3, wherein the method of forming the blocking dielectric layer and the second dielectric layer comprises: forming a blocking material layer on the side wall and the top of the grid structure of the first area, the surface of the first dielectric layer of the first area, the side wall and the top of the grid structure of the second area and the surface of the first dielectric layer of the second area, wherein a first recess on the first dielectric layer is formed in the blocking material layer of the first area, a second recess on the first dielectric layer is formed in the blocking material layer of the second area, and the thickness of the blocking material layer at the bottom of the first recess is larger than that of the blocking material layer of the second recess; forming a second dielectric material layer in the first recess and the second recess and on the barrier material layer; and flattening the second dielectric material layer and the blocking material layer until the top surface of the grid structure is exposed, so that the blocking material layer forms the blocking dielectric layer, the second dielectric material layer forms the second dielectric layer, and the second recess forms a dielectric recess in the blocking dielectric layer.
5. The method for forming a semiconductor device according to claim 4, wherein a process for forming the barrier material layer includes an atomic layer deposition process; the forming process of the second dielectric material layer comprises a fluid chemical vapor deposition process or a plasma chemical vapor deposition process.
6. The method of forming a semiconductor device according to claim 3, wherein a ratio of a thickness of the blocking dielectric at the bottom of the dielectric recess to a thickness of the blocking dielectric layer of the first region in a direction perpendicular to the top surface of the gate structure is 1.4 to 2.2.
7. The method of forming a semiconductor device according to claim 3, wherein a material of the second dielectric layer comprises silicon oxide.
8. The method for forming a semiconductor device according to claim 3, wherein a process of forming the first plug groove and the second plug groove is an etching process; and in the process of forming the first plug groove and the second plug groove, the etching rate of the second dielectric layer is greater than that of the barrier dielectric layer.
9. The method for forming a semiconductor device according to claim 1, wherein an etching rate of the barrier dielectric layer is smaller than an etching rate of the first dielectric layer in forming the first plug groove and the second plug groove; the ratio of the etching rate of the barrier dielectric layer to the etching rate of the first dielectric layer is 10 to 100.
10. The method for forming a semiconductor device according to claim 1, wherein a material of the first dielectric layer comprises silicon oxide; the material of the blocking dielectric layer comprises silicon nitride.
11. The method for forming a semiconductor device according to claim 1, wherein a dimension of the first plug groove in a channel length direction of the first region is smaller than a dimension of the second plug groove in a channel length direction of the second region.
12. The method for forming a semiconductor device according to claim 1, wherein a channel length of a bottom portion of the gate structure of the first region is smaller than a channel length of a bottom portion of the gate structure of the second region.
13. The method for forming a semiconductor device according to claim 1, further comprising: after the blocking dielectric layer is formed and before the first plug groove and the second plug groove are formed, removing the grid structure, and forming a grid opening in the first dielectric layer and the blocking dielectric layer; and forming metal gate structures in the gate openings, wherein the distance between the metal gate structures in the first region is smaller than that between the metal gate structures in the second region.
14. A semiconductor device, comprising:
a substrate comprising a first region and a second region;
the target gate structures are positioned on the substrate, and the distance between the target gate structures in the first area is smaller than that between the target gate structures in the second area;
source and drain doped regions respectively located in the substrate at both sides of the target gate structure;
a first dielectric layer on the substrate covering a portion of the sidewall of the target gate structure, a top surface of the first dielectric layer being lower than a top surface of the target gate structure;
the blocking dielectric layers are positioned on the first dielectric layers of the first area and the second area, and the thickness of the blocking dielectric layer of the first area is larger than that of the blocking dielectric layer of the second area;
the first plug groove is positioned on the source-drain doped region of the first region and penetrates through the first dielectric layer and the blocking dielectric layer;
and the second plug groove is positioned on the source-drain doped region of the second region and penetrates through the first dielectric layer and the blocking dielectric layer.
15. The semiconductor device of claim 14, wherein the blocking dielectric layer of the second region has a dielectric recess therein, and a thickness of the blocking dielectric at a bottom of the dielectric recess is less than a thickness of the blocking dielectric layer of the first region in a direction perpendicular to the top surface of the target gate structure; the semiconductor device further includes: a second dielectric layer located in the dielectric recess; the second plug groove also penetrates through the second medium layer.
16. The semiconductor device of claim 14, wherein a material of the second dielectric layer comprises silicon oxide; the material of the first dielectric layer comprises silicon oxide; the material of the blocking dielectric layer comprises silicon nitride.
17. The semiconductor device according to claim 14, wherein a dimension of the first plug groove in a channel length direction of the first region is smaller than a dimension of the second plug groove in a channel length direction of the second region.
18. The semiconductor device of claim 14, wherein a channel length at a bottom of the target gate structure of the first region is less than a channel length at a bottom of the target gate structure of the second region.
19. The semiconductor device according to claim 14, further comprising: a first plug located in the first plug slot; a second plug located in the second plug groove.
20. The semiconductor device of claim 14, wherein the base comprises a semiconductor substrate and a fin on the semiconductor substrate; the target gate structure spans across the fin.
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