CN113131934B - Comparator offset voltage calibration method applied to 16-bit low-power-consumption successive approximation type analog-to-digital converter - Google Patents
Comparator offset voltage calibration method applied to 16-bit low-power-consumption successive approximation type analog-to-digital converter Download PDFInfo
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Abstract
The invention discloses a comparator offset voltage calibration method applied to a 16-bit low-power-consumption successive approximation type analog-to-digital converter, which utilizes the structural characteristics of a three-section capacitor DAC array of the 16-bit low-power-consumption successive approximation type analog-to-digital converter, wherein the three-section capacitor DAC array is divided into a high section, a middle section and a low section, wherein partial capacitors Cd2 and Cd3 of the middle section and the low section are directly connected to a fixed level in the traditional conversion process, so that the offset voltage of the comparator can be calibrated by utilizing the capacitors. The capacitor DAC array switch switching algorithm adopted by the 16-bit low-power-consumption successive approximation type analog-to-digital converter is a Vcm-based switch algorithm. In the process of calibrating the offset voltage of the comparator, the capacitors Cd2 and Cd3 are shifted according to a certain sequence until the output of the comparator changes. The method effectively reduces the offset voltage of the comparator and improves the spurious-free dynamic range of the 16-bit low-power-consumption successive approximation type analog-to-digital converter.
Description
Technical Field
The invention relates to the technical field of comparator offset voltage calibration in a high-precision successive approximation type analog-to-digital converter structure, in particular to a comparator offset voltage calibration method applied to a 16-bit low-power-consumption successive approximation type analog-to-digital converter.
Background
With the continuous progress of semiconductor technology, the good process reduction and efficiency of Successive Approximation Analog-to-Digital Converter (SAR ADC) are continuously highlighted, and the research on the SAR ADC with high precision, high speed and low power consumption is increasingly deep. Fig. 1 is a block diagram of a general SAR ADC, wherein key modules mainly include a comparator, a sampling switch, a Digital-to-Analog Converter (DAC) and a Digital control logic. The core principle of the SAR ADC is the binary search method. Under the control of time sequence, the SAR ADC firstly samples input signals, then quantizes the sampled signals, and the specific process is that the lower plate switch of the capacitor DAC array arranged in binary system is successively shifted according to each comparison result of the comparator, so that the lower plate switch is connected to correct level, and the level change of the upper plate of the capacitor array is continuously close to the input signals. For the SAR ADC which seeks higher accuracy, the non-ideal factors have a great influence on the accuracy of the SAR ADC, and the offset voltage of the comparator is just one of them. Therefore, in a high-precision SAR ADC, calibration of the offset voltage of the comparator is necessary.
At present, the calibration method of the offset voltage of the comparator mainly includes an input offset voltage storage technology and an output offset voltage storage technology. Fig. 2-4 are schematic diagrams of the structures of the input offset voltage storage technique and the output offset voltage storage technique. The input offset voltage storage technology cannot be applied to the SAR ADC with a capacitor DAC array because a capacitor needs to be introduced into the input end of the comparator; in the output offset voltage storage technology, a capacitor needs to be introduced into the output end of the comparator, for the comparator which pursues the high-precision SAR ADC, the output of the comparator can be saturated due to the large gain of the comparator, the offset voltage elimination effect is influenced, and meanwhile, the introduction of the capacitor can generate substantial influence on the gain and the bandwidth of the comparator.
Disclosure of Invention
In view of this, the present invention provides a method for calibrating offset voltage of a comparator applied to a 16-bit successive approximation type analog-to-digital converter with low power consumption, which can achieve the effect of eliminating the offset voltage of the comparator without introducing an additional device to the comparator or the capacitor DAC array of the SAR ADC.
In order to achieve the purpose, the invention adopts the technical scheme that:
a method for calibrating offset voltage of a comparator applied to a 16-bit low-power-consumption successive approximation type analog-to-digital converter is provided, wherein the 16-bit low-power-consumption successive approximation type analog-to-digital converter comprises the following steps: the circuit comprises a comparator, a capacitor DAC array, control logic and a clock generation circuit, wherein the capacitor DAC array comprises an upper capacitor array and a lower capacitor array which are completely the same;
the positive end input signal is connected to the upper polar plate of the upper capacitor array through the sampling switch, the upper polar plate of the upper capacitor array is connected with the positive input end of the comparator, the negative end input signal is connected to the upper polar plate of the lower capacitor array through the sampling switch, and the upper polar plate of the lower capacitor array is connected with the negative input end of the comparator;
the differential output end of the comparator generates a control signal to control the lower pole plate switches of the upper and lower capacitor arrays after passing through the control logic, so that the lower pole plates of the upper and lower capacitor arrays are connected to corresponding levels, and the control signal is used for controlling the clock of the comparator; the upper capacitor array and the lower capacitor array respectively comprise a high Duan Dianrong array, a middle capacitor array and a low capacitor array;
the high Duan Dianrong array is connected with the middle capacitor array through a bridge capacitor, and the middle capacitor array is connected with the low capacitor array through the bridge capacitor; the middle-section capacitor array comprises a calibration capacitor Cd2, the calibration capacitor Cd2 comprises 31 unit capacitors, the low-section capacitor array comprises a calibration capacitor Cd3, and the calibration capacitor Cd3 comprises 15 unit capacitors;
the offset voltage calibration method comprises the following steps:
s1, starting calibration, and acquiring an initial comparison result D0 of a comparator;
sequentially sequencing the calibration capacitors Cd2 and the calibration capacitors Cd3 in the upper capacitor array according to a sequencing rule that the calibration capacitors Cd2 are in front of and the calibration capacitors Cd3 are in back of the upper capacitor array to obtain an upper capacitor sequence Ci, and sequentially sequencing the calibration capacitors Cd2 and the calibration capacitors Cd3 in the lower capacitor array according to the same sequencing rule to obtain a same lower capacitor sequence Ci;
s2, selecting a first unit capacitor from the upper capacitor sequence Ci and the lower capacitor sequence Ci, adjusting the switching position of a lower plate of the first unit capacitor according to the obtained initial comparison result D0, and then obtaining a comparison result D1 output by a comparator;
then judging whether the comparison result D1 is the same as the initial comparison result D0 or not, and if not, finishing the calibration;
if the two capacitor sequences are the same, continuing to switch the upper capacitor sequence Ci and the lower plate of the second unit capacitor in the lower capacitor sequence Ci according to the initial comparison result D0 to obtain a comparison result D2 output by the comparator;
s3, judging whether the comparison result D2 is the same as the initial comparison result D0, if so, continuing to adjust a third unit capacitor in the sequence according to the initial comparison result D0, and performing circulation until the comparison result Di output by the comparator is different from the initial comparison result D0;
s4, judging whether i is larger than 31, and if i is larger than 31, finishing calibration;
if i is smaller than 31, reassigning the initial comparison result D0 to be a comparison result Di, skipping over the first thirty unit capacitors in the sequence, and adjusting the thirty-second unit capacitor in the sequence according to the reassigned initial comparison result D0 to obtain a comparison result D32;
s5, judging whether the comparison result D32 is the same as the initial comparison result D0 after reassignment, and if not, finishing calibration;
if the two unit capacitors are the same, adjusting the next unit capacitor in the sequence according to the initial comparison result D0 after reassignment, and performing circulation until the latest comparison result of the comparator is not equal to the initial comparison result D0 after reassignment.
Further, according to the initial comparison result D0, the unit capacitance in the sequence is specifically adjusted as follows:
if the initial comparison result D0 is 1, switching the lower plate of the unit capacitor in the upper capacitor sequence Ci to GND, and switching the lower plate of the unit capacitor in the lower capacitor sequence Ci to VDD;
if the initial comparison result D0 is 0, the lower plate of the unit capacitor in the upper capacitor sequence Ci is switched to VDD, and the lower plate of the unit capacitor in the lower capacitor sequence Ci is switched to GND.
Further, before the calibration is started, all the lower plates of the capacitors in the upper capacitor sequence Ci and the lower capacitor sequence Ci are connected to Vcm.
Further, in step S4, if i is smaller than 31, the lower plate of the ith unit capacitor in the sequence is reconnected to Vcm.
Further, the unit capacitance values of the calibration capacitor Cd2 and the calibration capacitor Cd3 are the same and are both 1Cu, and the weight corresponding to one unit capacitor in the calibration capacitor Cd2 is 16 times the weight corresponding to one unit capacitor in the calibration capacitor Cd 3.
Furthermore, the unit capacity value can be selected according to the requirements, and needs to be comprehensively considered from the aspects of time sequence, precision, power consumption, area and the like. The smaller the unit capacitance value, the higher the accuracy of calibration, but the speed of calibration is also reduced and power consumption and area are correspondingly increased.
The invention has the beneficial effects that:
1. the invention can effectively reduce the offset voltage of the comparator, meet the required precision and improve the dynamic range of the SAR ADC.
2. The invention can achieve the purpose of calibrating the offset voltage of the comparator by only adding some digital control logics without adding extra capacitors and generating any adverse effect on the performance of the comparator.
Drawings
Fig. 1 is a block diagram of a general SAR ADC structure;
FIG. 2 is a schematic diagram of an input offset voltage storage technique;
FIG. 3 is a schematic diagram of the output offset voltage storage technique;
FIG. 4 is a schematic diagram of a cascade detuning calibration technique;
FIG. 5 is a unit capacitance number table of capacitors of each part of a three-segment type segmented capacitor DAC array designed by the invention;
FIG. 6 is a block diagram of a three-stage segmented capacitor DAC array structure designed according to the present invention;
FIG. 7 is a block diagram of a capacitor structure for offset voltage calibration of a comparator according to the present invention;
FIG. 8 is a schematic block diagram of the offset voltage calibration of the comparator according to the present invention;
FIG. 9 is a logic diagram illustrating offset voltage calibration of a comparator according to the present invention;
fig. 10 is a diagram of the offset voltage of a comparator to which the present invention is particularly applied.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 5 to fig. 10, the present embodiment provides a method for calibrating offset voltage of a comparator applied to a 16-bit successive approximation type analog-to-digital converter, where the 16-bit successive approximation type analog-to-digital converter includes: the circuit comprises a comparator, a capacitor DAC array, control logic and a clock generation circuit, wherein the capacitor DAC array comprises an upper capacitor array and a lower capacitor array which are completely the same;
the positive end input signal is connected to an upper polar plate of the upper capacitor array through a sampling switch, the upper polar plate of the upper capacitor array is connected with the positive input end of the comparator, the negative end input signal is connected to an upper polar plate of the lower capacitor array through the sampling switch, and the upper polar plate of the lower capacitor array is connected with the negative input end of the comparator;
the differential output end of the comparator generates a control signal to control the lower pole plate switches of the upper and lower capacitor arrays after passing through the control logic, so that the lower pole plates of the upper and lower capacitor arrays are connected to corresponding levels, and the control signal is used for controlling the clock of the comparator; the upper capacitor array and the lower capacitor array respectively comprise a high Duan Dianrong array, a middle capacitor array and a low capacitor array.
Specifically, fig. 5 is a table showing the number of unit capacitors of capacitors in each part of the three-stage segmented capacitor DAC array designed by the present invention, the three-stage segmented capacitor DAC designed by the present invention is composed of three sections, namely, a high section, a middle section and a low section, wherein the high Duan Dianrong array M has 6 bits, and the total number of unit capacitors CMt =64Cu; the middle-section capacitor array L1 has 5 bits, and the total unit capacitor number CL1t =62Cu; the low-section capacitor array L2 has 4 bits, and the total unit capacitor number CL2t =30Cu; the high section, the middle section and the low section are connected through bridging capacitors Ca1 and Ca2, and the bridging capacitors Ca1 and Ca2 are designed to be 2 unit capacitors; besides the capacitors used for sampling and quantification, the capacitors of the high-section capacitor array, the medium-section capacitor array and the low-section capacitor array, which can be used for calibrating offset voltage of the comparator, comprise Cd2 and Cd3, wherein the Cd2 comprises 31 unit capacitors, and the Cd3 comprises 15 unit capacitors; k1 represents the unit capacitance value of the high Duan Dianrong array, K2 represents the unit capacitance value of the middle-section capacitor array, and K1=1 and K2=1 of the design are that the unit capacitance values of the high Duan Dianrong array, the middle-section capacitor array and the low-section capacitor array are the same and are all 1Cu;
fig. 6 is a structural block diagram of a three-stage segmented capacitor DAC array designed by the present invention, where a Duan Dianrong array is connected to a middle-stage capacitor array through a bridging capacitor Ca1, the middle-stage capacitor array is connected to a low-stage capacitor array through a bridging capacitor Ca2, and a Duan Dianrong array includes Cd1, C2, C3, C4, C5, and C6, where Cd1=1cu, C2=2cu, C3=4cu, C4=8cu, C5= 169u, and C6=32cu;
the middle-segment capacitor array comprises Cd2, C1, C2, C3, C4 and C5, wherein Cd2=31Cu, C1=1Cu, C2=2Cu, C3=4Cu, C4=8Cu, C5= 1691u;
the low-section capacitance array comprises Cd3, C1, C2, C3 and C4, wherein Cd3=15Cu, C1=1Cu, C2=2Cu, C3=4Cu, C4=8Cu;
FIG. 7 is a block diagram of a capacitor structure for calibrating offset voltage of a comparator according to the present invention, where Cd2 is composed of 31 unit capacitors Cu and Cd3 is composed of 15 unit capacitors Cu; although the capacitance values of the Cd2 and the Cd3 are the same, the weights corresponding to the unit capacitors are different, and the weight corresponding to one unit capacitor in the Cd2 is 16 times that corresponding to one unit capacitor in the Cd 3;
fig. 8 is a schematic diagram of offset voltage calibration of a comparator, according to a comparison result of the comparator, a lower plate switch of 46 unit capacitors, cd2 and Cd3, is switched through offset voltage calibration control logic of the comparator, and the lower plate is connected to a proper level, and three levels are provided: and when the offset voltage of the comparator is calibrated, whether the Vref or the gnd is received or the Vcm is continuously kept received is determined according to a comparison result of the comparator.
Fig. 9 is a schematic diagram of offset voltage calibration logic of a comparator designed by the present invention, in which 31 unit capacitors Cu of Cd2 and 15 unit capacitors Cu of Cd3 are sequentially sequenced to Ci, where i is an integer between 1 and 46. After calibration is started, the comparator performs initial comparison to obtain a comparison result D0, then the lower plate switch of the first Cu is switched to be connected to a proper level according to the comparison result D0, after the switching is completed, the comparator performs comparison to obtain a comparison result D1, if D1= D0, the 2 nd Cu is continuously switched, after the switching is completed, the comparator performs comparison to obtain a comparison result D2, if D2= D0, the 3 rd Cu is continuously switched, and the operation is circulated until the latest comparison result Di of the comparator is not equal to D0. At this time, if i is greater than 31, it indicates that the whole comparator offset voltage calibration is completed, and the comparator offset voltage is already within the required precision range, so that the requirement can be met;
otherwise, directly skipping the remaining unit capacitors which are not switched in Cd2, starting to switch the unit capacitors in Cd3, simultaneously reassigning D0 as the latest comparison result Di of the comparator, after the 32 th unit capacitor is switched, carrying out comparison by the comparator to obtain a comparison result D32, if D32 is equal to D0, switching the 33 th unit capacitor according to D32, then continuing comparison by the comparator, if the comparison result is equal to D0, continuing to switch the next unit capacitor, continuing comparison by the comparator, and circulating until the latest comparison result Di of the comparator is not equal to D0, and if the latest comparison result Di of the comparator is not equal to D0, indicating that the offset voltage calibration of the whole comparator is completed, and the offset voltage of the comparator is already in the required precision range, so as to meet the requirement.
Fig. 10 is a graph of the offset voltage of a comparator, to which the present invention is specifically applied, the process used by the comparator is the TSMC 40nm process, and the average value μ =561.081 μ V and the standard deviation σ =4.8mV in the case of a power supply voltage of 1.1V. According to the 3 sigma criterion, the probability of the offset voltage distribution of the comparator in (mu-3 sigma, mu +3 sigma) is 0.9973, namely falls in (-4.24mV, 5.36mV), while the offset voltage calibration of the comparator designed by the invention can cover the range of (-9.13mV, 9.13mV). Therefore, the offset voltage calibration method of the comparator designed by the invention can completely correct the offset voltage of the comparator to be within a required precision range.
More specifically, the offset voltage calibration method provided by this embodiment includes the following steps:
s1, starting calibration, and acquiring an initial comparison result D0 of a comparator;
sequentially sequencing the calibration capacitors Cd2 and the calibration capacitors Cd3 in the upper capacitor array according to a sequencing rule that the calibration capacitors Cd2 are in front of and the calibration capacitors Cd3 are in back of the upper capacitor array to obtain an upper capacitor sequence Ci, and sequentially sequencing the calibration capacitors Cd2 and the calibration capacitors Cd3 in the lower capacitor array according to the same sequencing rule to obtain a same lower capacitor sequence Ci;
s2, selecting a first unit capacitor from the upper capacitor sequence Ci and the lower capacitor sequence Ci, adjusting the switching position of the lower plate of the first unit capacitor according to the obtained initial comparison result D0, and then obtaining a comparison result D1 output by the comparator;
then judging whether the comparison result D1 is the same as the initial comparison result D0 or not, and if not, finishing the calibration;
if the two capacitor sequences are the same, continuing to switch the lower plate of the second unit capacitor in the upper capacitor sequence Ci and the lower capacitor sequence Ci according to the initial comparison result D0 to obtain a comparison result D2 output by the comparator;
s3, judging whether the comparison result D2 is the same as the initial comparison result D0, if so, continuing to adjust a third unit capacitor in the sequence according to the initial comparison result D0, and performing circulation until the comparison result Di output by the comparator is different from the initial comparison result D0;
s4, judging whether i is larger than 31, and if i is larger than 31, finishing calibration;
if i is smaller than 31, reassigning the initial comparison result D0 to be a comparison result Di, skipping over the first thirty unit capacitors in the sequence, and adjusting the thirty-second unit capacitor in the sequence according to the reassigned initial comparison result D0 to obtain a comparison result D32;
s5, judging whether the comparison result D32 is the same as the initial comparison result D0 after re-assignment, and if not, finishing calibration;
if the two unit capacitors are the same, adjusting the next unit capacitor in the sequence according to the initial comparison result D0 after reassignment, and performing circulation until the latest comparison result of the comparator is not equal to the initial comparison result D0 after reassignment.
More specifically, in this embodiment, according to the initial comparison result D0, the unit capacitance in the sequence is adjusted specifically as follows:
if the initial comparison result D0 is 1, switching the lower plate of the unit capacitor in the upper capacitor sequence Ci to GND, and switching the lower plate of the unit capacitor in the lower capacitor sequence Ci to VDD;
if the initial comparison result D0 is 0, the lower plate of the unit capacitor in the upper capacitor sequence Ci is switched to VDD, and the lower plate of the unit capacitor in the lower capacitor sequence Ci is switched to GND.
The details of the present invention are well known to those skilled in the art.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations can be devised by those skilled in the art in light of the above teachings. Therefore, the technical solutions that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the prior art according to the concepts of the present invention should be within the scope of protection determined by the claims.
Claims (5)
1. A method for calibrating offset voltage of a comparator applied to a 16-bit low-power successive approximation type analog-to-digital converter, the 16-bit low-power successive approximation type analog-to-digital converter comprising: the circuit comprises a comparator, a capacitor DAC array, control logic and a clock generation circuit, wherein the capacitor DAC array comprises an upper capacitor array and a lower capacitor array which are identical;
the positive end input signal is connected to an upper polar plate of an upper capacitor array through a sampling switch, the upper polar plate of the upper capacitor array is connected with the positive input end of the comparator, the negative end input signal is connected to an upper polar plate of a lower capacitor array through the sampling switch, and the upper polar plate of the lower capacitor array is connected with the negative input end of the comparator;
the differential output end of the comparator generates a control signal to control the lower pole plate switches of the upper and lower capacitor arrays after passing through the control logic, so that the lower pole plates of the upper and lower capacitor arrays are connected to corresponding levels, and the control signal is used for controlling the clock of the comparator; the upper capacitor array and the lower capacitor array respectively comprise a high Duan Dianrong array, a middle capacitor array and a low capacitor array;
the high Duan Dianrong array is connected with the middle capacitor array through a bridge capacitor, and the middle capacitor array is connected with the low capacitor array through the bridge capacitor; the method is characterized in that the middle-section capacitor array comprises a calibration capacitor Cd2, the calibration capacitor Cd2 comprises 31 unit capacitors, the low-section capacitor array comprises a calibration capacitor Cd3, and the calibration capacitor Cd3 comprises 15 unit capacitors;
the offset voltage calibration method comprises the following steps:
s1, starting calibration, and acquiring an initial comparison result D0 of a comparator;
sequentially sequencing the calibration capacitors Cd2 and the calibration capacitors Cd3 in the upper capacitor array according to a sequencing rule that the calibration capacitors Cd2 are in front of and the calibration capacitors Cd3 are in back of the upper capacitor array to obtain an upper capacitor sequence Ci, and sequentially sequencing the calibration capacitors Cd2 and the calibration capacitors Cd3 in the lower capacitor array according to the same sequencing rule to obtain a same lower capacitor sequence Ci;
s2, selecting a first unit capacitor from the upper capacitor sequence Ci and the lower capacitor sequence Ci, adjusting the switching position of a lower plate of the first unit capacitor according to the obtained initial comparison result D0, and then obtaining a comparison result D1 output by a comparator;
then judging whether the comparison result D1 is the same as the initial comparison result D0 or not, and if not, finishing the calibration;
if the two capacitor sequences are the same, continuing to switch the upper capacitor sequence Ci and the lower plate of the second unit capacitor in the lower capacitor sequence Ci according to the initial comparison result D0 to obtain a comparison result D2 output by the comparator;
s3, judging whether the comparison result D2 is the same as the initial comparison result D0, if so, continuing to adjust a third unit capacitor in the sequence according to the initial comparison result D0, and circulating until the comparison result Di output by the comparator is different from the initial comparison result D0;
s4, judging whether i is larger than 31, and if i is larger than 31, finishing calibration;
if i is smaller than 31, reassigning the initial comparison result D0 to be a comparison result Di, skipping over the first thirty unit capacitors in the sequence, and adjusting the thirty-second unit capacitor in the sequence according to the reassigned initial comparison result D0 to obtain a comparison result D32;
s5, judging whether the comparison result D32 is the same as the initial comparison result D0 after re-assignment, and if not, finishing calibration;
if the two unit capacitors are the same, adjusting the next unit capacitor in the sequence according to the initial comparison result D0 after reassignment, and performing circulation until the latest comparison result of the comparator is not equal to the initial comparison result D0 after reassignment.
2. The method according to claim 1, wherein the adjusting the unit capacitance in the sequence according to the initial comparison result D0 is specifically:
if the initial comparison result D0 is 1, switching the lower plate of the unit capacitor in the upper capacitor sequence Ci to GND, and switching the lower plate of the unit capacitor in the lower capacitor sequence Ci to VDD;
if the initial comparison result D0 is 0, the lower plate of the unit capacitor in the upper capacitor sequence Ci is switched to VDD, and the lower plate of the unit capacitor in the lower capacitor sequence Ci is switched to GND.
3. The method according to claim 2, wherein before the calibration is started, all of the lower plates of the capacitors in the upper capacitor sequence Ci and the lower capacitor sequence Ci are connected to Vcm.
4. The method of claim 3, wherein in step S4, if i is smaller than 31, the lower plate of the ith unit capacitor in the sequence is reconnected to Vcm.
5. The method as claimed in claim 4, wherein the calibration capacitor Cd2 and the calibration capacitor Cd3 have the same capacitance per unit capacitor, and are both 1Cu, and the weight corresponding to one unit capacitor in the calibration capacitor Cd2 is 16 times the weight corresponding to one unit capacitor in the calibration capacitor Cd 3.
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