CN113130337A - Two-step process method for high-reliability flip interconnection of high-density narrow-spacing chip based on ACA/ACF - Google Patents
Two-step process method for high-reliability flip interconnection of high-density narrow-spacing chip based on ACA/ACF Download PDFInfo
- Publication number
- CN113130337A CN113130337A CN202110396600.4A CN202110396600A CN113130337A CN 113130337 A CN113130337 A CN 113130337A CN 202110396600 A CN202110396600 A CN 202110396600A CN 113130337 A CN113130337 A CN 113130337A
- Authority
- CN
- China
- Prior art keywords
- chip
- aca
- acf
- interconnection
- step process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000002245 particle Substances 0.000 claims abstract description 25
- 239000003292 glue Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000000853 adhesive Substances 0.000 claims abstract description 11
- 230000001070 adhesive effect Effects 0.000 claims abstract description 11
- 239000011248 coating agent Substances 0.000 claims abstract description 8
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 description 10
- 238000004458 analytical method Methods 0.000 description 7
- 238000004377 microelectronic Methods 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- CJRQAPHWCGEATR-UHFFFAOYSA-N n-methyl-n-prop-2-ynylbutan-2-amine Chemical compound CCC(C)N(C)CC#C CJRQAPHWCGEATR-UHFFFAOYSA-N 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention provides a high-reliability flip chip interconnection two-step process method of a high-density narrow-spacing chip based on ACA/ACF, which comprises the following steps: step 1: coating a layer of insulating glue with the height not higher than that of the bump (bump) on the chip, wherein the insulating glue does not cover the top end of the bump; step 2: a layer of anisotropic conductive adhesive (ACA/ACF) is coated on the substrate, and then the chip and the substrate are subjected to hot-press bonding to obtain high-reliability interconnection. The invention cuts off the connection between two adjacent bump, can effectively prevent conductive particles from entering between two bumps in the curing process, and greatly reduces the probability of short circuit between the bumps; and moreover, the generation of cavities between bumps during flip-chip bonding is reduced, the contact thermal resistance of ACA/ACF interconnection is reduced, and the interconnection reliability of the narrow-spacing chip is improved. In addition, the invention reduces the stress caused by the mismatch of CTE coefficients of materials; the bonding strength of chip interconnection is improved, and the mechanical property of chip bonding is improved.
Description
Technical Field
The invention relates to the technical field of chip flip-chip bonding by adopting ACA/ACF interconnection, in particular to a two-step process method for high-reliability flip-chip interconnection of a high-density narrow-spacing chip based on ACA/ACF.
Background
The microelectronic industry is the first industry in the current information age, the manufacturing process of microelectronic devices as the basis of the electronic industry is continuously advanced along with the technical innovation, the microelectronic packaging technology enters the age of super-large scale integrated circuits after the 21 st century, and the high-density packaging is the inevitable trend of the development of the microelectronic technology. The interconnection size is reduced from 30 μm, which is of great significance to the development of microelectronic encapsulation technology. The electronic packaging technology aims to lead the system to develop towards miniaturization, high performance, high reliability and low cost. At present, the bonding modes of the bump and the bonding pad mainly comprise 3 types of lead bonding, tape automated bonding and flip-chip bonding. The carrier tape automatic soldering and wire bonding technology is not suitable for high-density packaging of chips due to the limitations of the carrier tape automatic soldering and wire bonding technology, and the flip-chip building technology is more and more commonly applied to microelectronic packaging due to the advantages of small space, simple process, low cost and the like. The flip-chip bonding comprises three main forms of controlled collapse chip connection, thermosonic bonding and conductive adhesive connection. As flip-chip interconnection technology becomes the mainstream of the packaging industry, interconnection density is increased continuously, bump distance is reduced continuously, and new interconnection materials and technology must be developed to meet the increasingly strict requirements of mechanical, thermal and electrical properties of interconnection. Micro/nano interconnect technology has been developed to be adopted by the industry to realize high-density, multifunctional integration and packaging. Advances in micro/nano-system technology have not guaranteed the reliability of conventional interconnect materials. The development of electronic components has been limited by interconnects. Therefore, in order to alleviate the problems related to the existing interconnection, two solutions are proposed, one is to adopt anisotropic conductive adhesive for interconnection, and the other is to develop a novel interconnection material with higher material performance.
Anisotropic conductive adhesive (ACA/ACF) is considered to be one of the most promising packaging materials. ACA/ACF is a composite material, which is composed of a polymer matrix (epoxy resin) and conductive particles randomly distributed therein, has the advantages of no pollution, low curing temperature, suitability for thermosensitive materials and non-weldable materials, capability of providing interconnection with finer spacing, simple process steps, good maintenance performance and the like, and is a very important lead-free connecting material. They can be classified into paste-like Anisotropic Conductive Adhesives (ACAs) and film-like anisotropic conductive Adhesives (ACFs) according to their existence. The biggest problem currently encountered by ACA/ACF is that short circuits are easily generated in the interconnects,
disclosure of Invention
The invention provides a high-reliability flip interconnection two-step process method of a high-density narrow-space chip based on ACA/ACF, and aims to realize the high-density narrow-space interconnection of the chip and improve the reliability of chip packaging by adopting a conductive adhesive two-step process method.
In order to achieve the above object, the present invention provides a two-step process method for high-reliability flip chip interconnection of high-density narrow-pitch chip based on ACA/ACF, comprising the steps of:
step 1: coating a layer of insulating glue with the height not higher than that of the bump (bump) on the chip, wherein the insulating glue does not cover the top end of the bump;
step 2: a layer of anisotropic conductive adhesive (ACA/ACF) is coated on the substrate, and then the chip and the substrate are subjected to hot-press bonding to obtain high-reliability interconnection.
Preferably, the bump pitch is 10um or less.
Preferably, the height difference between the thickness of the insulating glue and the bump is not more than 0.5 um.
Preferably, the substrate is preheated before the ACA/ACF coating.
Preferably, the preheating temperature is 60-90 ℃ and the time is 2-5 s.
Preferably, the viscosity of the insulating glue is greater than that of ACA/ACF.
Preferably, the ACA/ACF is 10-20 um thick and is in full contact with the insulating glue during bonding.
Preferably, during thermocompression bonding, the chip bumps are aligned with the substrate pads, and the coverage area of the insulating glue is larger than that of the ACA/ACF.
Preferably, the temperature of the hot-press bonding is 150-210 ℃; the pressure is 15-60 MPa; the time is 8-15 s.
Preferably, the diameter of the conductive particles in the ACA/ACF is less than 1.5 um.
The scheme of the invention has the following beneficial effects:
according to the invention, before flip-chip bonding, the chip is coated with the insulating glue, so that on one hand, the connection between two adjacent bumps is cut off, conductive particles can be effectively prevented from entering between the two bumps in the curing process, and the probability of short circuit between the bumps is greatly reduced; on the other hand, the insulating glue is fully distributed between the bumps, so that the generation of cavities between the bumps during flip-chip bonding is reduced, the contact thermal resistance of ACA/ACF interconnection is reduced, and the interconnection reliability of the narrow-pitch chip is improved.
According to the invention, a layer of insulating glue is coated before the ACA/ACF is used, so that the stress caused by mismatch of CTE coefficients of materials is reduced; the bonding strength of chip interconnection is improved, and the mechanical property of chip bonding is improved.
The method is simple and efficient, can effectively improve the reliability of the interconnection of the high-density narrow-spacing chips, improves the quality of flip interconnection of the chips, and is beneficial to industrial production.
Drawings
FIG. 1 is a schematic diagram of an interconnect die of the present invention.
Fig. 2 shows l ═ 10 μm and d ═ 10 μm; and when Vf is 0.15 and r is 1-3 μm, the probability of short circuit and open circuit changes.
Fig. 3 shows l-10 μm and d-10 μm; and when Vf is 0-0.3 and r is 1.5 mu m, the probability change graph of short circuit and open circuit is shown.
Fig. 4 shows Vf equal to 0.145; r is 1.5 μm; d is 10 μm; graph of probability change of short circuit and open circuit when l is 10 μm.
Fig. 5 shows Vf equal to 0.145; r is 1.3 μm; d is 9 μm; graph of probability change of short circuit and open circuit when l is 9 μm.
Fig. 6 shows Vf equal to 0.145; r is 1.1 μm; d is 8 μm; graph of probability change of short circuit and open circuit when l is 8 μm.
[ description of reference ]
1-chip; 2-bump; 3-insulating glue; 4-ACA/ACF; 5-a substrate; 6-bonding pad.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
Examples 1 to 10
The bump pitch and the insulating paste of the chips were designed as shown in table 1,
coating a layer of insulating glue on a chip, preheating a substrate for 5s at 60 ℃, and then coating ACA/ACF on the substrate, wherein the coating area of the ACA/ACF is smaller than that of the insulating glue; aligning the chip salient points with the substrate bonding pads, and thermally pressing and bonding for 15s at 150 ℃ and 15MPa to ensure that the conductive particles deform to a certain extent, so as to obtain the interconnection of the high-density narrow-spacing chip with high reliability, as shown in figure 1.
Failure probability analysis by two-step process
Open circuit analysis
Assuming that the conductive particles in the ACF obey a poisson distribution, then:
wherein r is the radius of the conductive particles; l is the side length of the square bump; vf is the volume fraction of conductive particles in the ACF; u1 is the average number of conductive particles on the bump.
Short circuit analysis
Wherein d is the distance between the bumps; h is the sum of the bump height and the diameter of the conductive particles; u2 is the average number of conductive particles between bump areas; k is the number of cubic boxes containing conductive particles between bump regions, (4 π r3And/3) the volume of the cubic box of conductive particles; n is the number of cubic boxes between bump areas, (2r)3Volume of cube box;
global failure probability analysis
If the open and short circuits are independent events:
Popening∩bridging＝Pbridging·Popening
Popening∪bridging＝Popening+Pbridging-Popening∩bridging
＝Popening+Pbridging-Popening·Pbridging
the invention adopts a two-step process method, a layer of insulating glue is coated between bonding, the entering of conductive particles is effectively prevented, the area where the conductive particles can enter between the bump is changed from the previous h +2r to the current h ═ 2r, the open circuit probability of the bump is known from a calculation formula to be unrelated to the value of h, and the open circuit is mainly determined by the radius of the conductive particles and the volume fraction of the conductive particles; the addition of the insulating paste only reduces the probability of short circuit failure between the bumps.
When l is 10 μm, d is 10 μm; when Vf is 0.15 and r is 1 to 3 μm, the probability of short circuit and open circuit changes as shown in fig. 2.
When l is 10 μm, d is 10 μm; fig. 3 shows the probability of short-circuit and open-circuit when Vf is 0 to 0.3 and r is 1.5 μm.
As can be seen from fig. 2 and 3, when the diameter of the conductive particles is less than 1.6 μm and the integral number of the conductive particles is about 0.145, the reliable interconnection between the chip and the substrate can be ensured, so that the failure probability of both short circuit and open circuit is below 5%; as the distance between the bumps decreases, the diameter of the conductive particles should gradually decrease.
When the diameters r of the conductive particles are 1.5 μm, 1.3 μm, and 1.1 μm, respectively, the probability variation of the short circuit and the open circuit is changed as shown in fig. 4, 5, and 6, respectively.
The failure probability analysis results are shown in table 1:
TABLE 1 analysis results of probability of open, short, and total failures for embodiments of the present invention
Analysis shows that when the diameter of the conductive particles is less than 1.5 micrometers, and the volume fraction of the conductive particles is 0.15 +/-0.025, a layer of insulating glue with the distance of less than 0.5 micrometers from the bump top end is coated between bonding by adopting a two-step process method, so that the size of the particles entering a bump area is reduced, the distance between bumps is less than 10 micrometers, the probability of flip chip interconnection failure can be effectively reduced to less than 10%, and the reliable interconnection of high-density narrow-pitch chips is realized.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A two-step process method for high-reliability flip chip interconnection of a high-density narrow-space chip based on ACA/ACF is characterized by comprising the following steps:
step 1: coating a layer of insulating glue on the chip, wherein the height of the insulating glue is not higher than that of the salient points, and the insulating glue does not cover the top ends of the salient points;
step 2: and coating a layer of anisotropic conductive adhesive on the substrate, and then carrying out hot-press bonding on the chip and the substrate to obtain the interconnection with high reliability.
2. The two-step process method for high reliability flip chip interconnection of ACA/ACF based high density narrow pitch chip as claimed in claim 1, wherein the pitch of the bumps is 10um or less.
3. The two-step process method for high reliability flip chip interconnection of ACA/ACF based high density narrow space chip as claimed in claim 1, wherein the difference between the thickness of the insulating glue and the height of the bump is not more than 0.5 um.
4. The two-step process of ACA/ACF-based high-density narrow-pitch chip high-reliability flip chip interconnection as claimed in claim 1, wherein the substrate is preheated before the anisotropic conductive paste is coated.
5. The ACA/ACF-based two-step process method for high-reliability flip chip interconnection of high-density narrow-pitch chips according to claim 4, wherein the preheating temperature is 60-90 ℃ and the time is 2-5 s.
6. The two-step process method for high reliability flip chip interconnection of high density narrow pitch ACA/ACF based chip according to claim 1, wherein the viscosity of the insulating paste is greater than that of the anisotropic conductive paste.
7. The ACA/ACF-based two-step process method for high-reliability flip chip interconnection of high-density narrow-pitch chips as claimed in claim 1, wherein the anisotropic conductive adhesive has a thickness of 10-20 um and is in full contact with the insulating adhesive during bonding.
8. The ACA/ACF based high density narrow pitch chip high reliability flip chip interconnect two step process of claim 1, wherein the chip bumps are aligned with the substrate pads during thermocompression bonding, and the coverage area of the insulating glue is larger than that of the anisotropic conductive glue.
9. The ACA/ACF-based high-density narrow-pitch chip high-reliability flip chip interconnection two-step process method as claimed in claim 1, wherein the temperature of the hot-press bonding is 150-210 ℃; the pressure is 15-60 MPa; the time is 8-15 s.
10. The two-step process method for high reliability flip chip interconnection of high density narrow pitch ACA/ACF based chip according to claim 1, the diameter of the conductive particles in the anisotropic conductive paste is less than 1.5 um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110396600.4A CN113130337A (en) | 2021-04-13 | 2021-04-13 | Two-step process method for high-reliability flip interconnection of high-density narrow-spacing chip based on ACA/ACF |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110396600.4A CN113130337A (en) | 2021-04-13 | 2021-04-13 | Two-step process method for high-reliability flip interconnection of high-density narrow-spacing chip based on ACA/ACF |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113130337A true CN113130337A (en) | 2021-07-16 |
Family
ID=76776646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110396600.4A Pending CN113130337A (en) | 2021-04-13 | 2021-04-13 | Two-step process method for high-reliability flip interconnection of high-density narrow-spacing chip based on ACA/ACF |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113130337A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030004741A (en) * | 2001-07-06 | 2003-01-15 | 한국과학기술원 | Anisotropic conductive film and method of fabricating the same for ultra-fine pitch COG application |
| KR20030008607A (en) * | 2001-07-19 | 2003-01-29 | 한국과학기술원 | High adhesion triple layered anisotropic conductive adhesive film |
| CN101315916A (en) * | 2008-04-21 | 2008-12-03 | 上海大学 | Mobile phone drive chip interconnection module group and method for producing the same |
| US20090029504A1 (en) * | 2007-07-23 | 2009-01-29 | Korea Advanced Institute Of Science And Technology | Wafer-level aca flip chip package using double-layered aca/nca |
| CN110797267A (en) * | 2019-11-12 | 2020-02-14 | 中南大学 | Bottom filling method with interconnection structure in flip chip packaging |
| CN112466765A (en) * | 2020-11-26 | 2021-03-09 | 安徽光智科技有限公司 | Focal plane array flip interconnection process method and focal plane array detector |
-
2021
- 2021-04-13 CN CN202110396600.4A patent/CN113130337A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030004741A (en) * | 2001-07-06 | 2003-01-15 | 한국과학기술원 | Anisotropic conductive film and method of fabricating the same for ultra-fine pitch COG application |
| KR20030008607A (en) * | 2001-07-19 | 2003-01-29 | 한국과학기술원 | High adhesion triple layered anisotropic conductive adhesive film |
| US20090029504A1 (en) * | 2007-07-23 | 2009-01-29 | Korea Advanced Institute Of Science And Technology | Wafer-level aca flip chip package using double-layered aca/nca |
| CN101315916A (en) * | 2008-04-21 | 2008-12-03 | 上海大学 | Mobile phone drive chip interconnection module group and method for producing the same |
| CN110797267A (en) * | 2019-11-12 | 2020-02-14 | 中南大学 | Bottom filling method with interconnection structure in flip chip packaging |
| CN112466765A (en) * | 2020-11-26 | 2021-03-09 | 安徽光智科技有限公司 | Focal plane array flip interconnection process method and focal plane array detector |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8642393B1 (en) | Package on package devices and methods of forming same | |
| KR100398314B1 (en) | High Adhesion Triple layered anisotropic conductive adhesive film | |
| KR100315158B1 (en) | High reliability non-conductive adhesives for non-solder flip chip bondings and flip chip bonding method using the same | |
| CN101345199B (en) | Packaging structure and its forming method | |
| US20210305192A1 (en) | Semiconductor device package and method for manufacturing the same | |
| US9258904B2 (en) | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings | |
| CN103035593A (en) | Package on packaging structure and methods of making same | |
| US20140367850A1 (en) | Stacked package and method of fabricating the same | |
| TW550768B (en) | Flip-chip on film assembly for ball grid array packages | |
| CN112289743A (en) | Wafer system level fan-out package structure and manufacturing method thereof | |
| TW202243151A (en) | Structure and formation method of chip package with protective lid | |
| US11495531B2 (en) | Semiconductor device package and method of manufacturing the same | |
| US20210265290A1 (en) | Semiconductor package structures and methods of manufacturing the same | |
| CN112289742A (en) | Wafer system level three-dimensional fan-out type packaging structure and manufacturing method thereof | |
| CN113130337A (en) | Two-step process method for high-reliability flip interconnection of high-density narrow-spacing chip based on ACA/ACF | |
| US8558380B2 (en) | Stack package and method for manufacturing the same | |
| CN210805773U (en) | 3DIC packaging structure | |
| CN213184262U (en) | Three-dimensional stacked bonding structure of high-density chip | |
| CN109065515B (en) | Chip packaging structure with high conductivity and low resistance and preparation method thereof | |
| CN113990815A (en) | Silicon-based micro-module plastic package structure and preparation method thereof | |
| CN113113402A (en) | 3DIC packaging structure and preparation method | |
| CN213242550U (en) | Wafer system level fan-out type packaging structure | |
| CN213242537U (en) | Wafer system level three-dimensional fan-out type packaging structure | |
| US11201110B2 (en) | Semiconductor device package with conductive pillars and method for manufacturing the same | |
| TWI825790B (en) | Electronic package and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20240124 Address after: 410000 East, 2nd floor, building C, Lugu high level Talents Innovation and entrepreneurship Park, no.1698, Yuelu West Avenue, Changsha high tech Development Zone, Changsha City, Hunan Province Applicant after: Changsha Anmuquan Intelligent Technology Co.,Ltd. Country or region after: China Address before: 410000 East, 2nd floor, building C, Lugu high level Talents Innovation and entrepreneurship Park, no.1698, Yuelu West Avenue, Changsha high tech Development Zone, Changsha City, Hunan Province Applicant before: Changsha Anmuquan Intelligent Technology Co.,Ltd. Country or region before: China Applicant before: CENTRAL SOUTH University |