CN101286817A - General decoding method for conventional binary and double-binary Turbo code - Google Patents

Abstract

The invention relates to a general decoding method applied to traditional binary Turbo codes and duobinary Turbo codes. At present, no Turbo code decoding device can decode traditional binary Turbo codes as well as duobinary Turbo codes. The general decoding method for Turbo codes provided by the invention adopts enhanced Max-Log-MAP algorithm, makes use of Max-Sum semiring property in the generalized distribution law and combines and simplifies measure and calculation of forward and backward status of traditional binary Turbo codes, which means combining grid graph of traditional binary Turbo codes in nature to ensure that the status measure and calculation of the traditional binary Turbo codes have the same calculation expression way with that of the duobinary Turbo codes so that a general decoding device can both decode the traditional binary Turbo codes and duobinary Turbo codes. The method of the invention gives full consideration to the four indexes, namely, good generality, decoding performance, decoding complexity and resource occupation.

Description

Traditional binary and duobinary system Turbo code general decoding method

Technical field

What the present invention relates to is a kind of decoding scheme that is used for communication technical field, is a kind of traditional binary Turbo code and duobinary system Turbo code general decoding method of being applied to specifically.

Background technology

Founder's Shannon of modern digital communication was just pointed out in channel coding theorem as far back as 1948, as long as the code length of random coded is enough big, just can infinitely approaches the communication of channel capacity C and make error probability arbitrarily small.But Shannon has just proved the existence of the coding limit theoretically, does not but construct a kind of coding and decoding structure and approaches this limit.After Shannon, the sign indicating number of many excellent performances occurs in succession, BCH code, RS sign indicating number and convolution code etc., and they can both obtain good performance, but limit with the performance that Shannon proposes, and also have many gaps.

Up to the discovery of Turbo code, just make channel coding theorem step major step approaching on the road of shannon limit.1993, Berrou, Glavieux and Thitimajshima proposed Turbo code first in the meeting of ICC, realized the coding of big constraint length by the pseudo random interleaving to subcode, adopted soft inputting and soft output iterative decoding to approach maximum-likelihood decoding.Simulation result shows, is under the awgn channel condition of 0.7dB in signal to noise ratio, adopts (21,37) recursive systematic convolutional code as component code, interleave depth 65536, and the error rate drops to 10 after the iteration 18 times ^-5Below, only have only 0.7dB from shannon limit.

Berrou had proposed the duobinary system Turbo code in 1996, compared with the traditional binary Turbo code, and the duobinary system Turbo code has the following advantages: interleave depth is half of classical Turbo code, and decoding delay reduces; Interweaving by intersymbol increases minimum free distance, eliminates the error code flat bed; Under the identical complexity decoder, the error-correcting performance of duobinary system Turbo code is better than traditional Turbo code; Code check is deleted surplus performance impact for the duobinary system Turbo code less than traditional Turbo code; Adopt the circulation recursive systematic convolutional code to do subcode, it does not need " ending bit " just can make each frame have identical initial condition and state of termination.Because its outstanding performance, the duobinary system Turbo code has been widely used in the standard of a lot of radio communications at present, has all adopted the duobinary system Turbo code as WiMAX (IEEE 802.16) and European satellite network standard (DVB-RCS).

From the decoding algorithm angle, the Turbo code decoding algorithm is divided into two classes: a class is to be developed and next SOVA algorithm by the Viterbi algorithm, one class is based on the MAP algorithm of posterior probability, and by extended Log-MAP algorithm of MAP algorithm and correction Max-Log-MAP algorithm.The algorithm decoding performance of Log-MAP is relatively good, but needs a large amount of exponential sum logarithms to calculate the complexity height; And the Max-Log-MAP algorithm substitutes logarithm operation with addition and maximizing fully, and complexity is low, helps the realization on the hardware.From the way of output, duobinary decoding can be divided into again based on symbol with based on the decoded mode of the posterior probability log-likelihood ratio of bit.

The duobinary system Turbo code is compared with traditional binary system Turbo code a lot of outstanding performances, but the Turbo code that at present a lot of communication standards adopt still is the traditional binary Turbo code, what communication protocol that some are newer such as 3GPP-LTE, UMB etc. also adopted is the traditional binary Turbo code.And present Turbo code decoder all is special-purpose Turbo code decoder, can either not decipher the traditional binary Turbo code for one, also can be to the Turbo code decoder of duobinary system Turbo code decoding.

Figure 1 shows that the Log-MAP algorithm forward state metric α of traditional binary Turbo code _k(s) basic module ACSO (Add-Compare-Select-Offset) structure of recursion calculating.The forward recursion α of duobinary system Turbo code _k(s) basic structure owing to be that four numbers are got peaked structure, therefore can add that a CSO module forms by two ACSO modules as shown in Figure 2.Traditional binary Turbo code and the most basic recursion construction module of duobinary system Turbo code can't be shared as can be seen by Fig. 1 and 2.This is the principal element of the general Turbo code design of encoder of restriction.

Summary of the invention

The object of the present invention is to provide a kind of general configurable Turbo code interpretation method, make decoder both can decipher to the traditional binary Turbo code, also can decipher simultaneously, and general configurable Turbo code code translator when deciphering traditional Turbo code, special-purpose Turbo code decoder can reduce by one times of time delay the duobinary system Turbo code.

The Turbo code general decoding method that the present invention proposes adopts the Max-log-MAP algorithm of enhancement mode, approaches the Log-MAP algorithm on its performance, but has saved correction function when computing mode is measured, and has simplified decoding algorithm, has reduced the time delay of decoding.

The Turbo code general decoding method that the present invention proposes utilizes the Max-Sum semi-ring character in the broad sense apportionment ratio, forward direction and back to the traditional binary Turbo code merge simplification to state metric calculation, from just the grid chart of traditional binary Turbo code being merged in essence, make the state measurement of traditional binary Turbo code have the calculation expression the same, thereby general decoding method all can be realized to traditional binary Turbo code and duobinary system Turbo code with the duobinary system Turbo code.

In the enhancement mode Max-Log-MAP algorithm forward direction and the back to the state measurement recurrence formula as shown in the formula shown in (1) and the formula (2):

${\mathrm{\α}}_k\left(s\right)=\underset{s^{\′}\∈S}{\max }({\mathrm{\α}}_{k-1}\left(s^{\′}\right)+{\mathrm{\γ}}_k(s^{\′},s))---\left(1\right)$

${\mathrm{\β}}_{k-1}\left(s^{\′}\right)=\underset{s^{\′}\∈S}{\max }({\mathrm{\β}}_k\left(s\right)+{\mathrm{\γ}}_k(s^{\′},s))---\left(2\right)$

Definition "+" is

, " max " is , the max-sum computing is an exchange semi-loop so, uses

Represent $x_m\⊕x_{m+1}\⊕\·\·\·\⊕x_n(m\≤n),$ Come rewriting formula (1) with symbol defined above, then obtain formula (3), wherein M is the coder state number:

${\mathrm{\α}}_k\left(s\right)=\underset{i=1}{\overset{M}{\mathrm{\⊕}}}{\mathrm{\γ}}_k(s^{\′},s)\⊗{\mathrm{\α}}_{k-1}\left(s^{\′}\right)---\left(3\right)$

According to formula (3) forward recursion of Turbo code is converted into the matrix-vector product form:

$A_k={\mathrm{\Γ}}_k\⊗A_{k-1}---\left(4\right)$

Wherein, forward state metric vector A _kFor:

A _k＝(α _k(0)，α _k(1)，…，α _k(M-1)) ^T (5)

M * M rank matrix-vector Г _kAll branched measurement value γ have been comprised _k(s ', s), multiplication identical element Q=0 represents that branch metric is 0 γ _k(s ', s), matrix-vector Г _kThe corresponding branch metric of the same state s of k constantly of row vector, the corresponding branch metric of the same state s ' of k-1 constantly of column vector.The branch metric matrix of a four condition encoder is

${\mathrm{\Γ}}_k=\left(\begin{array}{cccc}{\mathrm{\γ}}_k\left(\mathrm{0,0}\right)& Q& {\mathrm{\γ}}_k\left(\mathrm{2,0}\right)& Q\\ {\mathrm{\γ}}_k\left(\mathrm{0,1}\right)& Q& {\mathrm{\γ}}_k\left(\mathrm{2,1}\right)& Q\\ Q& {\mathrm{\γ}}_k\left(\mathrm{1,2}\right)& Q& {\mathrm{\γ}}_k\left(\mathrm{3,2}\right)\\ Q& {\mathrm{\γ}}_k\left(\mathrm{1,3}\right)& Q& {\mathrm{\γ}}_k\left(\mathrm{3,3}\right)\end{array}\right)---\left(6\right)$

Because backward recursion computing formula and forward recursion computing formula are similar, equally also represent with the form of matrix-vector product:

$B_{k-1}={\mathrm{\Γ}}_k\⊗B_k---\left(7\right)$

Wherein, the back is to state measurement vector B _kFor:

B _k＝(β _k(0)，β _k(1)，…，β _k(M-1)) ^T (8)

The method for expressing of matrix-vector product makes us all computings of semi-ring can be used for the reckoning of forward recursion and backward recursion, finally merges grid chart.

Can represent with the form of the matrix-vector product of recurrence because forward direction and backward recursion calculate, therefore formula (9) is updated in the formula (10) and can obtain formula (11):

$A_{k+2}={\mathrm{\Γ}}_{k+2}\⊗A_{k+1}---\left(9\right)$

$A_{k+1}={\mathrm{\Γ}}_{k+1}\⊗A_k---\left(10\right)$

$A_{k+2}={\mathrm{\Γ}}_{k+2}\⊗({\mathrm{\Γ}}_{k+1}\⊗A_k)=({\mathrm{\Γ}}_{k+2}\⊗{\mathrm{\Γ}}_{k+1})\⊗A_k---\left(11\right)$

That is to say only needs to merge the branch metric matrix, and just two step forward recursion can be merged becomes the single step forward recursion.Definition ${}_2\mathrm{\&Gamma;}_{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="A20081006032100261.png,A20081006032100272.png"\; state="\{\{state\}\}">k</figure-callout>}}={\mathrm{\&Gamma;}}_{k+2}\&CircleTimes;{\mathrm{\&Gamma;}}_{k+1},$ Each element is in the single step forward recursion metric matrix after the merging:

${}_2\mathrm{\&Gamma;}_k(i,j)={\mathrm{\&Gamma;}}_{k+2}\&CircleTimes;{\mathrm{\&Gamma;}}_{k+1}$

$=\underset{l=0}{\overset{M-1}{\mathrm{\&CirclePlus;}}}{\mathrm{\&Gamma;}}_{k+2}(i,l)\&CircleTimes;{\mathrm{\&Gamma;}}_{k+1}(l,j)---\left(12\right)$

$=\underset{l=0}{\overset{M-1}{\max }}({\mathrm{\&Gamma;}}_{k+2}(i,l)+{\mathrm{\&Gamma;}}_{k+1}(l,j))$

More generally, following formula can be expanded to and L is gone on foot forward recursion merge into the single step recursion:

$A_{k+L}={}_L\mathrm{\&Gamma;}_k\&CircleTimes;A_k---\left(13\right)$

Wherein L goes on foot the branch metric matrix _LГ _k(L 〉=2) are defined as:

${}_L\mathrm{\&Gamma;}_k={\mathrm{\&Gamma;}}_{k+L}\&CircleTimes;\&CenterDot;\&CenterDot;\&CenterDot;\&CircleTimes;{\mathrm{\&Gamma;}}_{k+2}\&CircleTimes;{\mathrm{\&Gamma;}}_{k+1}=\underset{i=0}{\overset{L-1}{\mathrm{\&CircleTimes;}}}{\mathrm{\&Gamma;}}_{k+L-i}---\left(14\right)$

By the matrix-vector multiplication on the Max-Sum semi-ring, L is gone on foot forward recursion merge into the single step forward recursion, can be by all branch metrics on asking from k moment state s to k+L moment state s ' mesh wiring _LГ _k(s ', s) and α _k(s) maximum of sum is calculated α _K+L(s ').

General Turbo code interpretation method and device that the present invention proposes have following steps:

Step (1) is with the Input Data Buffer that stores into of the sequence order that receives, and the capacity of Input Data Buffer is two frames, when carrying out frame coding operation, receives the next frame data;

Step (2) control module control address generator produces sequence address, first subcode information position and the check digit sequence that receive in the input data buffer zone are read in the component decoder address in order, simultaneously with the external information in the external information memory also in order the address read in the component decoder, the external information initial value in the external information memory is 0;

Step (3-1) component decoder through type (1) calculates the branch metric of first component code;

${\mathrm{\&gamma;}}_k(s^{\&prime;},s)=\frac{1}{2}{L}_C\underset{l=1}{\overset{m}{\mathrm{\&Sigma;}}}{x}_{\mathrm{kl}}{y}_{\mathrm{kl}}+L^a\left(\mathrm{AB}\right)+\frac{1}{2}{L}_C\underset{l=1}{\overset{w}{\mathrm{\&Sigma;}}}{x}_{\mathrm{kl}}{y}_{\mathrm{kl}}---\left(1\right)$

Wherein m=2 represents the quantity of information bit, and w=2 represents the quantity of check digit, x _KlExpression information bit and check digit, span be+1 ,-1}, L ^a(AB) expression prior information; Four symbol prior informations of duobinary system Turbo code L ^a(AB) calculate by formula (2):

L ^a(00)＝0

L ^a(01)＝L ^e(01) (2)

L ^a(10)＝L ^e(10)

L ^a(11)＝L ^e(11)

And four bit prior informations of traditional binary Turbo code L ^a(AB) calculate by formula (3):

L ^a(00)＝0

L ^a(01)＝L ^e(B)＝L ^e(10) (3)

L ^a(10)＝L ^e(A)＝L ^e(01)

L ^a(11)＝L ^e(A)+L ^e(B)＝L ^e(01)+L ^e(10)

L wherein ^e(u _k) be the external information that the component decoder receives, realize the switching that traditional binary and duobinary system Turbo code prior information are calculated by control module;

Step (3-2) component decoder through type (4) calculates forward state metric, and the mould normalized is adopted to state in the back;

${\mathrm{\&alpha;}}_k\left(s\right)={\underset{s^{\&prime;}\&Element;S}{\max }}^{*}({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k(s^{\&prime;},s))---\left(4\right)$

Step (3-3) component decoder through type (5) calculates the back to state measurement, and adopts the mould normalized; To the metric calculation module, in the time of one of them output valid data, another carries out the calculating of pre-thermal window after adopting two simultaneously;

${\mathrm{\&beta;}}_{k-1}\left(s^{\&prime;}\right)=\underset{s^{\&prime;}\&Element;S}{\max }({\mathrm{\&beta;}}_k\left(s\right)+{\mathrm{\&gamma;}}_k(s^{\&prime;},s))---\left(5\right)$

Step (3-4) component decoder through type (6), (7) compute sign external information, the bit external information is calculated in through type (6), (8); For the duobinary system Turbo code, the is-symbol external information of transmitting, and for the traditional binary Turbo code, what transmit is the bit external information, and each two bit external informations or three shared three data lines of outer symbol information of transmitting are selected bit external information and outer symbol information by two data selectors;

${\mathrm{APP}}^e(u_k=i)=\underset{u_k=i}{\max }({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k^e(s^{\&prime;},s)+{\mathrm{\&beta;}}_k\left(s\right))---\left(6\right)$

APP ^e(u _k=i) expression u _k=i, i ∈ 00,01,10, the probability likelihood ratio of the external information of 11} correspondence;

L ^e(u _k＝00)＝0

L ^e(u _k＝01)＝APP ^e(u _k＝01)-APP ^e(u _k＝00) (7)

L ^e(u _k＝10)＝APP ^e(u _k＝10)-APP ^e(u _k＝00)

L ^e(u _k＝11)＝APP ^e(u _k＝11)-APP ^e(u _k＝00)

L ^e(A)＝max(APP ^e(u _k＝10)，APP ^e(u _k＝11))

-max(APP ^e(u _k＝00)，APP ^e(u _k＝01)) (8)

L ^e(B)＝max(APP ^e(u _k＝01)，APP ^e(u _k＝11))

-max(APP ^e(u _k＝00)，APP ^e(u _k＝10))

Step (4) control module control address generator produces sequence address, and three external information values that step (3-4) is calculated store in the external information memory address in order;

Step (5) control module control address generator produces interleaving address, second subcode information bit and check digit sequence that input is received in the data buffer zone read in the component decoder according to interleaving address, simultaneously the external information in the external information memory are read into the component decoder according to interleaving address;

The branch metric of second component code of step (6) component decoder calculating, forward state metric, back are to state measurement and external information, and concrete grammar and step are with (3-1)～(3-4) identical;

Step (7) control module control address generator produces interleaving address, and three external information values that step (6) is calculated store in the external information memory according to interleaving address, and method is identical with step (5), and once complete iterative decoding finishes;

The bit external information that step (8) component decoder calculates according to step (6) is carried out the iterative decoding arrest of judgement, if do not satisfy the iterative decoding stopping criterion, forwards step (9) to; Otherwise, forward step (10) to; Described iterative decoding stopping criterion is based on the judgement of bit external information;

Step (9) is judged the maximum iteration time whether current iterations equals to preset, if then forward step (10) to, otherwise, then forward step (1) to;

Step (10) is calculated three symbol posterior probability likelihood ratios according to formula (9), will 0, LLR (u _k=1), LLR (u _k=2), LLR (u _k=3) u of maximum posterior probability likelihood ratio correspondence } _kAs decoding output, wherein that 0 correspondence is u _k=0; Control module control address generator produces interleaving address, will decipher the u of coming out _kSequence is written in the output buffer according to interleaving address;

$L(u_k=i)=\underset{u_k=i}{\max }({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k(s^{\&prime;},s)+{\mathrm{\&beta;}}_k\left(s\right))---\left(9\right)$

Step (11) control module control address generator produces sequence address, with the address output in order of the information sequence in the output buffer.

The present invention proposes a kind of general configurable Turbo code decoding scheme that is applicable to traditional binary Turbo code and the decoding of duobinary system Turbo code, well taken into account four indexs of versatility, decoding performance, decoding complexity and resource occupation.

Description of drawings

Fig. 1 is a traditional binary Turbo code decoder forward recursion modular structure;

Fig. 2 is a duobinary system Turbo code decoder forward recursion modular structure;

Fig. 3 is the grid chart of (13,15) component code;

Fig. 4 is the grid chart after merging in two steps of (13,15) component code;

Fig. 5 is general Turbo code decoder The general frame;

Fig. 6 is the component code decoder architecture block diagram in the general Turbo code decoder;

Fig. 7 is the input buffer write operation schematic diagram of general Turbo code decoder;

Fig. 8 is the input buffer read operation schematic diagram of general Turbo code decoder;

Fig. 9 is the branch metric calculation modular structure block diagram in the general Turbo code decoder;

Figure 10 is the state metric calculation modular structure block diagram in the general Turbo code decoder;

Figure 11 is the external information computing module structured flowchart in the general Turbo code decoder;

Figure 12 is general Turbo code decoder external information RAM reading and writing structure chart;

Figure 13 for grid chart merge before and after the error rate of Log-MAP and enhancement mode MAX-Log-MAP algorithm (simulated environment: frame length is 1504,3GPP (15,13) component code encoder, code check 1/2, awgn channel, QPSK modulation, greatest iteration decoding number of times is 8 times, adopts the interleaver of 3GPP standard);

Figure 14 is four tunnel parallel real-time interleaver structure charts of general Turbo code decoder.

Embodiment

The general Turbo code interpretation method that the present invention proposes adopts the Max-log-MAP algorithm of enhancement mode, adopt two step forward directions, backward recursion to calculate to traditional Turbo code decoding and merge into single step forward direction, backward recursion calculating, be about to the state transitions merging of the step of two in traditional Turbo code grid chart and become a step state transitions, make traditional Turbo code and duobinary system Turbo code have identical grid chart structure, thus can be simultaneously to duobinary system and the decoding of traditional binary Turbo code.Traditional Turbo code encoder grid figure of one 8 state as shown in Figure 3, the traditional Turbo code encoder grid figure after merging through grid chart is as shown in Figure 4.

Among the present invention general configurable Turbo code code translator structure as shown in Figure 5, it is by Input Data Buffer, the component code decoder, the external information memory RAM, output data buffer, address generator, controller is formed.In order to reduce resource occupation, reduce energy loss, only use one-component code decoder module.What dotted line was represented among Fig. 5 is the address.General Turbo code code translator adopts corresponding configuration according to different Turbo codes, therefore increases some gating modules and carry out the allotment of intermodule on duobinary system Turbo code code translator.For the duobinary system Turbo code, do not have too big increase on the resource.With respect to the traditional binary Turbo code, have a certain amount of increase on the resource, but, therefore on the memory space that takies the main resource of Turbo code decoder, do not have great increase owing to adopt same sliding window algorithm.Trace increase on the SISO operand and the increase on the control module are compared with the big memory space of Turbo code, almost can ignore.The Resources Consumption of grid chart folding increase has also been brought very big benefit concerning the traditional binary Turbo code in addition.Merge by grid chart, make two bits decipher simultaneously, greatly reduce decoding delay.Increase certain resource, obtain the reduction of decoding delay.

Component decoder in the general Turbo code code translator is a part the most complicated, core, and what its adopted is the sliding window mode, based on the enhancement mode Max-Log-MAP decoding algorithm of symbol, stops iteration decision rule based on bit.The code translator structure as shown in Figure 6, the component code decoder is by the branch metric calculation module, the state metric calculation module, the external information computing module, judgement output judging module, RAM and selector are formed.

General Turbo code interpretation method and device that the present invention proposes have following steps:

Step (1): with the data buffer that stores into of the sequence order that receives.

In order to reduce time delay, the capacity of Input Data Buffer should be designed to the size of two frames, when carrying out frame coding operation, receives the next frame data.

Step (2): control module control address generator produces sequence address, first subcode information position and check digit sequence that input is received in the data buffer zone read in the component decoder address in order, simultaneously with the external information in the external information memory also in order the address read into (the external information initial value in the external information memory is 0) in the component decoder.

For the decoding of traditional binary Turbo code, the read and write operation of input buffer is at each bit, and for the decoding of duobinary system Turbo code, the read and write of input and output buffer operation is at each symbol.The write operation storage principle of input buffer as shown in Figure 7, the read operation principle is as shown in Figure 8.

Step (3-1): the component decoder calculates the branch metric of first component code.

Since the enhancement mode Max-Log-MAP decoding algorithm that decoder adopts, branch metric γ _k(s ', s) be expressed as:

${\mathrm{\&gamma;}}_k(s^{\&prime;},s)=\frac{1}{2}{L}_C\underset{l=1}{\overset{m}{\mathrm{\&Sigma;}}}{x}_{\mathrm{kl}}{y}_{\mathrm{kl}}+L^a\left(\mathrm{AB}\right)+\frac{1}{2}{L}_C\underset{l=1}{\overset{w}{\mathrm{\&Sigma;}}}{x}_{\mathrm{kl}}{y}_{\mathrm{kl}}$

$={\mathrm{\&gamma;}}_k^s(s^{\&prime;},s)+{\mathrm{\&gamma;}}_k^e(s^{\&prime;},s)$

Wherein m=2 represents the quantity of information bit, and w=2 represents the quantity of check digit, x _KlCorresponding to information bit and check digit, span be+1 ,-1}, L ^a(AB) Dai Biao is-symbol prior information.

Four symbol prior informations of duobinary system Turbo code L ^a(AB) calculate by following formula:

L ^a(00)＝0

L ^a(01)＝L ^e(01)

L ^a(10)＝L ^e(10)

L ^a(11)＝L ^e(11)

And to the traditional binary Turbo code, the external information transmission be two bit external information L ^e(A) and L ^eSo four symbol prior informations of traditional binary Turbo code L (B), ^a(AB) calculate by following formula:

L ^a(00)＝0

L ^a(01)＝L ^e(B)＝L ^e(10)

L ^a(10)＝L ^e(A)＝L ^e(01)

L ^a(11)＝L ^e(A)+L ^e(B)＝L ^e(01)+L ^e(10)

L wherein ^e(u _k) be the external information that the component decoder receives, realize the switching that traditional binary and duobinary system Turbo code prior information are calculated by control module;

For each moment k branch metric γ _k(s ', s) there are 32, two registers need 64 memory space stores branch tolerance altogether.Examine and to find γ _k ^s(s ', s) have only 4 kinds of possible values for two component code decoders, relevant with information symbol.And γ _k ^e(s ', s) also have only 4 kinds of possible values for each component code decoder, relevant with check digit, two component code decoders just have only 8 kinds of possible values.If therefore only store γ at each moment k _k ^s(s ', s) and γ _k ^e(s ', s) just only need 12 memory spaces to get final product, this will save more space than direct stores branch tolerance.

To γ _k ^s(s ', s) and γ _k ^e(s ', need calculate in real time according to grid chart when s) selecting.In fact, we only need to calculate a relative γ _k ^s(s ', s) and γ _k ^e(s ', s):

${\stackrel{\&OverBar;}{\mathrm{\&gamma;}}}_k^s(s^{\&prime;},s)={\mathrm{\&gamma;}}_k^s(s^{\&prime;},s)-{\mathrm{\&gamma;}}_k^s{(s^{\&prime;},s)}_{u_{\mathrm{ka}}{u}_{\mathrm{kb}}=00}$

${\stackrel{\&OverBar;}{\mathrm{\&gamma;}}}_k^e(s^{\&prime;},s)={\mathrm{\&gamma;}}_k^e(s^{\&prime;},s)-{\mathrm{\&gamma;}}_k^e{(s^{\&prime;},s)}_{p_{\mathrm{ky}}{p}_{\mathrm{kw}}=00}$

Therefore for two component code decoder γ _k ^s(s ', s) only need 3 numerical value of storage, γ _k ^e(s ', s) only need 6 numerical value of storage to get final product.The computing module structure as shown in Figure 9.Represented the joint account of traditional binary Turbo code in the frame of broken lines.Can realize the switching of traditional binary and duobinary system Turbo code by the options of control module change selector.

Step (3-2): the component decoder calculates the forward state metric of first component code.

According to the forward state metric calculation formula, can release:

${\mathrm{\&alpha;}}_k\left(s\right)={\underset{s^{\&prime;}\&Element;S}{\max }}^{*}({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k(s^{\&prime;},s))$

$\&DoubleLeftRightArrow;{\underset{s^{\&prime;}\&Element;S}{\max }}^{*}({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k^s(s^{\&prime;},s)+{\mathrm{\&gamma;}}_k^e(s^{\&prime;},s))$

$\&DoubleLeftRightArrow;{\underset{s^{\&prime;}\&Element;S}{\max }}^{*}({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k^s(s^{\&prime;},s)-{\mathrm{\&gamma;}}_k^s{(s^{\&prime;},s)}_{u_{\mathrm{ka}}{u}_{\mathrm{kb}}=00}+{\mathrm{\&gamma;}}_k^e(s^{\&prime;},s)-{\mathrm{\&gamma;}}_k^e{(s^{\&prime;},s)}_{p_{\mathrm{ky}}{p}_{\mathrm{kw}}=00})$

$\&DoubleLeftRightArrow;{\underset{s^{\&prime;}\&Element;S}{\max }}^{*}({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\stackrel{\&OverBar;}{\mathrm{\&gamma;}}}_k^s(s^{\&prime;},s)+{\stackrel{\&OverBar;}{\mathrm{\&gamma;}}}_k^e(s^{\&prime;},s))$

The forward state metric calculation module is the recursion structure just, and the forward state metric structure as shown in figure 10.Because what general decoder all adopted is the grid chart of 8 states, so is one 8 on the output state tolerance bus and selects 1 selector.Thick line among the figure represents it is one group of data, selects correspondingly data to be input among the ACS according to selector and goes.Each basic module can be finished in a clock cycle among Figure 10, reduces decoding delay greatly.The input of each ACS all is three inputs among the figure, and corresponding addition is exactly a three-input adder.Forward state metric calculation adopts the mould normalized.

Step (3-3): the component decoder calculates the back to state measurement of first component code.

β _k(s) structure and α _k(s) similar substantially, but, as shown in Figure 6, two β are arranged because what adopt is the sliding window algorithm _k(s) computing module, one of them β _kWhen (s) exporting valid data, another β _k(s) computing module carries out the calculating of pre-thermal window, reduces the wait of pre-thermal window like this by the mode that increases module, reduces time-delay.By the mould normalized, can omit the normalization module, simplify the calculating of state measurement, the calculating of acceleration mode tolerance.

Step (3-4): the component decoder calculates the outer symbol information and the bit external information of first component code respectively by following three formulas:

${\mathrm{APP}}^e(u_k=i)=\underset{u_k=i}{\max }({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k^e(s^{\&prime;},s)+{\mathrm{\&beta;}}_k\left(s\right))$

APP ^e(u _k=i) expression u _kI, i ∈ 00,01,10, the probability likelihood ratio of the external information of 11} correspondence;

L ^e(u _k＝00)＝0

L ^e(u _k＝01)＝APP ^e(u _k＝01)-APP ^e(u _k＝00)

L ^e(u _k＝10)＝APP ^e(u _k＝10)-APP ^e(u _k＝00)

L ^e(u _k＝11)＝APP ^e(u _k＝11)-APP ^e(u _k＝00)

L ^e(A)＝max(APP ^e(u _k＝10)，APP ^e(u _k＝11))

-max(APP ^e(u _k＝00)，APP ^e(u _k＝01))

L ^e(B)＝max(APP ^e(u _k＝01)，APP ^e(u _k＝11))

-max(APP ^e(u _k＝00)，APP ^e(u _k＝10))

For the duobinary system Turbo code, the is-symbol external information of transmitting, and for the traditional binary Turbo code, what transmit is the bit external information, and each two bit external informations or three shared three data lines of outer symbol information of transmitting are selected bit external information and outer symbol information by two data selectors.

External information L ^e(u _k=i) computing module structure as shown in figure 11.Wherein on behalf of the extra bit external information of traditional binary Turbo code, the empty frame in the right calculate.And we only need get final product by transmitting three external informations after the simple subtraction for the duobinary system Turbo code.The empty frame table on the left side shows the computing module of external information probability, and is similar in input mode and the state measurement, adopts selector to select input.Owing to adopt enhancement mode Max-Log-MAP algorithm, therefore Fig. 6 can see external information the output termination multiply by the process of verification factor sf.Sf gets 0.75 in the reality, only need be shifted and can realize from adding by displacement.No matter last point is owing to be to decipher to the traditional binary Turbo code or to the duobinary system Turbo code, the external information transmission all is public three data wires, therefore also needs two data selectors that bit external information and outer symbol information are selected.

Step (4): control module control address generator produces sequence address, and three external information values that step (3-4) is calculated store in the external information memory address in order.

The external information memory as shown in figure 12.For the decoding of traditional Turbo code, owing to interweave and deinterleaving is not that each symbol after merging at grid carries out, but carry out, so external information RAM storage is the external information of bit at each bit.No longer distinguishing among the external information RAM is A bit or B bit, and two bit external informations promptly deciphering out simultaneously in external information RAM are not carried out the cluster storage.What subscript was represented is that the bit external information is stored in the position among the external information RAM.Same when from external information RAM, reading the bit external information when, once from RAM, read two bit external informations according to two bit addresses of interleaver generation; For duobinary system Turbo code decoding because interweave and deinterleaving at each symbol, so is-symbol external information of external information RAM storage.Three outer symbol information of each symbol are the cluster storages.What subscript was represented is the relative position of this symbol in external information RAM.Same when from external information RAM, reading outer symbol information when, read three outer symbol information according to a symbolic address of interleaver generation is once continuous from RAM.Two bit external informations or three outer symbol information of being noted that each transmission at last are shared three data lines, need controller that the data that write or read are selected before the storage.

Step (5): control module control address generator produces interleaving address, second subcode information bit and check digit sequence that input is received in the data buffer zone read in the component decoder according to interleaving address, simultaneously the external information in the external information memory are also read in the component decoder according to interleaving address.

Step (6-1): the component decoder calculates the branch metric of second component code.

Step (6-2): the component decoder calculates the forward state metric of second component code.

Step (6.3): the component decoder calculates the back to state measurement of second component code.

Step (6-4): the component decoder calculates the symbol and the bit external information of second component code.

The method of step (6-1)～(6-4) is the same with step with (3-1)～(3-4).

Step (7): control module control address generator produces interleaving address, and step (6-4) is stored in the external information memory according to interleaving address through three external information values after selecting.In the same step of its method (5) is the same.This moment, once complete iterative decoding finished.

Step (8): the bit external information that the component decoder calculates according to step (6-4) is carried out the iteration stopping judgement.Because in step (6-4), no matter be duobinary system or traditional binary Turbo code, all calculated their bit external information, so the iteration stopping criterion adopt based on bit the arrest of judgement method.If stopping criterion does not satisfy, forward step (9) to; Otherwise stop iteration, forward step (10) to.

Step (9): judge the maximum iteration time whether current iterations equals to preset, if then forward step (10) to; Otherwise, then forward step (1) to.

Step (10) is calculated three symbol posterior probability likelihood ratios according to following formula, will 0, LLR (u _k=1), LLR (u _k=2), LLR (u _k=3) u of maximum posterior probability likelihood ratio correspondence } _kAs decoding output, wherein that 0 correspondence is u _k=0; Control module control address generator produces interleaving address, will decipher the u of coming out _kSequence is written in the output buffer according to interleaving address;

$L(u_k=i)=\underset{u_k=i}{\max }({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k(s^{\&prime;},s)+{\mathrm{\&beta;}}_k\left(s\right))$

$=\underset{u_k=i}{\max }({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k^e(s^{\&prime;},s)+{\mathrm{\&gamma;}}_k^s(s^{\&prime;},s)+{\mathrm{\&beta;}}_k\left(s\right))$

$={\mathrm{\&gamma;}}_k^s(u_k=i)+\underset{u_k=i}{\max }({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k^e(s^{\&prime;},s)+{\mathrm{\&beta;}}_k\left(s\right))$

$={\mathrm{\&gamma;}}_k^s(u_k=i)+L^e(u_k=i)$

Step (11): control module control address generator produces sequence address, with the address output in order of the information sequence in the output buffer.

With existing hardware technology, the floating-point of Turbo code decoding realizes it being almost impossible, therefore adopts fixed-point calculation here.Find by emulation, adopt the decoding architecture of duobinary system Turbo code, input The data 5bit quantizes, and branch metric adopts 8bit, state measurement adopts 9bit, and the fixed point under the external information employing 8bit quantification quantizes can obtain the performance of approaching and floating-point emulation.

Here providing a traditional binary Turbo code analogous diagram and an experimental result that is suitable for the general decoding method of the present invention's proposition compares.Figure 13 is a frame length 1504,3GPP (15,13) component code encoder, the error rate of Log-MAP and enhancement mode MAX-Log-MAP algorithm before and after traditional Turbo code grid chart of code check 1/2 merges, simulated environment adopts awgn channel, the QPSK modulation, and greatest iteration decoding number of times is 8 times, the interleaver of 3GPP standard, the structure chart of interleaver as shown in figure 14.

As shown in figure 13 when low signal-to-noise ratio, under the Log-MAP algorithm, the performance that two steps merged is than the decreased performance of nonjoinder 0.04dB only, and enhancement mode MAX-Log-MAP algorithm, decreased performance is still less.And in the high s/n ratio zone, the performance under four kinds of conditions does not almost have difference.What the reason of decreased performance was that above-mentioned derivation uses is the max-sum semi-ring, does not add correction term.Tradition Turbo code complexity is more as shown in table 1.

In sum, based on symbol and based on the bit stopping criterion increasing under the few situation of resource, can both obtain well to stop effect.

The realization result relatively

Operand relatively before and after table 1 grid chart merged

Turbo code after traditional binary Turbo code grid chart merges

Add operation comparison operation add operation comparison operation

γ _k(s’，s) 10 0 26 0

α _k(s) 32 16 32 24

β _k(s) 32 16 32 24

L(u _k) 66 28 66 32

Once decipher two bits because grid chart merges, therefore reasonably manner of comparison is that the operand of two bits of traditional binary Turbo code is added up, and the operand after merging with grid chart more relatively.Table 1 is per two the bit operands statistics of following each the component decoder of two kinds of methods of 8 states.

The basic module of traditional binary Turbo code state measurement only needs an ACSO module, and the basic module of the traditional binary Turbo code state measurement after the grid chart merging equally needs two ACSO modules to add a CSO module with duobinary system Turbo, so the resource of SISO computing module has increased by one times.And as can be seen from Table 1, in fact, from the operand angle, the operand increase seldom before and after grid chart merged.

Claims (1)

1, traditional binary and duobinary system Turbo code general decoding method is characterized in that the concrete steps of this method comprise:

Step (1) is with the Input Data Buffer that stores into of the sequence order that receives, and the capacity of Input Data Buffer is two frames, when carrying out frame coding operation, receives the next frame data;

Step (2) control module control address generator produces sequence address, first subcode information position and the check digit sequence that receive in the input data buffer zone are read in the component decoder address in order, simultaneously with the external information in the external information memory also in order the address read in the component decoder, the external information initial value in the external information memory is 0;

Step (3-1) component decoder through type (1) calculates the branch metric of first component code;

${\mathrm{\&gamma;}}_k(s^{\&prime;},s)=\frac{1}{2}{L}_C\underset{l=1}{\overset{m}{\mathrm{\&Sigma;}}}{x}_{\mathrm{kl}}{y}_{\mathrm{kl}}+L^a\left(\mathrm{AB}\right)+\frac{1}{2}{L}_C\underset{l=1}{\overset{w}{\mathrm{\&Sigma;}}}{x}_{\mathrm{kl}}{y}_{\mathrm{kl}}---\left(1\right)$

Wherein m=2 represents the quantity of information bit, and w=2 represents the quantity of check digit, x _KlExpression information bit and check digit, span be+1 ,-1}, L ^a(AB) expression prior information; Four symbol prior informations of duobinary system Turbo code L ^a(AB) calculate by formula (2):

L ^a(00)＝0

L ^a(01)＝L ^e(01) (2)

L ^a(10)＝L ^e(10)

L ^a(11)＝L ^e(11)

And four bit prior informations of traditional binary Turbo code L ^a(AB) calculate by formula (3):

L ^a(00)＝0

L ^a(01)＝L ^e(B)＝L ^e(10) (3)

L ^a(10)＝L ^e(A)＝L ^e(01)

L ^a(11)＝L ^e(A)+L ^e(B)＝L ^e(01)+L ^e(10)

L wherein ^e(u _k) be the external information that the component decoder receives, realize the switching that traditional binary and duobinary system Turbo code prior information are calculated by control module;

Step (3-2) component decoder through type (4) calculates forward state metric, and the mould normalized is adopted to state in the back;

${\mathrm{\&alpha;}}_k\left(s\right)={\underset{s^{\&prime;}\&Element;S}{\max }}^{*}({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k(s^{\&prime;},s))---\left(4\right)$

Step (3-3) component decoder through type (5) calculates the back to state measurement, and adopts the mould normalized; To the metric calculation module, in the time of one of them output valid data, another carries out the calculating of pre-thermal window after adopting two simultaneously;

${\mathrm{\&beta;}}_{k-1}\left(s^{\&prime;}\right)=\underset{s^{\&prime;}\&Element;S}{\max }({\mathrm{\&beta;}}_k\left(s\right)+{\mathrm{\&gamma;}}_k(s^{\&prime;},s))---\left(5\right)$

Step (3-4) component decoder through type (6), (7) compute sign external information, the bit external information is calculated in through type (6), (8); For the duobinary system Turbo code, the is-symbol external information of transmitting, and for the traditional binary Turbo code, what transmit is the bit external information, and each two bit external informations or three shared three data lines of outer symbol information of transmitting are selected bit external information and outer symbol information by two data selectors;

${\mathrm{APP}}^e(u_k=i)=\underset{u_k=i}{\max }({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k^e(s^{\&prime;},s)+{\mathrm{\&beta;}}_k\left(s\right))---\left(6\right)$

APP ^e(u _k=i) expression u _k=i, i ∈ 00,01,10, the probability likelihood ratio of the external information of 11} correspondence;

L ^e(u _k＝00)＝0

L ^e(u _k＝01)＝APP ^e(u _k＝01)-APP ^e(u _k＝00) (7)

L ^e(u _k＝10)＝APP ^e(u _k＝10)-APP ^e(u _k＝00)

L ^e(u _k＝11)＝APP ^e(u _k＝11)-APP ^e(u _k＝00)

L ^e(A)＝max(APP ^e(u _k＝10)，APP ^e(u _k＝11))

-max(APP ^e(u _k＝00)，APP ^e(u _k＝01)) (8)

L ^e(B)＝max(APP ^e(u _k＝01)，APP ^e(u _k＝11))

-max(APP ^e(u _k＝00)，APP ^e(u _k＝10))

Step (4) control module control address generator produces sequence address, and three external information values that step (3-4) is calculated store in the external information memory address in order;

Step (5) control module control address generator produces interleaving address, second subcode information bit and check digit sequence that input is received in the data buffer zone read in the component decoder according to interleaving address, simultaneously the external information in the external information memory are read into the component decoder according to interleaving address;

The branch metric of second component code of step (6) component decoder calculating, forward state metric, back are to state measurement and external information, and concrete grammar and step are with (3-1)～(3-4) identical;

Step (7) control module control address generator produces interleaving address, and step (6) is stored in the external information memory according to interleaving address through three external information values after selecting, and method is identical with step (5), and once complete iterative decoding finishes;

The bit external information that step (8) component decoder calculates according to step (6) is carried out the iterative decoding arrest of judgement, if do not satisfy the iterative decoding stopping criterion, forwards step (9) to; Otherwise, forward step (10) to; Described iterative decoding stopping criterion is based on the judgement of bit external information;

Step (9) is judged the maximum iteration time whether current iterations equals to preset, if then forward step (10) to, otherwise, then forward step (1) to;

Step (10) is calculated three symbol posterior probability likelihood ratios according to formula (9), will 0,

LLR (u _k=1), LLR (u _k=2), LLR (u _k=3) u of maximum posterior probability likelihood ratio correspondence } _kAs decoding output, wherein that 0 correspondence is u _k=0; Control module control address generator produces interleaving address, will decipher the u of coming out _kSequence is written in the output buffer according to interleaving address;

$L(u_k=i)=\underset{u_k=i}{\max }({\mathrm{\&alpha;}}_{k-1}\left(s^{\&prime;}\right)+{\mathrm{\&gamma;}}_k(s^{\&prime;},s)+{\mathrm{\&beta;}}_k\left(s\right))---\left(9\right)$

Step (11) control module control address generator produces sequence address, with the address output in order of the information sequence in the output buffer.

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