CN113113500B - Preparation method of full-angle light trapping suede and crystalline silicon solar cell - Google Patents
Preparation method of full-angle light trapping suede and crystalline silicon solar cell Download PDFInfo
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- 229910021419 crystalline silicon Inorganic materials 0.000 title claims abstract description 18
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- 239000000243 solution Substances 0.000 claims description 10
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- 229910021641 deionized water Inorganic materials 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- -1 fluorine ions Chemical class 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
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- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 229910002651 NO3 Inorganic materials 0.000 claims description 3
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 claims description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 17
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a preparation method of a full-angle light trapping suede and a crystalline silicon solar cell, wherein the preparation method of the full-angle light trapping suede comprises the following steps: s1, forming a regular pyramid structured suede on the surface of the monocrystalline silicon wafer by adopting an alkali etching texturing process; s2, depositing a dielectric layer on the surface of the textured monocrystalline silicon wafer; s3, depositing metal nanoparticles on the surface of the dielectric layer by adopting a wet deposition process; s4, modifying the metal nanoparticles by adopting an annealing process to form metal mask particles; s5, performing plasma etching on the dielectric layer on the surface of the monocrystalline silicon wafer by adopting a plasma etching process and taking the metal mask particles as a mask; and S6, removing residual metal mask particles on the surface of the dielectric layer to form a full-angle light trapping suede. According to the invention, the uniform full-angle light trapping micro-nano composite textured surface can be prepared on the silicon wafer with the textured surface with the regular pyramid structure in a way of etching the medium layer by using the plasma, so that the photoelectric conversion efficiency of the solar cell is improved.
Description
Technical Field
The invention belongs to the technical field of crystalline silicon solar cells, and particularly relates to a full-angle light trapping suede and a preparation method of a crystalline silicon solar cell.
Background
The crystalline silicon solar cell has the characteristics of low cost, high photoelectric conversion efficiency and high stability, so that the crystalline silicon solar cell is the mainstream solar cell in the market at present. In recent years, with the market having higher requirements on the efficiency and appearance of the crystalline silicon solar cell, how to improve the photoelectric conversion efficiency and solve the influence of appearance "color difference" becomes a problem to be solved at present.
Single crystal solar cells have become the mainstream crystalline silicon cells in the market over the years of polycrystalline solar cells, mainly due to their reduced cost and relatively high photoelectric conversion efficiency. At present, a reflection reducing texture (a positive pyramid texture) on the surface of a single crystal solar cell on a production line is mainly formed by anisotropic alkali etching through a two-step method, and the surface reflectivity is about 11%. Although the regular pyramid suede can effectively absorb light vertically incident to the surface of the solar cell, the regular pyramid suede can generate a 'reflecting' phenomenon at a specific angle due to higher side surface reflectivity. This not only results in a low light utilization rate of the solar cell, but also brings about the effect of "color difference" in visual angle. When the solar cell module generates electricity outdoors, the utilization rate of the solar cell module to light is low in the early morning and evening, and the generated energy is reduced; and secondly, the aesthetics of the battery pack is affected.
At present, in order to solve the problem of lateral luminescence of a positive pyramid textured surface of a single crystal solar cell, most reports show that the problem can be solved by preparing a nano pyramid, pit and nanowire or pyramid and nanowire micro-nano composite textured surface on the surface of a silicon wafer, but the method inevitably changes the surface morphology of the silicon wafer, increases the specific surface area and leads to surface recombination increase.
Therefore, in order to solve the above technical problems, it is necessary to provide a method for preparing a full-angle light-trapping textured surface and a crystalline silicon solar cell.
Disclosure of Invention
In view of the above, the present invention provides a full-angle light-trapping textured surface and a method for manufacturing a crystalline silicon solar cell, wherein the full-angle light-trapping textured surface is formed on the basis of a silicon wafer surface dielectric layer.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a preparation method of a full-angle light trapping suede comprises the following steps:
s1, forming a regular pyramid structured suede on the surface of the monocrystalline silicon wafer by adopting an alkali etching texturing process;
s2, depositing a dielectric layer on the surface of the textured monocrystalline silicon wafer;
s3, depositing metal nanoparticles on the surface of the dielectric layer by adopting a wet deposition process;
s4, modifying the metal nanoparticles by adopting an annealing process to form metal mask particles;
s5, performing plasma etching on the dielectric layer on the surface of the monocrystalline silicon wafer by adopting a plasma etching process and taking the metal mask particles as a mask;
s6, removing the residual metal mask particles on the surface of the dielectric layer to form a full-angle light trapping suede.
In one embodiment, the dielectric layer comprises SiNx、SiO2、SiOxNy、Al2O3、TiO2One or more of ITO; and/or the thickness of the dielectric layer is 50-300 nm.
In an embodiment, the step S3 specifically includes:
mixing a solution containing fluorine ions and ammonium ions, a nitrate solution containing metal ions and deionized water to obtain a mixed solution;
and (3) putting the monocrystalline silicon wafer deposited with the dielectric layer into the mixed solution, reacting for 20-40 min in a water bath at 70-90 ℃, and uniformly depositing a layer of metal nanoparticles on the surface of the dielectric layer.
In one embodiment, the metal nanoparticles have an average size of 5 to 10nm and an average distance of 10 to 50 nm.
In an embodiment, the step S4 is specifically:
and annealing the monocrystalline silicon wafer deposited with the metal nano particles in an air atmosphere, starting at room temperature, raising the temperature to 200 ℃ at a speed of 2-4 ℃/min, keeping the temperature for 10-30 min, and naturally cooling to the room temperature.
In one embodiment, the average size of the metal mask particles is 50-100 nm, and the average spacing is 100-500 nm.
In an embodiment, the step S5 specifically includes:
putting a monocrystalline silicon wafer into a capacitive coupling plasma generating device, and vacuumizing;
taking metal mask particles as a mask, carrying out plasma etching on a dielectric layer on the surface of the monocrystalline silicon piece, and taking discharge gas asAr and SF6Ar and SF6The flow ratio of (A) is 2: 3-4: 1, the reaction pressure is 1-5 Pa, the radio frequency is 13.56-40.68 MHz, the radio frequency power is 80-100W, the bias voltage is-300-200V, and the discharge time is 1-5 min.
In an embodiment, the step S6 specifically includes:
and (3) placing the monocrystalline silicon wafer etched by the plasma into a mixed solution of nitric acid and deionized water for ultrasonic reaction, and removing residual metal mask particles on the surface of the dielectric layer.
In one embodiment, the step S1 further includes:
carrying out phosphorus diffusion on the monocrystalline silicon wafer with the positive pyramid structure texture surface to prepare a PN junction;
and etching to remove the edge region and/or the back PSG layer.
The technical scheme provided by another embodiment of the invention is as follows:
a preparation method of a crystalline silicon solar cell comprises the following steps:
and processing the monocrystalline silicon wafer with the full-angle light trapping textured surface prepared by the preparation method.
The invention has the following beneficial effects:
according to the invention, a uniform full-angle light trapping micro-nano composite textured surface can be prepared on a silicon wafer with a textured surface with a regular pyramid structure in a way of etching a dielectric layer by using plasma;
the full-angle light trapping suede can effectively solve the problem of light reflection on the side face of the monocrystalline silicon wafer, fully utilizes sunlight on the premise of keeping the good passivation effect of the original dielectric layer on the silicon wafer without damaging the internal structure of the silicon wafer, improves the photoelectric conversion efficiency of the solar cell, and has important reference and utilization values for the current crystalline silicon solar cell production line.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic flow chart of a method for preparing a full-angle light-trapping suede surface according to the present invention;
FIG. 2 is a process flow diagram of the method for preparing the full-angle light trapping textured surface of the invention;
FIG. 3 is an SEM image of a silicon nitride dielectric layer on a surface of a silicon wafer in accordance with one embodiment of the present invention;
FIG. 4 is an SEM image of Ag nanoparticles on the surface of silicon nitride before annealing in an embodiment of the invention;
FIG. 5 is an SEM image of annealed silicon nitride surface Ag mask particles in accordance with one embodiment of the present invention;
FIG. 6 is an SEM image of a full-angle light trapping textured surface of the surface of a final monocrystalline silicon wafer in an embodiment of the present invention;
FIG. 7 is an SEM image of a full-angle light-trapping textured section on the surface of a final single-crystal silicon wafer in an embodiment of the invention.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 and fig. 2, the invention discloses a method for preparing a full-angle light trapping suede, which comprises the following steps:
s1, forming a regular pyramid structured suede on the surface of the monocrystalline silicon wafer by adopting an alkali etching texturing process;
s2, depositing a dielectric layer on the surface of the textured monocrystalline silicon wafer;
s3, depositing metal nanoparticles on the surface of the dielectric layer by adopting a wet deposition process;
s4, modifying the metal nanoparticles by adopting an annealing process to form metal mask particles;
s5, performing plasma etching on the dielectric layer on the surface of the monocrystalline silicon wafer by adopting a plasma etching process and taking the metal mask particles as a mask;
s6, removing the residual metal mask particles on the surface of the dielectric layer to form a full-angle light trapping suede.
Wherein the dielectric layer comprises SiNx、SiO2、SiOxNy、Al2O3、TiO2One or more of ITO, etc.; the thickness of the dielectric layer is 50-300 nm.
The step S3 is specifically:
mixing a solution containing fluorine ions and ammonium ions, a nitrate solution containing metal ions and deionized water to obtain a mixed solution;
and (3) putting the monocrystalline silicon wafer deposited with the dielectric layer into the mixed solution, reacting for 20-40 min in a water bath at 70-90 ℃, and uniformly depositing a layer of metal nanoparticles on the surface of the dielectric layer.
Wherein the average size range of the metal nano particles is 5-10 nm, and the average distance is 10-50 nm.
The step S4 is specifically:
and annealing the monocrystalline silicon wafer deposited with the metal nano particles in an air atmosphere, starting at room temperature, raising the temperature to 200 ℃ at a speed of 2-4 ℃/min, keeping the temperature for 10-30 min, and naturally cooling to the room temperature.
Wherein the average size range of the metal mask particles is 50-100 nm, and the average distance is 100-500 nm.
The step S5 is specifically:
putting a monocrystalline silicon wafer into a capacitive coupling plasma generating device, and vacuumizing;
taking metal mask particles as a mask, carrying out plasma etching on a dielectric layer on the surface of the monocrystalline silicon piece, wherein discharge gas is Ar and SF6Ar and SF6The flow ratio of (1) to (2: 3) - (4: 1), the reaction pressure of 1-5 Pa, the radio frequency of 13.56-40.68 MHz,the RF power is 80-100W, the bias voltage is-300 to-200V, and the discharge time is 1-5 min.
The step S6 is specifically:
and (3) placing the monocrystalline silicon wafer etched by the plasma into a mixed solution of nitric acid and deionized water for ultrasonic reaction, and removing residual metal mask particles on the surface of the dielectric layer.
Further, step S1 further includes:
carrying out phosphorus diffusion on the monocrystalline silicon wafer with the positive pyramid structure texture surface to prepare a PN junction;
and etching to remove the edge region and/or the back PSG layer.
The invention also discloses a preparation method of the crystalline silicon solar cell, which comprises the following steps:
and processing the monocrystalline silicon wafer with the full-angle light trapping textured surface prepared by the preparation method.
The present invention is further illustrated by the following specific examples.
The preparation method of the full-angle light-trapping suede in the embodiment specifically comprises the following steps:
1. forming a positive pyramid structure suede on the surface of a monocrystalline silicon wafer by adopting an alkali etching texturing process
The experiment adopts a p-type monocrystalline silicon wafer, the size is 157mm by 157mm, the thickness is 175um, and the resistivity is 0.5-2.0 omega cm.
Firstly, the silicon wafer is cleaned by RCA to remove dust, impurities and the like on the surface so as to clean the surface, and then the cleaned silicon wafer is put into an alkali texturing groove to be etched on the surface to form a positive pyramid structured textured surface, so that the silicon wafer can more fully absorb and utilize sunlight.
2. And depositing a dielectric layer on the surface of the textured monocrystalline silicon wafer.
And then, carrying out phosphorus diffusion on the silicon wafer with the manufactured regular pyramid structure suede to form a PN junction, and then carrying out etching to remove the edge region and the back PSG layer. And finally, depositing a silicon nitride medium layer with the thickness of 300nm on the surface of the pretreated monocrystalline silicon wafer in a PECVD mode, and using the silicon nitride medium layer as a subsequent sample.
Referring to fig. 3, which is an SEM image of the silicon nitride dielectric layer on the surface of the silicon wafer, it can be seen that the silicon nitride layer is well contacted with the silicon wafer and still has a regular pyramid shape as a whole.
3. And depositing metal nano particles on the surface of the dielectric layer by adopting a wet deposition process.
Placing a monocrystalline silicon wafer covered with a-300 nm silicon nitride dielectric layer into NH with the mass fraction of 1%4F. AgNO with mass fraction of 1%3And reacting in a mixed solution of deionized water for 30min in a water bath at 80 ℃, and uniformly depositing a layer of Ag nano particles on the surface of the silicon nitride, wherein the average size range of the Ag nano particles is 5-10 nm, and the average distance is 10-50 nm. The color of the whole monocrystalline silicon wafer surface is transited from dark purple to green.
Referring to fig. 4, which is an SEM image of Ag nanoparticles on the surface of silicon nitride before annealing, it can be seen that the Ag nanoparticles are uniformly distributed on the surface of silicon nitride, and the phenomenon of "tower tip aggregation, two-side sparseness" is not formed.
4. And modifying the metal nanoparticles by adopting an annealing process to form metal mask particles.
And (3) putting the monocrystalline silicon wafer attached with the Ag nano particles into an air box type annealing furnace, annealing in the air atmosphere, starting at the room temperature of 25 ℃, then raising the temperature to 200 ℃ at the speed of 3 ℃/min, keeping the temperature for 15min, and then naturally cooling to form Ag mask particles. The process aims to modify Ag nano particles which just grow on the silicon nitride surface to reach the required mask particle size, the average size range of the Ag mask particles after the mask particles are retreated is 50-100 nm, and the average distance is 100-500 nm.
Referring to fig. 5, which is an SEM image of Ag mask particles on the surface of silicon nitride after annealing, it can be seen that the size and spacing of the Ag mask particles after annealing are larger than those of the Ag nanoparticles before annealing.
5. And performing plasma etching on the dielectric layer on the surface of the monocrystalline silicon wafer by adopting a plasma etching process and taking the metal mask particles as a mask.
In the embodiment, the plasma etching adopts a capacitive coupling plasma generating device.
First uncoveringAnnealing the sample before placing, closing the cover, vacuumizing by using a mechanical pump and molecular pump combination mode, and vacuumizing to 1 x 10-2Pa or so.
Then Ar and SF with the purity of 99.99 percent are introduced6Gas, Ar and SF6The flow ratio of (2) is 7: and 3, adjusting the pressure to be about 3 Pa. And (3) opening a 13.56MHz power source connected to the lower electrode plate, adjusting the power to about 90W, adjusting the matcher to enable the bias voltage of the lower electrode plate to be about-240V, starting plasma etching, and enabling the discharge time to be about 4 min.
And closing the machine to open the cover and sample after the processing is finished.
6. And removing residual metal mask particles on the surface of the dielectric layer to form a full-angle light trapping suede.
Putting the sample after plasma etching into HNO with the mass fraction of 10%3And reacting the silicon wafer with deionized water mixed solution for 180s under the ultrasonic condition, removing residual Ag mask particles on the surface of the silicon wafer, and drying the cleaned silicon wafer to obtain the monocrystalline silicon wafer with the full-angle light trapping texture surface.
Referring to fig. 6, which is an SEM image of the full-angle light-trapping textured surface on the surface of the final single-crystal silicon wafer, the main direction of etching is along the vertical direction, and due to the presence of the Ag mask particles, the silicon nitride region not covered with the Ag mask particles is etched during the etching process, while the region covered with the Ag mask particles is not etched, so that an uneven pit-like structure is formed.
Referring to FIG. 7, which is an SEM image of a cross section of a final full-angle light trapping suede on the surface of a single crystal silicon wafer, the etched silicon nitride suede is very uniform in distribution and relatively uniform in size, the shape of the silicon nitride suede is similar to that of an inclined triangle, in addition, the silicon wafer is not damaged by the etching process, and secondary influence is avoided. The micro-nano composite silicon nitride textured surface effectively reduces the influence of chromatic aberration under a specific angle of the cell, simultaneously more effectively utilizes sunlight, and greatly improves the attractiveness of the outer surface of the cell.
The method for processing the monocrystalline silicon wafer with the full-angle light trapping suede to prepare the crystalline silicon solar cell is completely the same as the existing crystalline silicon solar cell process, and the details are not repeated here.
According to the technical scheme, the invention has the following advantages:
according to the invention, a uniform full-angle light trapping micro-nano composite textured surface can be prepared on a silicon wafer with a textured surface with a regular pyramid structure in a way of etching a dielectric layer by using plasma;
the full-angle light trapping suede can effectively solve the problem of side reflection of the monocrystalline silicon wafer, fully utilizes sunlight on the premise of keeping the good passivation effect of the original dielectric layer on the silicon wafer and not damaging the internal structure of the silicon wafer, improves the photoelectric conversion efficiency of the solar cell, and has important reference and utilization values for the current crystalline silicon solar cell production line.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present specification describes embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and it is to be understood that all embodiments may be combined as appropriate by one of ordinary skill in the art to form other embodiments as will be apparent to those of skill in the art from the description herein.
Claims (10)
1. A preparation method of a full-angle light trapping suede is characterized by comprising the following steps:
s1, forming a regular pyramid structured suede on the surface of the monocrystalline silicon wafer by adopting an alkali etching texturing process;
s2, depositing a dielectric layer on the surface of the textured monocrystalline silicon wafer;
s3, depositing metal nanoparticles on the surface of the dielectric layer by adopting a wet deposition process;
s4, modifying the metal nanoparticles by adopting an annealing process to form metal mask particles;
s5, performing plasma etching on the dielectric layer on the surface of the monocrystalline silicon wafer by adopting a plasma etching process and taking the metal mask particles as a mask;
and S6, removing residual metal mask particles on the surface of the dielectric layer to form a full-angle light trapping suede.
2. The method of claim 1, wherein the dielectric layer comprises SiNx、SiO2、SiOxNy、Al2O3、TiO2One or more of ITO; and/or the thickness of the dielectric layer is 50-300 nm.
3. The preparation method according to claim 1, wherein the step S3 specifically comprises:
mixing a solution containing fluorine ions and ammonium ions, a nitrate solution containing metal ions and deionized water to obtain a mixed solution;
and (3) putting the monocrystalline silicon wafer deposited with the dielectric layer into the mixed solution, reacting for 20-40 min in a water bath at 70-90 ℃, and uniformly depositing a layer of metal nanoparticles on the surface of the dielectric layer.
4. The method of claim 3, wherein the metal nanoparticles have an average size ranging from 5 to 10nm and an average pitch ranging from 10 to 50 nm.
5. The preparation method according to claim 1, wherein the step S4 specifically comprises:
and annealing the monocrystalline silicon wafer deposited with the metal nano particles in an air atmosphere, starting at room temperature, raising the temperature to 200 ℃ at a speed of 2-4 ℃/min, keeping the temperature for 10-30 min, and naturally cooling to the room temperature.
6. The method of claim 5, wherein the metal mask particles have an average size ranging from 50 to 100nm and an average pitch ranging from 100 to 500 nm.
7. The preparation method according to claim 1, wherein the step S5 specifically comprises:
putting a monocrystalline silicon wafer into a capacitive coupling plasma generating device, and vacuumizing;
taking metal mask particles as a mask, carrying out plasma etching on a dielectric layer on the surface of the monocrystalline silicon piece, wherein discharge gas is Ar and SF6Ar and SF6The flow ratio of (A) is 2: 3-4: 1, the reaction pressure is 1-5 Pa, the radio frequency is 13.56-40.68 MHz, the radio frequency power is 80-100W, the bias voltage is-300-200V, and the discharge time is 1-5 min.
8. The preparation method according to claim 1, wherein the step S6 specifically comprises:
and (3) placing the monocrystalline silicon wafer etched by the plasma into a mixed solution of nitric acid and deionized water for ultrasonic reaction, and removing residual metal mask particles on the surface of the dielectric layer.
9. The method for preparing a composite material according to claim 1, wherein the step S1 further includes:
carrying out phosphorus diffusion on the monocrystalline silicon wafer with the positive pyramid structure textured surface to prepare a PN junction;
and etching to remove the edge region and/or the back PSG layer.
10. A preparation method of a crystalline silicon solar cell is characterized by comprising the following steps:
processing a monocrystalline silicon wafer with full-angle light-trapping texture surface prepared by the preparation method according to any one of claims 1 to 9.
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