CN113113071A

CN113113071A - Shifting register unit and driving method thereof, grid driving circuit and display device

Info

Publication number: CN113113071A
Application number: CN202110393249.3A
Authority: CN
Inventors: 杨波; 石领
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-04-13
Filing date: 2021-04-13
Publication date: 2021-07-13

Abstract

The disclosure provides a shift register unit, a driving method thereof, a grid driving circuit and a display device, and belongs to the technical field of display. In the shift register unit, the input circuit can reliably transmit the first power supply signal to the pull-up node only under the control of the starting control end and the first clock end so as to charge the pull-up node. The pull-down control circuit can reliably control the potential of the pull-down node only under the control of the first clock end and the second clock end. Therefore, compared with the related art, each circuit included in the shift register unit provided by the disclosure can normally work only under the control of a small number of control ends, and accordingly, the structure of each circuit can be simpler, which is beneficial to the narrow frame design of the display device.

Description

Shifting register unit and driving method thereof, grid driving circuit and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a driving method thereof, a gate driving circuit, and a display device.

Background

The shift register generally includes a plurality of cascaded shift register units, each of which is coupled to a respective light-emitting control terminal in a row of pixel circuits for providing a light-emitting control signal to the light-emitting control terminal. The pixel circuit can drive the coupled light-emitting element to emit light under the control of the light-emitting control signal.

In the related art, each shift register unit generally includes: the pull-down circuit comprises an input circuit, an output circuit, a pull-down control circuit and a pull-down circuit. The input circuit is used for charging the pull-up node under the control of at least two clock terminals and one power supply terminal. The output circuit is used for outputting a light-emitting control signal to the pixel circuit through the output end under the control of the pull-up node. The pull-down control circuit is used for controlling the potential of the pull-down node under the control of the starting control end, the at least two clock ends and the at least two power end. The pull-down circuit is used for carrying out pull-down noise reduction on the pull-up node and the output end under the control of the pull-down node.

However, in the shift register unit in the related art, some circuits need to be controlled by a large number of control terminals to normally operate, so that the structure of some circuits is complicated, which is not favorable for the narrow frame design of the display device.

Disclosure of Invention

The embodiment of the disclosure provides a shift register unit, a driving method thereof, a gate driving circuit and a display device, which can solve the problem that narrow frame design is not facilitated in the related art. The technical scheme is as follows:

in one aspect, a shift register unit is provided, the shift register unit comprising: the pull-down circuit comprises an input circuit, a pull-down control circuit, a pull-down circuit and an output circuit;

the input circuit is respectively coupled with a first power end, a first clock end, a reference node and a pull-up node, and is used for receiving a starting control signal provided by a starting control end, responding to the starting control signal to control the connection and disconnection of the first power end and the reference node, and responding to a first clock signal provided by the first clock end to control the connection and disconnection of the reference node and the pull-up node;

the pull-down control circuit is respectively coupled with the starting control end, the first clock end, the reference node, the second clock end, the second power end and the pull-down node, and is used for responding to a second clock signal provided by the second clock end, controlling the on-off of the starting control end and the pull-down node, and responding to the potential of the reference node and the first clock signal, controlling the on-off of the second power end and the pull-down node;

the pull-down circuit is respectively coupled with the pull-down node, the first power supply end, the second power supply end, the reference node, the pull-up node and the output end, and is used for responding to the potential of the pull-down node, controlling the connection and disconnection of the second power supply end, the reference node and the pull-up node, and controlling the connection and disconnection of the first power supply end and the output end;

the output circuit is coupled to the pull-up node, the second power end and the output end respectively, and the output circuit is used for responding to the potential of the pull-up node and controlling the connection and disconnection of the second power end and the output end.

Optionally, the pull-down control circuit includes: a first control sub-circuit and a second control sub-circuit;

the first control sub-circuit is respectively coupled with the starting control terminal, the second clock terminal and the pull-down node; the first control sub-circuit is used for responding to the second clock signal and controlling the on-off of the starting control end and the pull-down node;

the second control sub-circuit is coupled to the reference node, the second power supply terminal, the first clock terminal, and the pull-down node, respectively; the second control sub-circuit is used for responding to the potential of the reference node and the first clock signal and controlling the connection and disconnection of the second power supply end and the pull-down node.

Optionally, the first control sub-circuit is further coupled to the first clock terminal, and the first control sub-circuit is further configured to adjust a potential of the pull-down node based on the first clock signal;

the first control sub-circuit comprises: a first pull-down control transistor and a first capacitor; the second control sub-circuit comprises: a second pull-down control transistor and a third pull-down control transistor;

a gate of the first pull-down control transistor is coupled to the second clock terminal, a first pole of the first pull-down control transistor is coupled to the turn-on control terminal, and a second pole of the first pull-down control transistor is coupled to the pull-down node;

a first terminal of the first capacitor is coupled to the first clock terminal, and a second terminal of the first capacitor is coupled to the pull-down node;

a gate of the second pull-down control transistor is coupled to the reference node, a first pole of the second pull-down control transistor is coupled to the second power supply terminal, and a second pole of the second pull-down control transistor is coupled to a first pole of the third pull-down control transistor;

a gate of the third pull-down control transistor is coupled to the first clock terminal, and a second pole of the third pull-down control transistor is coupled to the pull-down node.

Optionally, the pull-down node includes: a first pull-down node and a second pull-down node; the pull-down control circuit further comprises: a third control sub-circuit;

the third control sub-circuit is respectively coupled to a target power supply end, the first pull-down node and the second pull-down node, and is configured to control on/off of the first pull-down node and the second pull-down node in response to a target power supply signal provided by the target power supply end, where the target power supply end is the first power supply end or the second power supply end;

the first control sub-circuit and the second control sub-circuit are both coupled with the first pull-down node, the first control sub-circuit is used for responding to the second clock signal and controlling the connection and disconnection of the starting control end and the first pull-down node, and the second control sub-circuit is used for responding to the potential of the reference node and the first clock signal and controlling the connection and disconnection of the second power end and the first pull-down node;

the pull-down circuit is coupled to the second pull-down node, and the pull-down circuit is configured to control on/off of the second power source end, the reference node and the pull-up node, and control on/off of the first power source end and the output end in response to a potential of the second pull-down node.

Optionally, the third control sub-circuit includes: a fourth pull-down control transistor;

a gate of the fourth pull-down control transistor is coupled to the target power supply terminal, a first pole of the fourth pull-down control transistor is coupled to the first pull-down node, and a second pole of the fourth pull-down control transistor is coupled to the second pull-down node;

wherein if the fourth pull-down control transistor is an N-type transistor, the target power supply terminal is the second power supply terminal, and if the fourth pull-down control transistor is a P-type transistor, the target power supply terminal is the first power supply terminal.

Optionally, the second pull-down node includes: a first child node and a second child node; the second control sub-circuit comprises: a first control unit and a second control unit;

the first control unit is respectively coupled with the reference node, the second power supply end and the first sub-node, and is used for responding to the potential of the reference node and controlling the connection and disconnection of the second power supply end and the first sub-node;

the second control unit is respectively coupled with the first clock end, the first sub-node and the first pull-down node, and is used for responding to the first clock signal and controlling the on-off of the first sub-node and the first pull-down node;

the third control sub-circuit is coupled with the second sub-node and used for responding to the target power supply signal and controlling the connection and disconnection of the first pull-down node and the second sub-node;

the pull-down circuit is respectively coupled with the first sub-node and the second sub-node, and is used for responding to the potential of the first sub-node, controlling the connection and disconnection of the second power supply end with the reference node and the pull-up node, and responding to the potential of the second sub-node, controlling the connection and disconnection of the first power supply end with the output end;

the first control unit is a second pull-down control transistor included in the second control sub-circuit; the second control unit is a third pull-down control transistor included in the second control sub-circuit.

Optionally, the input circuit is further coupled to the pull-down node, and the input circuit is configured to receive the turn-on control signal transmitted to the pull-down node by the pull-down control circuit;

or, the input circuit is further coupled to the start control terminal.

Optionally, the input circuit is further coupled to the second power source terminal, and the input circuit is further configured to adjust the potential of the reference node based on the second power source signal.

Optionally, the input circuit is coupled to the pull-down node; the input circuit includes: a first input sub-circuit and a second input sub-circuit;

the first input sub-circuit is respectively coupled with the pull-down node, the first power supply end, the second power supply end and the reference node, and is used for responding to the potential of the pull-down node, controlling the connection and disconnection of the first power supply end and the reference node, and adjusting the potential of the reference node based on the second power supply signal;

the second input sub-circuit is respectively coupled with the first clock end, the reference node and the pull-up node, and the second input sub-circuit is used for responding to the first clock signal and controlling the connection and disconnection of the reference node and the pull-up node.

Optionally, the first input sub-circuit includes: a first input transistor and a second capacitor; the second input sub-circuit comprises: a second input transistor;

a gate of the first input transistor is coupled to the pull-down node, a first pole of the first input transistor is coupled to the first power supply terminal, and a second pole of the first input transistor is coupled to the reference node;

a first terminal of the second capacitor is coupled to the second power supply terminal, and a second terminal of the second capacitor is coupled to the reference node;

a gate of the second input transistor is coupled to the first clock terminal, a first pole of the second input transistor is coupled to the reference node, and a second pole of the second input transistor is coupled to the pull-up node.

Optionally, the pull-down circuit includes: a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor;

a gate of the first pull-down transistor, a gate of the second pull-down transistor, and a gate of the third pull-down transistor are all coupled to the pull-down node, a first pole of the first pull-down transistor and a first pole of the second pull-down transistor are all coupled to the second power supply terminal, and a first pole of the third pull-down transistor is coupled to the first power supply terminal; a second pole of the first pull-down transistor is coupled to the reference node, a second pole of the second pull-down transistor is coupled to the pull-up node, and a second pole of the third pull-down transistor is coupled to the output.

Optionally, the output circuit includes: an output transistor and a third capacitor;

a gate of the output transistor and a first terminal of the third capacitor are both coupled to the pull-up node, a first pole of the output transistor and a second terminal of the third capacitor are both coupled to the second power supply terminal, and a second pole of the output transistor is coupled to the output terminal.

Optionally, in the input circuit, a first input transistor for controlling on/off of the first power end and the reference node is an N-type transistor;

and in the input circuit, a second input transistor for controlling the connection and disconnection of the reference node and the pull-up node, a pull-down control transistor included in the pull-down control circuit, and a pull-down transistor included in the pull-down circuit and an output transistor included in the output circuit are both P-type transistors.

In another aspect, there is provided a driving method of a shift register unit for driving the shift register unit as described in the above aspect; the method comprises the following steps:

in the first stage, the pull-down control circuit responds to a second clock signal of the first potential to control the conduction of a pull-down node and a starting control end; the pull-down circuit responds to the potential of the pull-down node, controls the second power supply end to be respectively conducted with the pull-up node and the reference node, and controls the first power supply end to be conducted with the output end;

in the second stage, the pull-down circuit responds to the potential of the pull-down node, controls the second power supply end to be respectively conducted with the pull-up node and the reference node, and controls the first power supply end to be conducted with the output end; the input circuit responds to a first clock signal of the first potential and controls the pull-up node and the reference node to be conducted;

in the third stage, the pull-down control circuit responds to a second clock signal of the first potential to control the conduction of the pull-down node and the starting control end; the input circuit responds to a starting control signal of a second potential and controls the first power supply end to be conducted with the reference node;

a fourth stage in which the input circuit controls the first power terminal and the reference node to be turned on in response to a turn-on control signal of the second potential, and controls the reference node and the pull-up node to be turned on in response to a first clock signal of the first potential; the output circuit responds to the electric potential of the pull-up node and controls the second power supply end to be conducted with the output end; the pull-down control circuit responds to the potential of the reference node and a first clock signal of the first potential, and controls the second power supply end to be conducted with the pull-down node;

in the fifth stage, the pull-down control circuit responds to a second clock signal of the first potential to control the conduction of the pull-down node and the starting control end; the input circuit responds to a starting control signal of the second potential and controls the first power supply end to be conducted with the reference node; the output circuit responds to the electric potential of the pull-up node and controls the second power supply end to be conducted with the output end;

and after the fifth stage, executing the fourth stage again, wherein the potential of the starting control signal is a second potential.

In yet another aspect, there is provided a gate driving circuit including: at least two cascaded shift register cells as described in the above aspect.

In still another aspect, there is provided a display device including: a display panel including a plurality of pixel circuits, and the gate driving circuit as described in the above aspect;

the gate driving circuit is coupled to a light emitting control terminal of the pixel circuit, and the gate driving circuit is configured to provide a light emitting control signal to the light emitting control terminal.

The beneficial effect that technical scheme that this disclosure provided brought can include at least:

the embodiment of the disclosure provides a shift register unit, a driving method thereof, a grid driving circuit and a display device. In the shift register unit, the input circuit can reliably transmit the first power supply signal to the pull-up node only under the control of the starting control end and the first clock end so as to charge the pull-up node. The pull-down control circuit can reliably control the potential of the pull-down node only under the control of the first clock end and the second clock end. Therefore, compared with the related art, each circuit included in the shift register unit provided by the embodiment of the disclosure can normally work only under the control of a small number of control ends, and accordingly, the structure of each circuit can be simpler, which is beneficial to the narrow frame design of the display device.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a sub-pixel provided in an embodiment of the present disclosure;

FIG. 2 is a timing diagram of driving a sub-pixel according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure;

FIG. 4 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a shift register unit according to another embodiment of the present disclosure;

FIG. 11 is a schematic structural diagram of a shift register unit according to another embodiment of the present disclosure;

FIG. 12 is a schematic structural diagram of a shift register unit according to another embodiment of the present disclosure;

FIG. 13 is a schematic diagram of a shift register unit according to another embodiment of the present disclosure;

FIG. 14 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure;

FIG. 15 is a schematic diagram of a shift register unit according to another embodiment of the present disclosure;

fig. 16 is a flowchart of a driving method of a shift register unit according to an embodiment of the disclosure;

fig. 17 is a timing diagram of a driving method of a shift register unit according to an embodiment of the disclosure;

FIG. 18 is an equivalent diagram of a shift register unit at a first stage according to an embodiment of the disclosure;

FIG. 19 is an equivalent diagram of a shift register unit at the second stage according to an embodiment of the disclosure;

fig. 20 is an equivalent diagram of a shift register unit at a third stage according to an embodiment of the disclosure;

fig. 21 is an equivalent diagram of a shift register unit at a fourth stage according to an embodiment of the disclosure;

fig. 22 is an equivalent diagram of a shift register unit at a fifth stage according to an embodiment of the disclosure;

FIG. 23 is a simulated timing diagram of each node of a shift register unit according to an embodiment of the present disclosure;

FIG. 24 is a simulated timing diagram of signal terminals of a shift register unit according to an embodiment of the present disclosure;

fig. 25 is a schematic structural diagram of a gate driving circuit according to an embodiment of the disclosure;

fig. 26 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

The display panel generally includes a plurality of sub-pixels. Referring to fig. 1, each sub-pixel may include a pixel circuit 10 and a light emitting element L1 coupled to each other. And the pixel circuit 10 may be further coupled to a GATE signal terminal GATE, a reset signal terminal RST, a light emission control terminal EM, a DATA signal line DATA, a reset signal line Vinit, a driving power supply terminal Vdd, a pull-down power supply terminal Vss, and the like, respectively. The pixel circuit 10 can drive the light emitting element L1 to emit light based on the signal supplied from each signal terminal, the signal supplied from each power source terminal, and the signal supplied from each signal line, which are coupled. In the disclosed embodiments, coupling may refer to electrical connection.

As can be seen from the timing diagram shown in fig. 2, the whole process of driving the light emitting element to emit light may include: a reset phase t01, a data write phase t02, and a light emission phase t 03. In the reset phase t01, the potential of the reset signal provided by the reset signal terminal RST may be an active potential. In the data writing phase t02, the potential of the GATE driving signal provided by the GATE signal terminal GATE may be an effective potential. In the emission period t03, the potential of the emission control signal heard by the emission control terminal EM may include an effective potential.

Since each transistor in the pixel circuit 10 shown in fig. 1 is a P-type transistor, it can be seen from fig. 2 that the effective potential can be a low potential relative to the ineffective potential.

The above signals supplied from the respective signal terminals, the signals supplied from the respective power source terminals, and the signals supplied from the respective signal lines may be supplied from a driver circuit independent of the pixel circuit. The following embodiments of the present disclosure provide a gate driving circuit (which may also be referred to as a screen shift register) for providing a light emitting control signal to a light emitting control terminal. Compared with a gate driving circuit for providing a light emitting control signal in the related art, the structure of each shift register in the gate driving circuit described in the embodiments of the present disclosure is simpler, and the number of thin film transistors included in the gate driving circuit is smaller. Therefore, the voltage loss of the finally transmitted light-emitting control signal can be effectively reduced, the area of the screen (namely, the display panel) required to be occupied can be reduced, and the narrow frame design of the screen is facilitated.

Alternatively, in conjunction with fig. 1, a currently commonly used pixel circuit is a circuit having a 7T1C (i.e., seven transistors M1 and one capacitor C0) structure, but may also have another structure, such as 6T 1C. The embodiments of the present disclosure do not limit this.

Fig. 3 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure. As shown in fig. 3, the shift register unit may include: an input circuit 01, a pull-down control circuit 02, a pull-down circuit 03, and an output circuit 04.

The input circuit 01 may be coupled to the first power source terminal VGL, the first clock terminal CK, the reference node N1, and the pull-up node N2, respectively. The input circuit 01 may be configured to receive a start-up control signal provided by the start-up control terminal STV, and control the connection and disconnection between the first power terminal VGL and the reference node N1 in response to the start-up control signal. And may be used to control the on/off of the reference node N1 and the pull-up node N2 in response to a first clock signal provided by the first clock terminal CK.

For example, the input circuit 01 may control the first power source terminal VGL to be turned on with respect to the reference node N1 when the potential of the turn-on control signal is the second potential, and may control the first power source terminal VGL to be turned off with respect to the reference node N1 when the potential of the turn-on control signal is the first potential. When the first power source terminal VGL is turned on with the reference node N1, the first power source signal provided by the first power source terminal VGL can be transmitted to the reference node N1. The input circuit 01 may control the reference node N1 to be turned on with the pull-up node N2 when the potential of the first clock signal is a first potential, and may control the reference node N1 to be disconnected with the pull-up node N2 when the potential of the first clock signal is a second potential. When the reference node N1 and the pull-up node N2 are turned on, the potential of the reference node N1 is transmitted to the pull-up node N2. Thereby enabling charging of the pull-up node N2.

It should be noted that in the embodiment of the present disclosure, the input circuit 01, the pull-down control circuit 02, the pull-down circuit 03, and the output circuit 04 may each include one or more thin film transistors (hereinafter, referred to as transistors). Wherein, part can be P type transistor, and part can be N type transistor.

In addition, the first potential may be a low potential relative to the second potential, that is, the first potential is smaller than the second potential. And for a P-type transistor, the first potential can be an active potential and the second potential can be an inactive potential. For an N-type transistor, the second potential may be an active potential and the first potential may be an inactive potential.

The pull-down control circuit 02 may be coupled to the turn-on control terminal STV, the first clock terminal CK, the reference node N1, the second clock terminal CB, the second power terminal VGL, and the pull-down node N3, respectively. The pull-down control circuit 02 may be configured to control the on/off of the turn-on control terminal STV and the pull-down node N3 in response to a second clock signal provided from the second clock terminal CB, and may control the on/off of the second power source terminal VGH and the pull-down node N3 in response to the potential of the reference node N1 and the first clock signal.

For example, the pull-down control circuit 02 may control the turn-on control terminal STV to be turned on with the pull-down node N3 when the potential of the second clock signal is the first potential, and may control the turn-on control terminal STV to be turned off with the pull-down node N3 when the potential of the second clock signal is the second potential. When the turn-on control terminal STV is conducted to the pull-down node N3, the turn-on control signal provided by the turn-on control terminal STV can be transmitted to the pull-down node N3. The same is true. The pull-down control circuit 02 may control the second power source terminal VGH to be turned on with the pull-down node N3 when both the potential of the reference node N1 and the potential of the first clock signal are the first potential, and may control the second power source terminal VGH to be turned off with the pull-down node N3 when both the potential of the reference node N1 and/or the potential of the first clock signal are the second potential. When the second power source terminal VGH is turned on with the pull-down node N3, the second power signal provided by the second power source terminal VGH can be transmitted to the pull-down node N3. In this manner, the potential of the pull-down node N3 is controlled. The potential of the second power signal may be a high potential with respect to the potential of the first power signal.

The pull-down circuit 03 may be coupled to the pull-down node N3, the first power source terminal VGL, the second power source terminal VGH, the reference node N1, the pull-up node N2, and the output terminal OUT, respectively. The pull-down circuit 03 may be configured to control the on/off of the second power source terminal VGH with the reference node N1 and the pull-up node N2 and the on/off of the first power source terminal VGL with the output terminal OUT in response to the potential of the pull-down node N3.

For example, the pull-down circuit 03 can control the second power source terminal VGH to be conducted with the reference node N1, the pull-up node N2, and the output terminal OUT when the voltage of the pull-down node N3 is the first voltage. At this time, the second power signal provided from the second power terminal VGH may be transmitted to the reference node N1 and the pull-up node N2, and the first power signal provided from the first power terminal VGL may be transmitted to the output terminal OUT. Thereby realizing the pull-down noise reduction of the reference node N1, the pull-up node N2 and the output terminal OUT. The pull-down circuit 03 may control the second power terminal VGH to be disconnected from the reference node N1, the pull-up node N2, and the first power terminal VGL to be disconnected from the output terminal OUT when the potential of the pull-down node N3 is the second potential.

The output circuit 04 may be coupled to the pull-up node N2, the second power source terminal VGH, and the output terminal OUT, respectively. The output circuit 04 may be configured to control the connection and disconnection between the second power source terminal VGH and the output terminal OUT in response to the potential of the pull-up node N2.

For example, the output circuit 04 may control the second power source terminal VGH to be turned on with the output terminal OUT when the potential of the pull-up node N2 is a first potential, and may control the second power source terminal VGH to be turned off with the output terminal OUT when the potential of the pull-up node N2 is a second potential. When the second power source terminal VGH is turned on with the output terminal OUT, the second power signal provided by the second power source terminal VGH can be transmitted to the output terminal OUT. As can be seen from the above embodiments, the second power signal can be transmitted as an emission control signal to the emission control terminal EM coupled to the pixel circuit shown in fig. 1.

In summary, the embodiments of the present disclosure provide a shift register unit. In the shift register unit, the input circuit can reliably transmit the first power supply signal to the pull-up node only under the control of the starting control end and the first clock end so as to charge the pull-up node. The pull-down control circuit can reliably control the potential of the pull-down node only under the control of the first clock end and the second clock end. Therefore, compared with the related art, each circuit included in the shift register unit can normally work only under the control of a small number of control ends, and accordingly, the structure of each circuit can be simpler, and narrow-frame design of the display device is facilitated.

Fig. 4 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 4, the pull-down control circuit 02 may include: a first control sub-circuit 021 and a second control sub-circuit 022.

The first control sub-circuit 021 may be coupled to the start control terminal STV, the second clock terminal CB, and the pull-down node N3, respectively. The first control sub-circuit 021 may be configured to control on/off of the start control terminal STV and the pull-down node N3 in response to the second clock signal.

For example, the first control sub-circuit 021 may control the turn-on control terminal STV to be turned on with the pull-down node N3 when the potential of the second clock signal is the first potential, and may control the turn-on control terminal STV to be turned off with the pull-down node N3 when the potential of the second clock signal is the second potential.

The second control sub-circuit 022 may be coupled to the reference node N1, the second power source terminal VGH, the first clock terminal CK, and the pull-down node N3, respectively. The second control sub-circuit 022 may be configured to control on and off of the second power source terminal VGH and the pull-down node N3 in response to the potential of the reference node N1 and the first clock signal.

For example, the second control sub-circuit 022 may control the second power source terminal VGH to be turned on with the pull-down node N3 when the potential of the reference node N1 and the potential of the first clock signal are both the first potential, and may control the second power source terminal VGH to be disconnected with the pull-down node N3 when the potential of the reference node N1 is the second potential and/or the potential of the first clock signal is the second potential.

Optionally, as can also be seen with reference to fig. 4, in the embodiment of the present disclosure, the first control sub-circuit 021 may be further coupled to the first clock terminal CK. Based on this, the first control sub-circuit 021 can also adjust the potential of the pull-down node N3 based on the first clock signal. In this manner, the stability of the pull-down node N3 can be ensured.

Optionally, the pull-down node N3 described in the above embodiment may include: a first pull-down node N31 and a second pull-down node N32. Based on this, referring to another shift register unit shown in fig. 5, the pull-down control circuit 02 according to the embodiment of the disclosure may further include: a third control sub-circuit 023.

The third control sub-circuit 023 may be coupled to the target power supply terminal, the first pull-down node N31, and the second pull-down node N32, respectively. The third control sub-circuit 023 may be configured to control the first pull-down node N31 to be turned on or off with the second pull-down node N32 in response to a target power supply signal provided from a target power supply terminal.

For example, the third control sub-circuit 023 may control the first pull-down node N31 and the second pull-down node N32 to be turned on when the potential of the target power supply signal is the first potential, and may control the first pull-down node N31 and the second pull-down node N32 to be turned off when the potential of the target power supply signal is the second potential. When the first pull-down node N31 and the second pull-down node N32 are turned on, the potential of the first pull-down node N31 is transmitted to the second pull-down node N32.

Alternatively, the target power source terminal may be the first power source terminal VGL or the second power source terminal VGH, and the type of the target power source terminal is related to the type of the transistor included in the third control sub-circuit 023. For example, in the structure shown in fig. 5, the target power source terminal is the second power source terminal VGH.

With the third control sub-circuit 023, referring to fig. 5, the pull-down node N3 coupled to the first control sub-circuit 021 may include a first pull-down node N31 and a second pull-down node N32. The pull-down node N3 to which the second control sub-circuit 022 is coupled may be the first pull-down node N31. The pull-down node N3 coupled to the pull-down circuit 03 is a second pull-down node N32.

As can be seen, for the structure shown in fig. 5, the first control sub-circuit 021 can be used for controlling the on/off of the start control terminal STV and the first pull-down node N31 in response to the second clock signal, and can adjust the potential of the second pull-down node N32 based on the first clock signal. The second control sub-circuit 022 may be configured to control on and off of the second power source terminal VGH and the first pull-down node N31 in response to the potential of the reference node and the first clock signal. The pull-down circuit 03 may be configured to control the on/off of the second power source terminal VGH with the reference node N1 and the pull-up node N2 and the on/off of the first power source terminal VGL with the output terminal OUT in response to the potential of the second pull-down node N32.

Optionally, fig. 6 is a schematic structural diagram of another shift register unit provided in the embodiment of the present disclosure. As can be seen from fig. 5 and 6, the second pull-down node N32 may include: a first child node N32_1 and a second child node N32_ 2. The second control sub-circuit 022 may include: a first control unit 0221 and a second control unit 0222.

Wherein, the first control unit 0221 may be coupled to the reference node N1, the second power source terminal VGH, and the first sub-node N32_1, respectively. The first control unit 0221 may be configured to control the on and off of the second power source terminal VGH and the first sub-node N32_1 in response to the potential of the reference node N1.

The second control unit 0222 may be coupled to the first sub-node N32_1, the first clock terminal CK, and the first pull-down node N31, respectively. The second control unit 0222 may be configured to control on and off of the first sub-node N32_1 and the first pull-down node N31 in response to the first clock signal.

On the premise that the second pull-down node N32 is divided into the first sub-node N32_1 and the second sub-node N32_2, as can be seen from fig. 6, the first control sub-circuit 021 and the third control sub-circuit 023 may be both coupled to the second sub-node N32_2 of the second pull-down node N32. The pull-down circuit 03 may be coupled to the first sub-node N32_1 and the second sub-node N32_2, respectively.

As such, for the structure shown in fig. 6, the first control sub-circuit 021 can adjust the potential of the second sub-node N32_2 based on the first clock signal. The third control sub-circuit 023 may be configured to control the first pull-down node N31 to be switched on and off with the second sub-node N32_2 in response to the target power supply signal. The pull-down circuit 03 may be configured to control the second power source terminal VGH to be turned on or off with the reference node N1 and the pull-up node N2 in response to the potential of the first sub-node N32_1, and may control the first power source terminal VGL to be turned on or off with the output terminal OUT in response to the potential of the second sub-node N32_ 2.

Taking the structure shown in fig. 4 as an example, fig. 7 shows a schematic structure diagram of another shift register unit. Fig. 8 shows a schematic diagram of a further shift register cell.

As an alternative implementation: as shown in fig. 7, the input circuit 01 may be further coupled to the pull-down node N3, and the input circuit 01 may be configured to receive an on control signal transmitted from the pull-down control circuit 02 to the pull-down node N3.

For example, the input circuit 01 may be configured to receive the turn-on control signal transmitted to the pull-down node N3 after the pull-down control circuit 02 turns on the turn-on control terminal STV and the pull-down node N3. In other words, the input circuit 01 may be indirectly coupled to the turn-on control terminal STV through the pull-down control circuit 03.

It should be noted that, taking the structure shown in fig. 5 or fig. 6 as an example, the input circuit 01 is actually coupled to the first pull-down node N31 of the pull-down nodes N3.

As another alternative implementation: as shown in fig. 8, the input circuit 01 may also be directly coupled to the turn-on control terminal STV.

Alternatively, under the premise of the structure shown in fig. 7, fig. 9 shows another shift register unit. As can be seen from fig. 9, the input circuit 01 according to the embodiment of the present disclosure may be further coupled to the second power source terminal VGH. Based on this, the input circuit 01 may also be used to adjust the potential of the reference node N1 based on the second power supply signal. In this manner, stability of the potential of the reference node N1 can be ensured.

On the premise of the structure shown in fig. 9, fig. 10 shows a schematic structure of yet another shift register unit. As shown in fig. 10, the input circuit 01 according to the embodiment of the present disclosure may include: a first input sub-circuit 011 and a second input sub-circuit 012.

The first input sub-circuit 011 can be coupled to the pull-down node N3, the first power source terminal VGL, the second power source terminal VGH, and the reference node N1, respectively. The first input sub-circuit 011 can be configured to control the first power source terminal VGL to be turned on or off with the reference node N1 in response to the potential of the pull-down node N3, and can adjust the potential of the reference node N1 based on the second power source signal.

For example, the first input sub-circuit 011 can control the first power source terminal VGL to be turned on with the reference node N1 when the potential of the pull-down node N3 is the second potential, and can control the first power source terminal VGL to be turned off with the reference node N1 when the potential of the pull-down node N3 is the first potential.

The second input sub-circuit 012 may be coupled to the first clock terminal CK, the reference node N1, and the pull-up node N2, respectively. The second input sub-circuit 012 may be configured to control on/off of the reference node N1 and the pull-up node N2 in response to a first clock signal.

For example, the second input sub-circuit 012 may control the reference node N1 to be turned on with the pull-up node N2 when the potential of the first clock signal is a first potential, and may control the reference node N1 to be disconnected with the pull-up node N2 when the potential of the first clock signal is a second potential.

With the structure shown in fig. 10, fig. 11 shows a schematic structure diagram of another shift register unit. As shown in fig. 11, the first control sub-circuit 021 may include: a first pull-down control transistor T1 and a first capacitor C1. The second control sub-circuit 022 may include: a second pull-down control transistor T2 and a third pull-down control transistor T3. The first control unit 0221 described in the above embodiment may actually include the second pull-down control transistor T2, and the second control unit 0222 may actually include the third pull-down control transistor T3. The first input sub-circuit 011 may include: a first input transistor T5 and a second capacitor C2. The second input sub-circuit 012 may include: and a second input transistor T6. The pull-down circuit 03 may include: a first pull-down transistor T7, a second pull-down transistor T8, and a third pull-down transistor T9. The output circuit 04 may include: an output transistor T0 and a third capacitor C3.

Wherein, the gate of the first pull-down control transistor T1 may be coupled to the second clock terminal CB, the first pole of the first pull-down control transistor T1 may be coupled to the turn-on control terminal STV, and the second pole of the first pull-down control transistor T1 may be coupled to the pull-down node N3.

A first terminal of the first capacitor C1 may be coupled to the first clock terminal CK, and a second terminal of the first capacitor C1 may be coupled to the pull-down node N3.

A gate of the second pull-down control transistor T2 may be coupled to the reference node N1, a first pole of the second pull-down control transistor T2 may be coupled to the second power source terminal VGH, and a second pole of the second pull-down control transistor T2 may be coupled to a first pole of the third pull-down control transistor T3.

The gate of the third pull-down control transistor T3 may be coupled to the first clock terminal CK, and the second pole of the third pull-down control transistor T3 may be coupled to the pull-down node N3.

The gate of the first input transistor T5 may be coupled to the pull-down node N3, a first pole of the first input transistor T5 may be coupled to the first power source terminal VGL, and a second pole of the first input transistor T5 may be coupled to the reference node N1.

A first terminal of the second capacitor C2 may be coupled to the second power source terminal VGH, and a second terminal of the second capacitor C2 may be coupled to the reference node N1.

The gate of the second input transistor T6 may be coupled to the first clock terminal CK, the first pole of the second input transistor T6 may be coupled to the reference node N1, and the second pole of the second input transistor T6 may be coupled to the pull-up node N2.

The gate of the first pull-down transistor T7, the gate of the second pull-down transistor T8, and the gate of the third pull-down transistor T9 may each be coupled to a pull-down node N3, the first poles of the first and second pull-down transistors T7 and T8 may each be coupled to a second power supply terminal VGH, and the first pole of the third pull-down transistor T9 may be coupled to a first power supply terminal VGL. A second pole of the first pull-down transistor T7 may be coupled to the reference node N1, a second pole of the second pull-down transistor T8 may be coupled to the pull-up node N2, and a second pole of the third pull-down transistor T9 may be coupled to the output terminal OUT.

The gate of the output transistor T0 and the first terminal of the third capacitor C3 may be both coupled to the pull-up node N2, the first pole of the output transistor T0 and the second terminal of the third capacitor C3 may be both coupled to the second power source terminal VGH, and the second pole of the output transistor T0 may be coupled to the output terminal OUT.

Taking the structure shown in fig. 7 as an example, referring to fig. 12, the first input sub-circuit 011 can include only the first input transistor T5 and not include the second capacitor C2.

Taking the structure shown in fig. 8 as an example, and the first input sub-circuit 011 is further coupled to the second power source terminal VGH, referring to fig. 13, the first input sub-circuit 011 can include a first input transistor T5 and a second capacitor C2. And the gate of the first input transistor T5 may be directly coupled to the turn-on control terminal STV.

Fig. 14 shows a schematic structure of another shift register unit, based on the structure shown in fig. 5 and fig. 11. In contrast to the structure shown in fig. 11, fig. 14 only needs to provide one more fourth pull-down control transistor T4. The gate of the fourth pull-down control transistor T4 may be coupled to a target power source terminal, the first pole of the fourth pull-down control transistor T4 may be coupled to the first pull-down node N31, and the second pole of the fourth pull-down control transistor T4 may be coupled to the second pull-down node N32.

As can be seen from the embodiment shown in fig. 5, if the fourth pull-down control transistor T4 is an N-type transistor, the target power source terminal may be the second power source terminal VGH. If the fourth pull-down control transistor T4 is a P-type transistor, the target power source terminal is the first power source terminal VGL. The fourth pull-down controlling transistor T4 shown in fig. 14 is an N-type transistor and the target power source terminal is the second power source terminal VGH.

Fig. 15 shows a schematic structure of another shift register unit, based on the structure shown in fig. 14 and fig. 6. With respect to the structure shown in fig. 14, in the structure shown in fig. 15, the gates of the first pull-down transistor T7 and the second pull-down transistor T8 are both coupled to the first sub-node N32_1, and the gate of the third pull-down transistor T9 is coupled to the second sub-node N32_ 2.

For the structures shown in fig. 11 to 15, in order to ensure that the circuits operate reliably under the control of the above-mentioned potentials, the first input transistor T5 for controlling the on/off of the first power source terminal VGL and the reference node N1 in the input circuit 01 may be an N-type transistor. In the input circuit 01, the second input transistor T6 for controlling the on/off of the reference node N1 and the pull-up node N2, the pull-down control transistors included in the pull-down control circuit 02, the pull-down transistors included in the pull-down circuit 03, and the output transistor T0 included in the output circuit 04 may all be P-type transistors. This approach of using P-type + N-type transistors may also be referred to as a complementary metal-oxide-semiconductor (CMOS) process.

In addition, the shift register unit shown in fig. 11 to 13 includes 9 transistors in total, and the shift register unit shown in fig. 14 and 15 includes 10 transistors in total. Whereas shift register cells used to provide light emission control signals in the related art typically each include at least 12 transistors. It can thus be further determined that the shift register cell described in the embodiments of the present disclosure includes a relatively small number of transistors.

Because each transistor has a certain resistance, when a signal passes through the transistor, the voltage of the signal generally has a certain loss correspondingly, so that the number of the transistors is reduced, the narrow frame design of the display device can be facilitated, the loss of the voltage of the signal can be reduced, and the loss of the light-emitting control signal finally transmitted to the pixel circuit is less. Further, the problem of abnormal light emission of the light emitting element can be avoided, and the problem of abnormal display (such as split screen and flash screen) of the display panel can be further avoided. In other words, the shift register unit described in the embodiment of the present disclosure can ensure that the pixel circuit normally drives the light emitting element only by including a small number of transistors, and the area of the display panel required to be occupied by the whole shift register unit is small, thereby improving the problem of a large frame of the display device and facilitating the design of a narrow frame. In addition, the display effect of the display panel can be ensured to be better.

Fig. 16 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure. The method may be used to drive a shift register cell as shown in any of figures 3 to 15. As shown in fig. 16, the method may include:

step 1601, in a first stage, the pull-down control circuit controls the pull-down node to be conducted with the start control terminal in response to a second clock signal of the first potential, and the pull-down circuit controls the second power terminal to be conducted with the pull-up node and the reference node respectively in response to the potential of the pull-down node, and controls the first power terminal to be conducted with the output terminal.

In step 1602, in the second stage, the pull-down circuit responds to the potential of the pull-down node to control the second power source terminal to be respectively conducted with the pull-up node and the reference node, and to control the first power source terminal to be conducted with the output terminal, and the input circuit responds to the first clock signal of the first potential to control the pull-up node to be conducted with the reference node.

In the third stage 1603, the pull-down control circuit responds to the second clock signal of the first potential to control the pull-down node to be conducted with the start control end; the input circuit responds to a starting control signal of the second potential and controls the first power supply end to be conducted with the reference node.

1604, in a fourth stage, the input circuit controls the first power end and the reference node to be conducted in response to the start control signal of the second potential, and controls the reference node and the pull-up node to be conducted in response to the first clock signal of the first potential; the output circuit responds to the electric potential of the pull-up node and controls the conduction of the second power supply end and the output end; the pull-down control circuit controls the second power supply terminal to be conducted with the pull-down node in response to the potential of the reference node and a first clock signal of the first potential.

Step 1605, in the fifth stage, the pull-down control circuit responds to the second clock signal of the first potential to control the conduction of the pull-down node and the start control end; the input circuit responds to a starting control signal of the second potential and controls the first power supply end to be conducted with the reference node; the output circuit responds to the electric potential of the pull-up node and controls the conduction of the second power supply end and the output end.

And, step 1606, after the fifth stage, again performs the fourth stage.

After the fifth stage, the potential of the turn-on control signal may be the second potential.

Take the shift register unit shown in fig. 11 as an example. The pixel circuit driving principle described in the embodiments of the present disclosure is described in detail. The following description will clearly describe the first potential and the second potential of each terminal signal as a high potential and a low potential. Fig. 17 is a timing diagram of signal terminals in a shift register unit according to an embodiment of the disclosure. As shown in fig. 17:

in the first phase t1, the potential of the first clock signal provided by the first clock terminal CK is high. The second clock signal provided by the second clock terminal CB and the turn-on control signal provided by the turn-on control terminal STV are both low, and the second input transistor T6 and the third pull-down control transistor T3 are both turned off. The first pull-down control transistor T1 is turned on. The low-level turn-on control signal is transmitted to the pull-down node N3 through the first pull-down control transistor T1 to charge the first capacitor C1. The first input transistor T5 is turned off, and the first pull-down transistor T7, the second pull-down transistor T8, and the third pull-down transistor T9 are all turned on. The first power signal supplied from the first power terminal VGL is transmitted to the output terminal OUT through the third pull-down transistor T9. The second power signal provided from the second power source terminal VGH is transmitted to the reference node N1 through the first pull-down transistor T7 and to the pull-up node N2 through the second pull-down transistor T8. Since the potential of the second power signal is high, the second pull-down control transistor T2 and the output transistor T0 are turned off. Since the first power signal is at a low potential, the emission control signal transmitted from the output terminal OUT to the emission control terminal EM is at a low potential. The low-potential emission control signal corresponds to an inactive potential for the pixel circuit.

In addition, in the first stage t1, the second power signal with the high potential continuously charges the second capacitor C2 and the third capacitor C3, so that the potential of the reference node N1 and the potential of the pull-up node N2 can be stably maintained at the high potential. Fig. 18 shows an equivalent circuit diagram of the shift register cell at the first stage t 1. Where "dashed √" is used to indicate that the transistor is on, and "dashed x" is used to indicate that the transistor is off.

In the second stage t2, the level of the start control signal is kept low, the level of the second clock signal jumps to high, and the level of the first clock signal jumps to low. The first pull-down control transistor T1 is turned off, and both the second input transistor T6 and the third pull-down control transistor T3 are turned on. Although the first pull-down control transistor T1 is turned off, the pull-down node N3 may be further pulled down by the low-level first clock signal under the bootstrap action of the first capacitor C1. The first input transistor T5 remains off, and the first pull-down transistor T7, the second pull-down transistor T8, and the third pull-down transistor T9 remain on. The first power signal with the low potential is still transmitted to the output terminal OUT through the third pull-down transistor T9. The high-level second power signal is still transmitted to the reference node N1 through the first pull-down transistor T7, and is still transmitted to the pull-up node N2 through the second pull-down transistor T8. In addition, since the second input transistor T6 is turned on, the potential of the pull-up node N2 can be kept consistent with the potential of the reference node N1. The second pull-down control transistor T2 and the output transistor T0 may remain turned off under the control of the second power signal of the high potential as in the first stage T1. The emission control signal transmitted from the output terminal OUT to the emission control terminal EM is still at a low potential. The low-potential emission control signal corresponds to an inactive potential for the pixel circuit.

In addition, in the first stage t1, the second power signal with high voltage still charges the second capacitor C2 and the third capacitor C3, so that the voltage of the reference node N1 and the voltage of the pull-up node N2 can be stably maintained at high voltage. Fig. 19 shows an equivalent circuit diagram of the shift register cell at the first stage t 2.

In the third stage t3, the potential of the start control signal jumps to a high potential, the potential of the second clock signal jumps to a low potential, and the potential of the first clock signal jumps to a high potential. The first pull-down control transistor T1 is turned on, and the second input transistor T6 and the third pull-down control transistor T3 are turned off. The high-level on control signal is transmitted to the pull-down node N3 through the first pull-down control transistor T1 and charges the first capacitor C1, so that the level of the pull-down node N3 can be reliably maintained at a high level under the control of the high-level on control signal and the high-level first clock signal. The first pull-down transistor T7, the second pull-down transistor T8, and the third pull-down transistor T9 are all turned off. The first input transistor T5 is turned on. The first power signal with the low level is transmitted to the reference node N1 through the first input transistor T5, and charges the second capacitor C2. The second pull-down control transistor T2 is turned on. In addition, under the holding action of the third capacitor C3, the pull-up node N2 may be held at the high potential of the second stage T2, and the output transistor T0 may be kept turned off. Further, the output terminal OUT may be maintained at the low potential of the second stage t 2. Fig. 20 shows an equivalent circuit diagram of the shift register cell at the third stage t 3.

In the fourth stage t4, the potential of the on control signal is kept high, the potential of the second clock signal jumps to high, and the potential of the first clock signal jumps to low. The second input transistor T6 and the third pull-down control transistor T3 are turned on. The first pull-down control transistor T1 is turned off, but the pull-down node N3 may be maintained at the high potential of the second stage T2 by the holding action of the first capacitor C1. The first pull-down transistor T7, the second pull-down transistor T8, and the third pull-down transistor T9 are all turned off. The first input transistor T5 is turned on. The first power signal having a low potential is transmitted to the reference node N1 through the first input transistor T5, and charges the second capacitor C2. The second pull-down control transistor T2 is turned on, and the high-level second power signal is transmitted to the pull-down node N3 through the second pull-down control transistor T2 and the third pull-down control transistor T3, thereby ensuring that the pull-down node N3 is reliably kept at the high level. Since the second input transistor T6 is turned on, the low potential at the reference node N1 can be transmitted to the pull-up node N2 through the second input transistor T6 and charge the third capacitor C3, ensuring that the pull-up node N2 is kept at a low potential. Thus, the output transistor T0 is turned on reliably, and the high-level second power signal can be transmitted to the output terminal OUT through the output transistor T0. The light emission control signal at a high potential corresponds to an effective potential for the pixel circuit. The pixel circuit can drive the coupled light-emitting element to reliably emit light under the drive of the high-potential light-emitting control signal. Fig. 21 shows an equivalent circuit diagram of the shift register cell at a fourth stage t 4.

In the fifth period t5, the potential of the start control signal is kept high, the potential of the second clock signal jumps to the low potential, and the potential of the first clock signal jumps to the high potential. The first pull-down control transistor T1 is turned on, and the second input transistor T6 and the third pull-down control transistor T3 are turned off. The high-level on control signal is transmitted to the pull-down node N3 through the first pull-down control transistor T1 and charges the first capacitor C1, so that the level of the pull-down node N3 can be reliably maintained at a high level under the control of the high-level on control signal and the high-level first clock signal. The first pull-down transistor T7, the second pull-down transistor T8, and the third pull-down transistor T9 are all turned off. The first input transistor T5 is turned on. The first power signal with a low potential is transmitted to the reference node N1 through the first input transistor T5 and charges the second capacitor C2, and the reference node N1 is reliably maintained at a low potential. The second pull-down control transistor T2 is turned on. In addition, under the holding action of the third capacitor C3, the pull-up node N2 may be kept at the low potential of the fourth stage T4, and the output transistor T0 may be kept turned on. Further, the high-level second power signal may continue to be transmitted to the output terminal OUT through the output transistor T0. Fig. 22 shows an equivalent circuit diagram of the shift register cell at the fifth stage t 5.

After the fifth stage t5, the above-mentioned fourth stage t4, first stage t1 and second stage t2 are sequentially performed continuously (the fourth stage t4, first stage t1 and second stage t2 which are sequentially performed are respectively identified by t6, t7 and t8 in fig. 17). After the fifth stage t5, the potential of the on control signal jumps to the low potential, and after the next third stage t3, the potential of the on control signal jumps to the high potential again. As can be seen from comparing the timing diagrams shown in fig. 2 and fig. 17, the shift register unit according to the embodiment of the present disclosure can reliably transmit the light emission control signal shown in fig. 2 to the pixel circuit.

It should be noted that after the fifth phase t5, the fourth phase may be resumed after a certain time interval, that is, the phase t6 shown in fig. 17 is resumed.

It should be noted that, in the embodiment of the present disclosure, the light-emitting control signal finally output by the output terminal OUT of the shift register unit may be a pulse with a width of 3H as shown in fig. 17, where H is a unit of pulse width. Of course, in some embodiments, the pulse width of the light emitting control signal finally output by the output terminal OUT of the shift register unit may also be 5H or 7H, etc. The embodiments of the present disclosure do not limit this.

Optionally, the pulse width of the light-emitting control signal output by the output terminal OUT of the shift register unit may be flexibly adjusted by setting the potential of the signal provided by each control terminal and/or each clock terminal coupled to the shift register unit. And the flexible adjustment of the luminous brightness of the luminous element can be achieved by adjusting the pulse width of the luminous control signal.

Optionally, fig. 23 further shows a timing simulation diagram of the reference node N1, the pull-up node N2, the reference node N3, and the output end OUT of the shift register unit according to the embodiment of the disclosure. Fig. 24 also shows a timing simulation diagram of the turn-on control terminal STV, the output terminal OUT, the first clock terminal CK and the second clock terminal CB to which the shift register unit is coupled according to the embodiment of the disclosure. And in the simulation diagrams shown in fig. 23 and 24, the abscissa may be used to indicate the time T in microseconds (μ s), and the ordinate may be used to indicate the voltage U in volts (v). Fig. 23 and 24 collectively identify 5 different time nodes Tm1, Tm2, Tm3, Tm4, and Tm 5.

In summary, the embodiments of the present disclosure provide a driving method of a shift register unit. In the driving method, the input circuit included in the shift register unit can reliably transmit the first power supply signal to the pull-up node only under the control of the starting control end and the first clock end so as to charge the pull-up node. The pull-down control circuit can reliably control the potential of the pull-down node only under the control of the first clock end and the second clock end. Therefore, compared with the related art, each circuit included in the shift register unit can normally work only under the control of a small number of control ends, and accordingly, the structure of each circuit can be simpler, and narrow-frame design of the display device is facilitated.

Fig. 25 is a schematic structural diagram of a gate driving circuit according to an embodiment of the disclosure. As shown in fig. 25, the gate driving circuit may include: at least two cascaded shift register cells as shown in any of fig. 3 to 15. For example, fig. 25 collectively shows 4 shift register units 00_1, 00_2, 00_3, and 00_4 in cascade.

The output terminal OUT of each stage of the shift register unit may be coupled to the emission control terminal EM of one row of the pixel circuits (not shown in fig. 25). The first power source terminal VGL of each stage of the shift register unit may be coupled to the first power source line VGL. The second power source terminal VGH of each stage of the shift register unit may be coupled to the second power source line VGH. The first clock terminal CK of the odd-numbered stage shift register unit (e.g., the first stage shift register unit 00_1 and the third stage shift register unit 00_3) may be coupled to the first clock line CK, and the second clock terminal CB of the odd-numbered stage shift register unit may be coupled to the second clock line CB. The first clock terminal CK of the even-numbered stage shift register unit (e.g., the second stage shift register unit 00_2 and the fourth stage shift register unit 00_4) may be coupled to the second clock line CB, and the second clock terminal CB of the even-numbered stage shift register unit may be coupled to the first clock line CK. That is, the two first clock terminals CK included in each adjacent two shift register units may be alternately coupled with the first clock line CK and the second clock line CB, and the two second clock terminals CB included in each adjacent two shift register units may be alternately coupled with the first clock line CK and the second clock line CB. In addition, the turn-on control terminal STV of the first stage shift register unit 00_1 may be coupled to a turn-on control line STV. The start control terminal STV of each stage of shift register unit except the first stage of shift register unit 00_1 may be coupled to the output terminal OUT of the previous stage of shift register unit in cascade. For example, the turn-on control terminal STV of the second stage shift register unit 00_2 can be coupled to the output terminal OUT of the first stage shift register unit 00_ 1. Thus, the purpose of effective cascade connection is achieved.

Fig. 26 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 26, the display device may include: a display panel 100, and a gate driving circuit 000 as shown in fig. 25.

The display panel 100 may include a plurality of pixel circuits. The gate driving circuit 000 may be coupled to the emission control terminal EM in the pixel circuit (not shown in fig. 25), and the gate driving circuit 000 may be configured to provide an emission control signal to the emission control terminal EM.

Alternatively, referring to fig. 26, the display device 000 may generally include two gate driving circuits 000 located at two opposite sides (e.g., the left and right sides shown in the figure) of the display panel 100, and each gate driving circuit 000 may include a plurality of shift register units connected in cascade.

Optionally, the display device may be: any product or component having a display function, such as an active-matrix organic light-emitting diode (AMOLED) display device, an organic light-emitting diode (OLED) display device, and a liquid crystal display device.

The AMOLED display device has the advantages of low power consumption, wide working temperature range, low cost, high contrast, wide viewing angle, wide color gamut and thin display panel, can realize flexible display, and gradually becomes a display crown of the next generation. The OLED display device can meet the requirements of most of the current information times on high performance and large capacity of display equipment, can be used for indoor and outdoor illumination, can be used as a wallpaper ornament, can be made into folded electronic newspapers, and can also be applied to portable electronic products such as mobile phones, tablet computers, wearable electronic equipment and the like.

It should be understood that the terms "first," "second," and the like in the description and claims of the embodiments of the disclosure and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used are interchangeable under appropriate circumstances and can be implemented in sequences other than those illustrated or otherwise described herein with respect to the embodiments of the application, for example.

It should be understood that the term "and/or" in the description of the embodiments of the present disclosure means that there may be three relationships, for example, a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims

1. A shift register cell, comprising: the pull-down circuit comprises an input circuit, a pull-down control circuit, a pull-down circuit and an output circuit;

2. The shift register cell of claim 1, wherein the pull-down control circuit comprises: a first control sub-circuit and a second control sub-circuit;

3. The shift register cell of claim 2, wherein the first control sub-circuit is further coupled to the first clock terminal, the first control sub-circuit being further configured to adjust a potential of the pull-down node based on the first clock signal;

4. The shift register cell of claim 2, wherein the pull-down node comprises: a first pull-down node and a second pull-down node; the pull-down control circuit further comprises: a third control sub-circuit;

5. The shift register cell of claim 4, wherein the third control sub-circuit comprises: a fourth pull-down control transistor;

6. The shift register cell of claim 4, wherein the second pull-down node comprises: a first child node and a second child node; the second control sub-circuit comprises: a first control unit and a second control unit;

7. The shift register cell according to any one of claims 1 to 6, wherein the input circuit is further coupled to the pull-down node, the input circuit being configured to receive the enable control signal transmitted to the pull-down node by the pull-down control circuit;

or, the input circuit is further coupled to the start control terminal.

8. The shift register cell of claim 7, wherein the input circuit is further coupled to the second power supply terminal, the input circuit further for adjusting the potential of the reference node based on the second power supply signal.

9. The shift register cell of claim 8, wherein the input circuit is coupled to the pull-down node; the input circuit includes: a first input sub-circuit and a second input sub-circuit;

10. The shift register cell of claim 9, wherein the first input sub-circuit comprises: a first input transistor and a second capacitor; the second input sub-circuit comprises: a second input transistor;

11. The shift register cell according to any one of claims 1 to 6, wherein the pull-down circuit comprises: a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor;

12. The shift register cell according to any one of claims 1 to 6, wherein the output circuit comprises: an output transistor and a third capacitor;

13. The shift register unit according to any one of claims 1 to 6, wherein in the input circuit, a first input transistor for controlling on/off of the first power source terminal and the reference node is an N-type transistor;

14. A method of driving a shift register cell, for driving a shift register cell according to any one of claims 1 to 13; the method comprises the following steps:

15. A gate drive circuit, comprising: at least two cascaded shift register cells according to any of claims 1 to 13.

16. A display device, characterized in that the display device comprises: a display panel including a plurality of pixel circuits, and the gate driver circuit according to claim 15;