CN113097310A - Fin-type EAFin-LDMOS device with electron accumulation effect - Google Patents
Fin-type EAFin-LDMOS device with electron accumulation effect Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention relates to a fin-type EAFin-LDMOS device with an electron accumulation effect, and belongs to the technical field of semiconductors. The device is divided into: a substrate, a buried oxide layer and a device upper portion; wherein the device upper portion includes: a gate oxide layer; outer part of the gate oxide layer: a source electrode P + region, a source electrode N + region, a P-body, a drift region and a drain electrode N + region are arranged from left to right in sequence; the inner side part of the gate oxide layer: the gate P + region, the gate P-body, the drift region of the control structure, the drain N + region of the control structure and the drain P + region of the control structure are arranged from left to right in sequence. The invention uses the electron accumulation effect in the device and adopts a fin type structure, thereby greatly reducing R under the condition of keeping higher breakdown voltageon,spFinally, the Baliga figure of merit FOM is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a fin-type EAFin-LDMOS device with an electron accumulation effect.
Background
As the demand for power semiconductor devices continues to increase, the development of power semiconductor devices is promoted. The lateral double-diffused field effect transistor (LDMOS) used for processing medium-low power plays a very important role in the process, and the manufacturing process of the LDMOS can be compatible with the traditional CMOS process, and the manufacturing process is simple and has good stability. Since the LDMOS is a voltage-controlled device, the input impedance is high and the driving circuit is much easier compared to a device controlled by current (e.g. power bipolar transistor, conventional thyristor). And it only has the majority carrier conduction and no minority carrier storage effect, and can obtain higher switching speed, so that its working frequency can have higher working frequency than other devices whose several carriers are conductive. These advantages of LDMOS also make it extremely competitive in the power semiconductor industry, while driving the benign development of power semiconductor devices. The LDMOS is used for carrying out medium-low power processing, so that the electric energy can be utilized more efficiently, the energy is saved, and the effect is improved.
In addition, due to the unique structural characteristics of the SOI (Silicon-On-Insulator) base substrate, the defects of a plurality of bulk Silicon materials are overcome, and the potential of the Silicon integrated circuit technology can be fully exerted when the SOI substrate is used in an integrated circuit. High Voltage Integrated Circuits (HVICs) based on SOI substrates integrate SOI technology, microelectronics and power electronics, and thus are rapidly developed, and have a very wide application prospect in weaponry, aerospace, industrial automation, power electronics and other High and new technology industries. One of the cornerstone and core portions of an SOI HVIC is an SOI-LDMOS (silicon-on-insulator-Metal-Oxide-Semiconductor) device, which has a major problem in the current time in the specific on-resistance Ron,sp∝BV2.5. In order to achieve a high Breakdown Voltage (BV), a long and low concentration lateral drift region is inevitably required, and hence the specific on-resistance (R) of the deviceon,sp) Higher, BV and Ron,spThe contradiction between the two methods is more prominent. In order to better measure the overall performance of the device, the Baliga figure of merit is used as an important index FOM (figure of meri) for evaluating the devicet), wherein FOM ═ BV2/Ron,sp。
In order to solve the contradiction, the electrical performance limit of the silicon device is broken through, and a new LDMOS device is urgently needed, the specific on-resistance of the device can be reduced, and higher BV can be maintained to obtain larger FOM.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a fin-type EAFin-LDMOS device with electron accumulation effect, in which the electron accumulation effect is used and a fin-type structure is adopted to greatly reduce R under the condition of keeping a higher breakdown voltageon,spFinally, the Baliga figure of merit FOM is improved.
In order to achieve the purpose, the invention provides the following technical scheme:
a fin-type EAFin-LDMOS device with an electron accumulation effect is divided into:
1) a device upper portion comprising: the gate oxide layer 6, the outer part of the gate oxide layer 6 and the inner part of the gate oxide layer 6;
the outer part of the gate oxide layer 6 (which is a conventional LDMOS structure): the source electrode P + region 1, the source electrode N + region 2, the P-body3, the drift region 4 and the drain electrode N + region 5 are arranged from left to right in sequence; the source P + region 1 and the source N + region 2 are positioned in the upper left region of the whole device and are surrounded by a P-body 3; the right side of the P-body3 is in contact with the left side of the drift region 4; the drain N + region 5 is positioned in the upper right region of the whole device, and the left side and the lower side are surrounded by the drift region 4;
2) the middle part of the device: a buried oxide layer 10, located below the upper portion of the device and above the bottom portion of the device;
3) device bottom part: consisting of a substrate 11, located under the middle portion of the device.
Preferably, the drift region 4 and the drift region 9 of the control structure can be added with P-type regions, and the RESURF technology is used for improving the performance of the device.
Preferably, the drift region 4 and the drift region 9 of the control structure can be added with a super junction P-type region, and the super junction technology is used for improving the performance of the device.
Preferably, the outer part of the gate oxide layer 6 further comprises: and the surface gate oxide layer 16 is positioned on the upper surface of the P-body3 between the source N + region 2 and the drift region 4 and is connected with the gate P + region 12.
Preferably, the drain P + region 7 of the control structure is extended to the outer portion of the gate oxide layer 6, forming a drain P + region 17, such that the drain N + region 5 is in direct contact with the drain P + region 17.
Preferably, the Z-direction width and thickness of the inner portion of the gate oxide layer 6 may be changed as desired.
Preferably, the device is an N-type LDMOS device and can be correspondingly switched into a P-type LDMOS device.
Preferably, the source P + region 1 and the source N + region 2 at the source end outside the gate oxide layer 6 may be designed from the device surface as the inside of the left side of the device.
Preferably, the device structure is also applicable to VDMOS devices and IGBT devices.
Preferably, the device structure can replace the inner part of the gate oxide layer 6 with the outer part structure, so that the LDMOS device structure is located inside the gate oxide layer 6 and the gate control structure is located outside the gate oxide layer 6.
Preferably, the device may not use a buried oxide layer 10, with the substrate 11 in direct contact over the buried oxide layer 10.
Preferably, the device can completely encapsulate the gate control structure therein using the LDMOS structure of the gate oxide layer 6.
Preferably, the drift region 4 and the drift region 9 of the control structure may be doped with varying concentrations.
Preferably, the drain N + region 5, the drain N + region 8 of the control structure and the drain P + region 7 of the control structure may have their doping concentrations and structure sizes changed as required.
Preferably, the gate P + region 12 may be modified as desired to other conductive materials including, but not limited to, aluminum and polysilicon.
Preferably, the doping concentration of the gate P + region 12 may be changed as desired.
The invention has the beneficial effects that:
the device is additionally provided with a control structure inside the traditional LDMOS device, and is isolated by using the gate oxide layer, so that the upper part of the buried oxide layer of the LDMOS device can be divided into three parts, namely the gate oxide layer, the control structure inside the gate oxide layer and the LDMOS structure outside the gate oxide layer. When the grid electrode P + area is positively conducted, grid voltage is applied to the grid electrode P + area, at the moment, the PN junction of the grid electrode P-body and the drift area of the control structure is positively biased, and the PN junction of the drain electrode N + area of the control structure and the drain electrode P + area of the control structure is reversely biased.
Therefore, the voltage of the gate voltage from the gate P + region to the drain N + region of the control structure is reduced little through the gate P-body and the drift region of the control structure, so that an electron accumulation layer is formed in the P-body and the drift region close to the gate oxide layer when the gate is conducted in the forward direction, and the specific conducting resistance of the device is greatly reduced. Meanwhile, due to the existence of PN reverse bias junctions of the drain electrode N + region of the control structure and the drain electrode P + region of the control structure, the grid electrode and the drain electrode are not conducted. When the device is turned off, PN junctions of the drain N + region of the control structure and the drain P + region of the control structure are forward biased, the whole device is a reverse biased PN junction of the P-body and the drift region, and the reverse biased PN junction of the grid P-body and the drift region of the control structure is resistant to pressure. Meanwhile, the parameters of the P-body and the grid P-body, the drift region and the drift region of the control structure, and the parameters of the drain N + region and the drain N + region of the control structure are the same, so that the voltage change at the same position inside and outside the gate oxide layer is not large, the drift region near the gate oxide layer of the drift region cannot be broken down in advance, and the device can still obtain larger breakdown voltage.
The invention greatly reduces the specific on-resistance of the device and enables the device to have larger breakdown voltage. The irreconcilable contradiction relation between the specific on-resistance and the breakdown voltage of the traditional MOSFET is solved, and the silicon limit is broken.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural diagram of an EAFin-LDMOS device according to embodiment 1 of the present invention;
fig. 2 is a schematic structural diagram of the middle of the EAFin-LDMOS device in the Z direction according to embodiment 1 of the present invention, where the cut plane is shown by a dashed line in fig. 1;
FIG. 3 is a schematic structural diagram of an EAFin-LDMOS device according to embodiment 2 of the present invention;
FIG. 4 is a schematic structural diagram of an EAFin-LDMOS device according to embodiment 3 of the present invention;
FIG. 5 is a schematic structural diagram of an EAFin-LDMOS device according to embodiment 4 of the present invention;
FIG. 6 is a schematic structural diagram of an EAFin-LDMOS device according to embodiment 5 of the present invention;
fig. 7 is a schematic structural diagram of the middle of the EAFin-LDMOS device in the Z direction according to embodiment 5 of the present invention, where the cut plane is shown by a dashed line in fig. 6;
FIG. 8 shows that the doping concentration of the drift region of the EAFin-LDMOS device and the conventional SOI-LDMOS device of embodiment 1 of the present invention is 2 × 1015cm-3To 4.5X 1015cm-3Breakdown voltage comparison graph between;
FIG. 9 shows the EAFin-LDMOS device of embodiment 1 of the present invention with a doping concentration of 2 × 10 in the drift region15cm-3The doping concentration of the drift region of the traditional SOI-LDMOS device is 2 multiplied by 1015cm-3、3×1015cm-3、3.5×1015cm-3And 4.5X 1015cm-3A drain voltage versus drain current graph of;
FIG. 10 shows a graph at V of example 1 of the present inventionGS＝10V、VDSThe doping concentration of the drift region is 3.5 × 10 at 0V15cm-3The electron density distribution of the drift region of the CON-LDMOS and the doping concentration of the drift region are 4 multiplied by 1015cm-3The EAFin-LDMOS is close to the electron density distribution condition of a drift region at the outer side of a gate oxide layer;
FIG. 11 shows example 1 of the present invention at VGS＝10V、VDSWhen 1V and Y are 5 μm, the doping concentration of the drift region is 3.5 × 1015cm-3The doping concentration of the CON-LDMOS (left) and the drift region is 4 multiplied by 1015cm-3Electron current density distribution at the cross section of the drift region of the EAFin-LDMOS (right);
FIG. 12 shows example 1 of the present invention at VGS＝10V、VDSThe doping concentration of the drift region is 3.5 multiplied by 10 when the value is 1V15cm-3The doping concentration of the CON-LDMOS and the drift region is 4 multiplied by 1015cm-3The electron current density distribution condition of the drift region of the EAFin-LDMOS along the Y-axis direction;
FIG. 13 shows the EAFin-LDMOS device of embodiment 1 of the present invention and the conventional SOI-LDMOS device having a drift region with a doping concentration of 2 × 1015cm-3To 4.5X 1015cm-3A comparison graph of specific on-resistance between;
FIG. 14 shows the EAFin-LDMOS device of embodiment 1 of the present invention and the conventional SOI-LDMOS device having a drift region with a doping concentration of 2 × 1015cm-3To 4.5X 1015cm-3Baliga figure of merit FOM comparison between;
FIG. 15 is a distribution diagram of the voltage along the Y-axis of the control structure of the EAFin-LDMOS device of embodiment 1 of the present invention;
FIG. 16 is an equivalent circuit diagram of an EAFin-LDMOS device in accordance with embodiment 1 of the present invention;
FIG. 17 is a schematic diagram of a main process flow of an EAFin-LDMOS device according to embodiment 1 of the present invention;
reference numerals: the transistor comprises a 1-source P + region, a 2-source N + region, a 3-P-body, a 4-drift region, a 5-drain N + region, a 6-gate oxide layer, a 7-control structure drain P + region, an 8-control structure drain N + region, a 9-control structure drift region, a 10-buried oxide layer, an 11-substrate, a 12-gate P + region, a 13-gate P-body, a 14-P type region, a 15-super-junction P type region, a 16-surface gate oxide layer and a 17-drain P + region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.
Example 1:
as shown in fig. 1 and fig. 2, the present embodiment designs a fin-type EAFin-LDMOS device with an electron accumulation effect, which includes: the semiconductor device comprises a source P + region 1, a source N + region 2, a P-body3, a drift region 4, a drain N + region 5, a gate oxide layer 6, a drain P + region 7 of a control structure, a drain N + region 8 of the control structure, a drift region 9 of the control structure, a buried oxide layer 10, a substrate 11, a gate P + region 12 and a gate P-body 13.
1) The upper part of the device is as follows: the upper part of the device can be divided into three parts, namely a gate oxide layer 6 part, a gate oxide layer 6 outer part and a gate oxide layer 6 inner part. The method comprises the following specific steps:
Outer part of gate oxide layer 6: the part is a traditional LDMOS structure and comprises a source P + region 1, a source N + region 2, a P-body3, a drift region 4 and a drain N + region 5 from left to right. The source P + region 1 and the source N + region 2 are positioned in the upper left region of the whole device and are surrounded by the P-body 3; the right side of the P-body3 is in contact with the left side of the drift region 4; the drain N + region 5 is located in the upper right region of the overall device, and the left and lower sides are surrounded by the drift region 4.
Inner side part of gate oxide layer 6: this portion is a PNP structure, and from left to right there is a gate P + region 12, a gate P-body13, a drift region 9 of the control structure, a drain N + region 8 of the control structure, and a drain P + region 7 of the control structure. Wherein the right side of gate P + region 12 is in contact with the left side of gate P-body 13; the right side of the gate P-body13 is in contact with the left side of the drift region 9 of the control structure; the drain N + region 8 of the control structure is located in the upper right region of the device and is surrounded by the drift region 9 of the control structure, while its upper right corner also surrounds the drain P + region 7 of the control structure.
2) The middle part of the device: the device middle portion is located below the device upper portion and above the device bottom portion, and this layer is comprised of a buried oxide layer 10.
3) Device bottom part: the bottom part of the device is located below the middle part of the device and this layer is composed of the substrate 11.
Wherein the substrate 11 is 1.5 μm thickDoped silicon with a width of 10 μm and a doping concentration of 8 × 1014cm-3Boron (b) in the presence of boron. The buried oxide layer 10 is silicon dioxide with a thickness of 2 μm and a width of 10 μm.
In the upper part of the device, the source P + region 1 has a length of 1 μm in the x-direction, a length of 0.5 μm in the y-direction, and a length of 1 μm in the z-direction, and has a doping concentration of 1X 1019cm-3(ii) a The source N + region 2 has a length of 1 μm in the x direction, a length of 0.5 μm in the y direction, a length of 1 μm in the z direction, and a doping concentration of 1X 1019cm-3(ii) a The length of the P-body3 in the x direction was 3 μm, the length in the y direction was 1.5 μm, the length in the z direction was 1 μm, and the doping concentration was 1X 1017cm-3(ii) a The drift region 4 has a length of 3 μm in the x-direction, a length of 7.5 μm in the y-direction, a length of 1 μm in the z-direction, and a doping concentration of 4X 1015cm-3(ii) a The drain N + region 5 has a length of 1.5 μm in the x-direction, a length of 1 μm in the y-direction, a length of 1 μm in the z-direction, and a doping concentration of 1X 1019cm-3(ii) a The thickness of the gate oxide layer 6 is 0.1 μm, the length in the y direction is 10 μm, and the length in the z direction is 0.6 μm; the drain P + region 7 of the control structure has a length of 0.6 μm in the x-direction, a length of 0.5 μm in the y-direction, a length of 0.4 μm in the z-direction, and a doping concentration of 1 × 1019cm-3(ii) a The drain N + region 8 of the control structure has a length of 1.1 μm in the x-direction, a length of 1 μm in the y-direction, a length of 0.4 μm in the z-direction, and a doping concentration of 1 × 1019cm-3(ii) a The drift region 9 of the control structure has a length of 2.6 μm in the x-direction, a length of 7.5 μm in the y-direction and a length of 0.4 μm in the z-direction, and a doping concentration of 4X 1015cm-3(ii) a The gate P + region 12 has a length of 3 μm in the x-direction, a length of 1 μm in the y-direction, and a length of 0.4 μm in the z-direction, and has a doping concentration of 1X 1019cm-3(ii) a The gate P-body13 has a length of 3 μm in the x-direction, a length of 0.5 μm in the y-direction, and a length of 0.4 μm in the z-direction, and a doping concentration of 1X 1017cm-3。
Example 2:
as shown in fig. 3, the present embodiment designs a fin-type EAFin-LDMOS device with electron accumulation effect, which includes: the structure comprises a source P + region 1, a source N + region 2, a P-body3, a drift region 4, a drain N + region 5, a gate oxide layer 6, a drain P + region 7 of a control structure, a drain N + region 8 of the control structure, a drift region 9 of the control structure, a buried oxide layer 10, a substrate 11, a gate P + region 12, a gate P-body13 and a P-type region 14.
On the basis of the structure of the embodiment 1, the P-type region 14 is added in the middle of the drift region 4 of the LDMOS structure outside the original gate oxide layer 6, and the RESURF technology is used for optimizing the specific on-resistance and the breakdown voltage of the device. The position, size and doping concentration of the P-type region 14 in the drift region can be changed according to actual conditions.
Example 3:
as shown in fig. 4, the present embodiment designs a fin EAFin-LDMOS device with electron accumulation effect, which includes: the semiconductor device comprises a source P + region 1, a source N + region 2, a P-body3, a drift region 4, a drain N + region 5, a gate oxide layer 6, a drain P + region 7 of a control structure, a drain N + region 8 of the control structure, a drift region 9 of the control structure, a buried oxide layer 10, a substrate 11, a gate P + region 12, a gate P-body13 and a super junction P-type region 15.
A super junction P-type region 15 is added in a drift region of the device, the doping concentration of the device can be further improved by using a super junction technology, and the specific on-resistance and breakdown voltage of the device are optimized. The thickness, width and doping concentration of the super junction P-type region 15 in the drift region can be changed according to actual conditions.
Example 4:
as shown in fig. 5, the present embodiment designs a fin-type EAFin-LDMOS device with an electron accumulation effect, which includes a source P + region 1, a source N + region 2, a P-body3, a drift region 4, a drain N + region 5, a gate oxide layer 6, a drain P + region 7 of a control structure, a drain N + region 8 of a control structure, a drift region 9 of a control structure, a buried oxide layer 10, a substrate 11, a gate P + region 12, a gate P-body13, and a surface gate oxide layer 16.
On the basis of the structure of the embodiment 1, a gate oxide layer is additionally arranged on the upper surface of the P-body3 between the source N + region 2 and the drift region 4 and is connected with a gate, so that an electronic channel is increased when the forward conduction is carried out, and the specific on-resistance is further reduced. Wherein the gate oxide layer has a thickness of 0.1 μm in the x-direction, a length of 1 μm in the y-direction, and a length of 1 μm in the z-direction.
Example 5:
as shown in fig. 6 and fig. 7, the present embodiment designs a fin-type EAFin-LDMOS device with electron accumulation effect, which includes a source P + region 1, a source N + region 2, a P-body3, a drift region 4, a drain N + region 5, a gate oxide layer 6, a drain P + region 7 of a control structure, a drain N + region 8 of a control structure, a drift region 9 of a control structure, a buried oxide layer 10, a substrate 11, a gate P + region 12, a gate P-body13, and a drain P + region 17.
On the basis of the structure of embodiment 1, the drain P + region 7 of the control structure originally located inside the gate oxide layer 6 is extended to the outside of the gate oxide layer 6, and a drain P + region 17 is formed, so that the drain N + region 5 is in direct contact with the drain P + region 17. Wherein the size and doping concentration of the drain P + region 17 can be varied according to the actual situation.
Simulation experiment:
the simulation comparison of the conventional SOI-LDMOS and the novel EAFin-LDMOS of the example 1 of the invention is carried out by using Sentaurus simulation software, and the simulation parameters of the two structures are consistent in the simulation process, wherein the total thickness of the drift region is 3 mu m, the distance between the drain electrode and the P-body is 7.5 mu m, the ambient temperature is 300K, and the doping concentration N of the drift region is NdThe doping concentration of the grid electrode P + region, the thickness of the oxidation isolation layer, the thickness of the LDMOS structure and the thickness of the control structure in the Z direction can be adjusted.
TABLE 1 basic structural parameters of two devices
| Conventional SOI-LDMOS | EAFin-LDMOS with novel structure | |
| Drift region length in X direction (mum) | 3 | 3 |
| Drift region length in Y direction (mum) | 7.5 | 7.5 |
| Device length in Z-direction (μm) | 1 | 1 |
| Thickness of gate oxide layer (mum) | 0.1 | 0.1 |
| Controlling the thickness of the structure (mum) | - | 0.1 |
| Length of drain P + region (mum) of control structure in X direction | - | 0.6 |
| Length of drain P + region (mum) of control structure in Y direction | - | 0.5 |
| Doping concentration (cm) of drift region-3) | 3.5×1015 | 4.0×1015 |
| Doping concentration (cm) of drain P + region-3) | - | 1.0×1019 |
FIG. 8 shows that the drift region concentration is 2X 10 at room temperature when T is 300K15cm-3To 4.5X 1015cm-3And comparing the voltage endurance of the conventional LDMOS (CON-LDMOS) with that of the SOI-LDMOS device (EAFin-LDMOS) with the new structure in an avalanche breakdown state. The data results from the Sentaurus simulation are further plotted by the Origin tool in a comparison graph as shown in fig. 8, and it can be seen that: in the concentration interval of the drift region, the breakdown voltage of the CON-LDMOS shows a trend of increasing first and decreasing along with the increase of the concentration of the drift region, and the breakdown voltage of the EAFin-LDMOS shows a trend of increasing, wherein the CON-LDMOS is at 3.5 multiplied by 1015cm-3Where it reaches the maximum value, EAFin-LDMOS is at 4 x 1015cm-3Where it reaches a maximum value.
FIG. 9 shows the variation of drain current with drain voltage for the CON-LDMOS device and the EAFin-LDMOS device under different doping concentrations of the drift region. It can be seen from FIG. 9 that the drain current of the EAFin-LDMOS device is much larger than that of the CON-LDMOS device at the same drain voltage, so that it can be concluded that the specific on-resistance of the EAFin-LDMOS device is lower than that of the CON-LDMOS device.
FIG. 10 is a graph showing the relationship between V and VGS＝10V、VDSThe doping concentration of the drift region is 3.5 × 10 at 0V15cm-3The electron density distribution of the drift region of the CON-LDMOS and the doping concentration of the drift region are 4 multiplied by 1015cm-3The EAFin-LDMOS is close to the electron density distribution condition of the drift region at the outer side of the gate oxide layer. From FIG. 10, it can be seen that the electron density of the EAFin-LDMOS near the drift region outside the gate oxide layer is 1.9 × 1017cm-3The drift region electron density of CON-LDMOS is 3.5 × 1015cm-3At this time, the electron density of the EAFin-LDMOS is much larger than that of the drift region of the CON-LDMOS.
FIG. 11 shows example 1 of the present invention at VGS＝10V、VDSWhen 1V and Y are 5 μm, the doping concentration of the drift region is 3.5 × 1015cm-3CON-LDMOS of(left) and drift region doping concentration of 4X 1015cm-3The EAFin-LDMOS (right) is close to the electron current density distribution condition at the section of the drift region outside the gate oxide layer. The electron current density of the drift region of CON-LDMOS (left) in FIG. 11 is 4.5 × 102A/cm2The electron current density of the drift region of EAFin-LDMOS (right) close to the outer side of the gate oxide layer is 8.2 multiplied by 103A/cm2. In addition, the drift region of the EAFin-LDMOS close to the outer side of the gate oxide layer is the position indicated by the arrow of the EAFin-LDMOS in FIG. 11.
FIG. 12 shows example 1 of the present invention at VGS＝10V、VDSThe doping concentration of the drift region is 3.5 multiplied by 10 when the value is 1V15cm-3The doping concentration of the CON-LDMOS and the drift region is 4 multiplied by 1015cm-3The EAFin-LDMOS is close to the electron current density distribution condition of a drift region at the outer side of a gate oxide layer along the Y-axis direction. As can be seen from FIG. 12, the electron current density of the EAFin-LDMOS near the drift region outside the gate oxide is 8.2 × 103A/cm2Electron current density 4.5 × 10 larger than that of CON-LDMOS2A/cm2。
FIG. 13 shows the EAFin-LDMOS device of embodiment 1 of the present invention and the conventional SOI-LDMOS device having a drift region with a doping concentration of 2 × 1015cm-3To 4.5X 1015cm-3Comparative graph of specific on-resistance between. Fig. 13 shows that the drift region concentration is from 2 × 10 at room temperature T300K15cm-3To 4.5X 1015cm-3In the meantime, the specific on-resistance of the conventional LDMOS (CON-LDMOS) and the SOI-LDMOS device (EAFin-LDMOS) with the new structure are compared in the forward on state. It can be seen from fig. 13 that the specific on-resistance of the CON-LDMOS showed a rapid decrease with increasing concentration of the drift region, with a final value close to 6; in addition, the specific on-resistance of the EAFin-LDMOS generally shows a descending trend along with the increase of the concentration of the drift region, but the influence of the concentration of the drift region in a range on the specific on-resistance of the EAFin-LDMOS is not great, because the drift region in the control structure has an electron accumulation effect on the drift region in the LDMOS structure when the forward conduction is carried out, the electron concentration in the LDMOS structure close to the oxidation isolation layer is great, namely, the doping concentration is greatThe specific on-resistance of the device is greatly reduced, and the variation of the specific on-resistance of the EAFin-LDMOS in the concentration range along with the concentration of the drift region is smaller.
TABLE 2 FOM figure of merit for two devices at different drift region doping concentrations
FIG. 14 shows the EAFin-LDMOS device of embodiment 1 of the present invention and the conventional SOI-LDMOS device having a drift region with a doping concentration of 2 × 1015cm-3To 4.5X 1015cm-3Baliga figure of merit FOM comparison between. Fig. 14 shows that the drift region concentration is from 2 × 10 at room temperature T300K15cm-3To 4.5X 1015cm-3In the meantime, the Baliga figure of merit (FOM) of the conventional LDMOS (CON-LDMOS) and the SOI-LDMOS device (EAFin-LDMOS) with the new structure are compared. It can be seen from FIG. 14 that FOM of the CON-LDMOS device rises first and then falls to 3.5 × 1015cm-3A maximum of 3.4MW/cm is obtained2While the FOM of the EAFin-LDMOS device is at 4 x 1015cm-3A maximum of 23MW/cm is obtained2Comparing the two structures, the FOM of the EAFin-LDMOS is much higher than that of the CON-LDMOS.
FIG. 15 is a distribution diagram of the voltage along the Y-axis of the control structure of the EAFin-LDMOS device in accordance with embodiment 1 of the present invention. FIG. 15 is a graph of voltage distribution along the Y-axis for the control structure of the new structure EAFin-LDMOS device; it can be seen from fig. 15 that the potentials of the gate and the drift region in the control structure are substantially equal, which enables a large number of electrons to be accumulated in the P-body and the drift region outside the gate oxide layer when the device is turned on, and reduces the specific on-resistance of the device.
An equivalent circuit of the EAFin-LDMOS device of embodiment 1 of the present invention is shown in fig. 16.
The main process flow of the fin-type EAFin-LDMOS device with the electron accumulation effect designed in embodiment 1 of the present invention is shown in fig. 17, and the specific implementation method thereof includes: firstly, processes such as ion implantation, diffusion and the like are adopted on an SOI (silicon on insulator) silicon chip to complete a P-body, a drain N + region and a drain P + region of a control structure of the novel EAFin-LDMOS; then, forming a longitudinal gate oxide layer by oxidation, and forming a gate P + region in doping; oxidizing again to form a surface gate oxide layer; then depositing a layer of silicon material on the surface of the device, and then passing through a doped layer source electrode N + region, a source electrode P + region and a drain electrode N + region; and finally, punching and depositing a drain metal contact on the right upper corner of the etching oxidation isolation layer.
Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.
Claims (9)
1. A fin-type EAFin-LDMOS device with an electron accumulation effect is characterized in that the device is divided into:
1) a device upper portion comprising: the gate oxide layer (6), the outer part of the gate oxide layer (6) and the inner part of the gate oxide layer (6);
outer part of the gate oxide (6): the source electrode P + region (1), the source electrode N + region (2), the P-body (3), the drift region (4) and the drain electrode N + region (5) are arranged from left to right in sequence; the source P + region (1) and the source N + region (2) are positioned in the upper left region of the whole device and are surrounded by the P-body (3); the right side of the P-body (3) is in contact with the left side of the drift region (4); the drain N + region (5) is positioned in the upper right region of the whole device, and the left side and the lower side of the drain N + region are surrounded by the drift region (4);
the inner part of the gate oxide (6): a grid P + region (12), a grid P-body (13), a drift region (9) of the control structure, a drain N + region (8) of the control structure and a drain P + region (7) of the control structure are arranged from left to right in sequence; the right side of the grid electrode P + region (12) is contacted with the left side of the grid electrode P-body (13); the right side of the gate P-body (13) is in contact with the left side of the drift region (9) of the control structure; the drain N + region (8) of the control structure is positioned in the upper right region of the device and is surrounded by the drift region (9) of the control structure, and the upper right corner of the drain N + region (8) of the control structure also surrounds the drain P + region (7) of the control structure;
2) device bottom part: consists of a substrate (11) located below the upper part of the device.
2. The fin-EAFin-LDMOS device of claim 1, further comprising adding a P-type region or super junction P-type region in the drift region (4) or drift region (9) of the control structure.
3. The fin EAFin-LDMOS device of claim 1, wherein the gate oxide (6) outer portion further comprises: and the surface gate oxide layer (16) is positioned on the upper surface of the P-body (3) between the source N + region (2) and the drift region (4) and is connected with the gate P + region (12).
4. The fin-type EAFin-LDMOS device of claim 1, wherein the drain P + region (7) of the control structure is extended to an outer portion of the gate oxide layer (6) to form a drain P + region (17) such that the drain N + region (5) is in direct contact with the drain P + region (17).
5. The fin-type EAFin-LDMOS device of any of claims 1-4, wherein the Z-direction width and thickness of the inner portion of the gate oxide layer (6) are varied as desired.
6. The fin-type EAFin-LDMOS device of any one of claims 1-4, which is an N-type LDMOS device and can be correspondingly switched to a P-type LDMOS device.
7. The fin-type EAFin-LDMOS device of any one of claims 1-4, wherein the device structure is suitable for VDMOS devices and IGBT devices.
8. The fin-type EAFin-LDMOS device according to any of claims 1-4, wherein the device structure is capable of exchanging the structure of the inner portion and the outer portion of the gate oxide (6) such that the LDMOS device structure is located inside the gate oxide (6) and the gate control structure is located outside the gate oxide (6).
9. The fin-EAFin-LDMOS device of any of claims 1-4, further comprising: the device middle part, which consists of a buried oxide layer (10), is located below the device upper part and above the device bottom part.
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