CN113097090A - Method for measuring thickness of three-dimensional memory channel hole thin film - Google Patents
Method for measuring thickness of three-dimensional memory channel hole thin film Download PDFInfo
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- CN113097090A CN113097090A CN202110342133.7A CN202110342133A CN113097090A CN 113097090 A CN113097090 A CN 113097090A CN 202110342133 A CN202110342133 A CN 202110342133A CN 113097090 A CN113097090 A CN 113097090A
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- H01—ELECTRIC ELEMENTS
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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Abstract
The embodiment of the application discloses a method for measuring the thickness of a three-dimensional memory channel hole thin film, which comprises the following steps: providing a test sample, wherein the test sample comprises a semiconductor substrate, a semiconductor device structure positioned on the semiconductor substrate and a covering layer covering the semiconductor device structure; the semiconductor device structure comprises a target structure and an enclosing structure, wherein the enclosing structure encloses the target structure along a direction parallel to the semiconductor substrate; forming a dicing opening in a side of the cover layer of the test sample, the dicing opening exposing the semiconductor device structure; removing the surrounding structure in the semiconductor device structure through the cutting opening by using etching liquid so as to expose the target structure; thinning the test sample along a direction parallel to the semiconductor substrate through the cutting opening to obtain a TEM sample; a thickness measurement is made of the target structure in the TEM sample.
Description
Technical Field
The embodiment of the application relates to the field of semiconductor manufacturing, in particular to a method for measuring the thickness of a three-dimensional memory channel hole thin film.
Background
Transmission Electron Microscopes (TEMs) are widely used for measuring the thickness of semiconductor microstructures due to their extremely high resolving power. The special illumination and optical system of TEM can focus the electrons accelerated by electric field and project them on very thin sample. The transmitted electron beams with the structural and composition information of the sample finally pass through an imaging system, and the microscopic appearance of the sample can be clearly shown.
At present, the thickness of a thin film in a three-dimensional memory is often measured by taking a TEM image after being sectioned by a Focused Ion Beam (FIB). However, when the thickness measurement of the target observation object is performed using the TEM image, the thickness measurement is affected by other structures around the target observation object, so that the accuracy and efficiency of the measurement are further reduced.
Disclosure of Invention
In view of the above, embodiments of the present application provide a method for measuring a thickness of a three-dimensional memory trench hole film to solve at least one problem in the prior art.
In order to achieve the above purpose, the technical solution of the embodiment of the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a method for measuring a thickness of a three-dimensional memory trench hole thin film, where the method includes:
providing a test sample, wherein the test sample comprises a semiconductor substrate, a semiconductor device structure positioned on the semiconductor substrate and a covering layer covering the semiconductor device structure; the semiconductor device structure comprises a target structure and an enclosing structure, wherein the enclosing structure encloses the target structure along a direction parallel to the semiconductor substrate;
forming a dicing opening in a side of the cover layer of the test sample, the dicing opening exposing the semiconductor device structure;
removing the surrounding structure in the semiconductor device structure by using etching liquid through the cutting opening to expose the target structure;
thinning the test sample along a direction parallel to the semiconductor substrate through the cutting opening to obtain a TEM sample;
a thickness measurement is made of the target structure in the TEM sample.
In an alternative embodiment, said making a thickness measurement of said target structure on said TEM sample comprises:
obtaining a TEM image of the target structure by a transmission electron microscope imaging technology;
performing a thickness measurement on the target structure on the TEM image to obtain thickness data of the target structure.
In an alternative embodiment, the semiconductor device structure includes a stack structure on the semiconductor substrate and a channel hole through the stack structure; the target structure surrounds the channel hole in a direction parallel to the semiconductor substrate.
In an alternative embodiment, the stacked structure is formed by alternately stacking insulating layers and gate layers; the target structure and the surrounding structure constitute the gate layer.
In an alternative embodiment, forming a dicing opening in a side of the cover layer of the test sample, the dicing opening exposing the semiconductor device structure, comprises:
forming a dicing opening on a side of the cap layer of the test sample, the dicing opening exposing at least the gate layer in the semiconductor device structure.
In an alternative embodiment, the TEM sample comprises at least one gate layer.
In an alternative embodiment, the target structure is an aluminum oxide layer; the surrounding structure comprises a titanium nitride layer and a tungsten layer.
In an alternative embodiment, the etching liquid includes an aqueous hydrogen peroxide solution, or a mixed solution of hydrogen peroxide and ammonia.
In an alternative embodiment, forming the cut openings is performed using an automated milling process or a focused ion beam technique.
In an alternative embodiment, the thinning of the test sample is performed using a focused ion beam technique.
In an alternative embodiment, the thickness of the TEM sample is in the range of 60-70 nm.
The embodiment of the application discloses a method for measuring the thickness of a three-dimensional memory channel hole thin film, which comprises the following steps: providing a test sample, wherein the test sample comprises a semiconductor substrate, a semiconductor device structure positioned on the semiconductor substrate and a covering layer covering the semiconductor device structure; the semiconductor device structure comprises a target structure and an enclosing structure, wherein the enclosing structure encloses the target structure along a direction parallel to the semiconductor substrate; forming a dicing opening in a side of the cover layer of the test sample, the dicing opening exposing the semiconductor device structure; removing the surrounding structure in the semiconductor device structure through the cutting opening by using etching liquid so as to expose the target structure; thinning the test sample along a direction parallel to the semiconductor substrate through the cutting opening to obtain a TEM sample; a thickness measurement is made of the target structure in the TEM sample. The embodiment of the application is right before the test sample is thinned, the surrounding structure surrounding the target structure is removed through etching liquid. Therefore, no matter when the sample is thinned or the thickness is measured, the surrounding structure surrounding the target structure cannot influence the thickness measurement of the target structure, so that the thickness measurement data can be obtained more quickly and accurately.
Drawings
Fig. 1 is a schematic flow chart illustrating an implementation of a method for measuring a thickness of a three-dimensional memory trench hole film according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a local semiconductor device structure provided in an embodiment of the present application;
FIG. 3 is a TEM image of a target structure and surrounding structures provided by embodiments of the present application;
FIG. 4 is an SEM image of a test sample with cut openings provided by an embodiment of the present application;
FIG. 5 is a first SEM image of a TEM sample provided in an embodiment of the present application;
FIG. 6 is a second SEM image of a TEM sample provided in an example of the present application;
FIG. 7 is a TEM image of a TEM sample provided by an embodiment of the present application;
FIG. 8 is a schematic illustration of thickness measurements of an alumina film of TEM samples provided by examples herein;
fig. 9 is thickness measurement data provided in an embodiment of the present application.
Detailed Description
Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Fig. 1 is a schematic flow chart illustrating an implementation of a method for measuring a thickness of a three-dimensional memory trench hole film according to an embodiment of the present disclosure. Referring to fig. 1, the method includes the steps of:
In an embodiment of the present application, the semiconductor device structure includes a stack structure on the semiconductor substrate and a channel hole penetrating the stack structure; the target structure surrounds the channel hole in a direction parallel to the semiconductor substrate. The semiconductor substrate may be an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The channel hole sequentially comprises a blocking layer, a charge trap layer, a tunneling layer and a channel layer along the radial direction of the channel hole inwards. The material of the barrier layer can be silicon oxide; the material of the charge trap layer can be silicon nitride; the tunneling layer can be made of silicon oxide; the material of the channel layer may be a conductive material, such as polysilicon.
Here, the test sample may be a chip (chip), and the cover layer is an encapsulation material layer of the chip. In some embodiments, the test sample may also be a die (die), and the cover layer is a dielectric layer covering the semiconductor device structure.
In the embodiment of the application, the stacked structure is formed by alternately stacking insulating layers and gate electrode layers; the target structure and the surrounding structure constitute the gate layer. Here, the target structure is a dielectric layer, and in practical application, the material of the dielectric layer may be aluminum oxide; the surrounding structure comprises an adhesion layer and a conductive layer, wherein in practical application, the adhesion layer can be made of titanium nitride, and the conductive layer can be made of tungsten. The material of the insulating layer may be silicon oxide. In practical applications, the insulating Layer, the dielectric Layer, the adhesion Layer and the conductive Layer may be formed by a Deposition process, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma-Enhanced CVD (PECVD), sputtering (sputtering), Metal-Organic Chemical Vapor Deposition (MOCVD) or Atomic Layer Deposition (ALD).
Fig. 2 is a schematic diagram of a local semiconductor device structure provided in an embodiment of the present application, and it should be noted that fig. 2 is a cross-sectional view taken along a direction perpendicular to the semiconductor substrate. As shown in fig. 2, the semiconductor device structure includes a stack structure 200 on the semiconductor substrate and a channel hole 210 penetrating the stack structure 200; the stack structure 200 is formed by alternately stacking insulating layers 220 and gate layers 230; the target structure 231 and the surrounding structure 232 constitute the gate layer 230; the target structure 231 surrounds the channel hole 210 in a direction parallel to the semiconductor substrate. The surrounding structure 232 includes an adhesion layer 2321 and a conductive layer 2322. In some embodiments, the stacked structure 200 herein may be a structure of a step region (stir Case).
The gate layer 230 is formed by forming a dielectric layer (the target structure 231), forming an adhesion layer 2321, and forming a conductive layer 2322, where the conductive layer 2322 is disposed in a direction parallel to the substrate, and the conductive layer 2322 is disposed in the dielectric layer (the target structure 231) and the adhesion layer 2321. Since the adhesion layer has a small thickness and a relatively rough boundary, the adhesion layer does not maintain a complete and independent profile after the tungsten layer is formed. In measuring the thickness of a target structure (dielectric layer), the accuracy and repeatability of the thickness measurement data of the target structure can be affected.
Fig. 3 is a TEM image of a target structure and a surrounding structure provided in an embodiment of the present application, and it should be noted that fig. 3 is a plane TEM image along a direction parallel to the semiconductor substrate. As shown in fig. 3, the target structure 231 surrounds the channel hole 210, and the surrounding structure (the attachment layer 2321 and the conductive layer 2322) surrounds the target structure 231. Here, in fig. 2, inside the dotted line is a trench hole 210. It can be seen that the boundary of the adhesion layer 2321 is rough, and that the boundary between the target structure 231 and the adhesion layer 2321 is difficult to distinguish under the influence of the contrast of the conductive layer 2322.
In an embodiment of the present application, a cut opening is formed at a side of a cap layer of the test sample by an Auto-polish (Auto-polish) process or a Focused Ion Beam (FIB) process, the cut opening exposing the semiconductor device structure. Here, the cutting opening exposes a stacked structure in the semiconductor device structure. It should be noted that, since the target structure is located in the gate layer in the stacked structure, when forming the cut opening on the side of the cover layer of the test sample, the cut opening needs to expose the gate layer in the stacked structure. In some embodiments, to ensure structural integrity of the semiconductor device, the cut-out opening is preferably formed by FIB techniques.
Fig. 4 is an SEM image of a test sample with a cut opening provided in an embodiment of the present application, and as shown in fig. 4, a cut opening is formed by FIB technology, which exposes the semiconductor device structure.
And 103, removing the surrounding structure in the semiconductor device structure through the cutting opening by using etching liquid so as to expose the target structure.
In the embodiment of the present application, the test specimen with the cut opening is placed in an etching bath, an etching liquid is injected into the etching bath, the etching liquid submerges the test specimen, and the test specimen is immersed at a temperature of about 70 ℃ for 10 to 30 minutes. And the etching liquid etches the grid layer exposed by the cutting opening so as to remove the surrounding structure in the grid layer. It should be noted that, in the embodiment of the present application, the etching liquid can simultaneously remove the titanium nitride layer and the tungsten layer.
Here, the etching liquid includes an aqueous hydrogen peroxide solution, or a mixed solution of hydrogen peroxide and ammonia water. When the etching liquid is hydrogen peroxide solution, the concentration of the hydrogen peroxide solution is 30%. When the etching liquid is a mixed solution of hydrogen peroxide and ammonia water, the concentration of the hydrogen peroxide solution is 30% and the concentration of the ammonia water solution is 25% -28%. The volume ratio of the hydrogen peroxide to the ammonia water in the mixed solution is 8:1-10: 1.
And 104, thinning the test sample along a direction parallel to the semiconductor substrate through the cutting opening to obtain a TEM sample.
In the present example, the test sample was thinned in a direction parallel to the semiconductor substrate using FIB techniques to obtain TEM samples in the thickness range of 60-70 nm. Because the target structure is located in the gate layer, when the test sample is thinned, it is required to ensure that at least the gate layer is included in the thinned TEM sample. Here, the gate layer may be a single layer or a plurality of layers. It should be noted that, in order to obtain a TEM sample with a specific number of gate layers, after forming a cut opening, the position of the target structure or the position near the target structure may be marked, and then the test sample is thinned in the subsequent thinning process according to the mark, so as to ensure that the gate layers with the corresponding number of layers are located in the TEM sample.
Fig. 5 and 6 are SEM images of TEM samples provided in an embodiment of the present application, where fig. 5 is taken at a stage tilt angle of 0 °, and fig. 6 is taken at a stage tilt angle of 58 °.
In the embodiment of the application, a TEM image of the target structure is obtained by a transmission electron microscope imaging technology, and the target structure of the TEM image is measured to obtain thickness data of the target structure.
Fig. 7 is a TEM image of a TEM sample provided in an embodiment of the present application, and the arrow in fig. 7 indicates the boundary of the target structure. As shown in fig. 7, the boundary of the target structure in the TEM sample obtained by the method provided by the embodiment of the present application is clear, and the surrounding structure is removed, so that the surrounding structure no longer affects the thickness measurement of the target structure.
Fig. 8 is a schematic diagram illustrating thickness measurement of an alumina thin film of a TEM sample provided in an embodiment of the present application. The length of the dotted line between two parallel dotted lines in the dotted line of the "i" in fig. 8 is the thickness of the target structure.
Fig. 9 is thickness measurement data provided in an embodiment of the present application. The thickness fluctuation of the measured target structure is small, the average thickness of the measured target structure is 2.79nm, and the standard deviation is 0.25 nm.
The embodiment of the application discloses a method for measuring the thickness of a three-dimensional memory channel hole thin film, which comprises the following steps: providing a test sample, wherein the test sample comprises a semiconductor substrate, a semiconductor device structure positioned on the semiconductor substrate and a covering layer covering the semiconductor device structure; the semiconductor device structure comprises a target structure and an enclosing structure, wherein the enclosing structure encloses the target structure along a direction parallel to the semiconductor substrate; forming a dicing opening in a side of the cover layer of the test sample, the dicing opening exposing the semiconductor device structure; removing the surrounding structure in the semiconductor device structure through the cutting opening by using etching liquid so as to expose the target structure; thinning the test sample along a direction parallel to the semiconductor substrate through the cutting opening to obtain a TEM sample; a thickness measurement is made of the target structure in the TEM sample.
The embodiment of the application is right before the test sample is thinned, the surrounding structure surrounding the target structure is removed through etching liquid. Therefore, the surrounding structure can not influence the thickness measurement of the target structure, and the thickness measurement data can be obtained more quickly and accurately.
It should be appreciated that reference throughout this specification to "in an embodiment" or "in some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrase "in an embodiment of the present application" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A method for measuring the thickness of a three-dimensional memory channel hole thin film is characterized by comprising the following steps:
providing a test sample, wherein the test sample comprises a semiconductor substrate, a semiconductor device structure positioned on the semiconductor substrate and a covering layer covering the semiconductor device structure; the semiconductor device structure comprises a target structure and an enclosing structure, wherein the enclosing structure encloses the target structure along a direction parallel to the semiconductor substrate;
forming a dicing opening in a side of the cover layer of the test sample, the dicing opening exposing the semiconductor device structure;
removing the surrounding structure in the semiconductor device structure through the cutting opening by using etching liquid so as to expose the target structure;
thinning the test sample along a direction parallel to the semiconductor substrate through the cutting opening to obtain a TEM sample;
a thickness measurement is made of the target structure in the TEM sample.
2. The method of claim 1, wherein said measuring a thickness of said target structure on said TEM sample comprises:
obtaining a TEM image of the target structure by a transmission electron microscope imaging technology;
performing a thickness measurement on the target structure on the TEM image to obtain thickness data of the target structure.
3. The method for measuring the thickness of a three-dimensional memory channel hole film according to claim 1,
the semiconductor device structure comprises a stacked structure positioned on the semiconductor substrate and a channel hole penetrating through the stacked structure; the target structure surrounds the channel hole in a direction parallel to the semiconductor substrate.
4. The method for measuring the thickness of a three-dimensional memory channel hole film according to claim 3,
the stacked structure is formed by alternately stacking insulating layers and gate electrode layers; the target structure and the surrounding structure constitute the gate layer.
5. The method of claim 4, wherein forming a cut opening on a side of the test sample's cap layer, the cut opening exposing the semiconductor device structure, comprises:
forming a dicing opening on a side of the cap layer of the test sample, the dicing opening exposing at least the gate layer in the semiconductor device structure.
6. The method for measuring the thickness of a three-dimensional memory channel hole film according to claim 4,
the TEM sample comprises at least one gate layer.
7. The method for measuring the thickness of a three-dimensional memory channel hole film according to any one of claims 1 to 6,
the target structure is an aluminum oxide layer; the surrounding structure comprises a titanium nitride layer and a tungsten layer.
8. The method for measuring the thickness of a three-dimensional memory channel hole film according to any one of claims 1 to 6,
the etching liquid comprises hydrogen peroxide solution or mixed solution of hydrogen peroxide and ammonia water.
9. The method for measuring the thickness of a three-dimensional memory channel hole film according to any one of claims 1 to 6,
forming the cutting opening is performed using an automated milling process or a focused ion beam technique.
10. The method for measuring the thickness of a three-dimensional memory channel hole film according to any one of claims 1 to 6,
and thinning the test sample by adopting a focused ion beam technology.
11. The method for measuring the thickness of a three-dimensional memory channel hole film according to any one of claims 1 to 6,
the thickness of the TEM sample ranges from 60 to 70 nm.
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| CN117038674A (en) * | 2023-10-10 | 2023-11-10 | 合肥新晶集成电路有限公司 | Semiconductor structure and preparation method thereof |
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