CN113078063B - Structure for reducing heterojunction bipolar transistor b-c junction capacitance and manufacturing method - Google Patents
Structure for reducing heterojunction bipolar transistor b-c junction capacitance and manufacturing method Download PDFInfo
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- CN113078063B CN113078063B CN202110240235.8A CN202110240235A CN113078063B CN 113078063 B CN113078063 B CN 113078063B CN 202110240235 A CN202110240235 A CN 202110240235A CN 113078063 B CN113078063 B CN 113078063B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 46
- 239000010953 base metal Substances 0.000 claims abstract description 28
- 238000002161 passivation Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000011248 coating agent Substances 0.000 claims abstract description 12
- 238000000576 coating method Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 18
- 238000011161 development Methods 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 238000001816 cooling Methods 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims 1
- 230000010355 oscillation Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 1
- 239000010931 gold Substances 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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Abstract
The invention discloses a structure for reducing heterojunction bipolar transistor b-c junction capacitance and a manufacturing method thereof, when base metal is manufactured, first coating a first photoresist on a chip structure, exposing and developing to form a first window, then coating a second photoresist, reducing the line width of the first window through a micro and reflow process, etching a passivation layer in the first window to form a first opening, removing the photoresist, coating a third photoresist, exposing and developing to form a second window positioned on the first opening, enabling the line width of the second window to be larger than that of the first opening, then depositing gold to form the base metal in the second window and the first opening, and removing the photoresist. The invention forms the base metal structure with the bottom line width smaller than the top line width, reduces the b-c junction area under the condition of not increasing the base resistance, achieves the effect of reducing the b-c junction capacitance, and further improves the highest oscillation frequency.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a structure for reducing heterojunction bipolar transistor b-c junction capacitance and a manufacturing method thereof.
Background
With the development of HBT technology, higher demands are being placed on high frequency parameters. The high frequency parameters are mainly two, namely current gain cut-off frequency (ft); the second is the highest oscillation frequency (fmax). The highest oscillation frequency (fmax) is inversely proportional to the product of the base resistance (Rb) and the b-c junction capacitance (Cbc), and therefore in order to increase the highest oscillation frequency (fmax), the b-c junction capacitance (Cbc) and the base resistance (Rb) must be reduced. The traditional method for reducing the b-c junction capacitance (Cbc) is to reduce the base metal Width (WB) directly by a photoetching method so as to reduce the BC junction area (Abc) and achieve the effect of reducing the b-c junction capacitance (Cbc); however, a decrease in the base metal Width (WB) results in an increase in the base resistance Rb, which adversely affects both the current gain cutoff frequency (ft) and the maximum oscillation frequency (fmax) of the device.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a structure for reducing the b-c junction capacitance of a heterojunction bipolar transistor and a manufacturing method thereof.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a manufacturing method for reducing heterojunction bipolar transistor b-c junction capacitance is characterized in that base metal is manufactured on a chip structure which is subjected to partial manufacture procedure, the chip structure which is subjected to partial manufacture procedure comprises an epitaxial layer and a passivation layer arranged on the epitaxial layer, and the manufacturing method of the base metal comprises the following steps:
1) coating a first photoresist with the thickness of 0.5-1.0 mu m on the chip structure, and forming a first window with a first line width through exposure and development;
2) coating a second photoresist with the thickness of 0.3-0.5 μm, and heating at 85-105 ℃ for 1-3 min;
3) after the cleaning is carried out by using deionized water at the temperature of 90-120 ℃, the line width of the first window is reduced to a second line width;
4) baking at 120-150 ℃ for 30-60 min, and naturally cooling, wherein the line width of the first window is reduced to a third line width;
5) etching and removing the passivation layer in the first window to obtain a first opening with a third line width, and removing the light resistance;
6) coating a third photoresist, forming a second window on the first opening through exposure and development, wherein the line width of the second window is larger than that of the first opening;
7) depositing metal to form base metal in the second window and the first opening, and removing the photoresist.
Optionally, the chip structure with the completed partial process further includes an emitter structure disposed on the epitaxial layer, the emitter structure includes an emitter mesa and an emitter metal, and the passivation layer is deposited after the emitter metal.
Optionally, the passivation layer is made of SiN or SiO 2 The thickness is 20-80 nm.
Optionally, the first photoresist is a positive photoresist AR80, and the second photoresist is an R200 photoresist.
Optionally, the line width of the second window is greater than the line width of the first opening by more than 0.4 μm.
Optionally, the base metal is Pt/Ti/Pt/Au/Ti sequentially deposited by an evaporation process, and the thickness of each metal component is 10-500 nm.
Optionally, the first line width is 0.4 to 0.5 μm, the second line width is 0.3 to 0.35 μm, and the third line width is 0.22 to 0.28 μm.
Optionally, in step 1), the first photoresist is exposed by using an I-line lithography machine, and then developed by using a TMAH developer with a concentration of 2% to 2.5%.
The structure for reducing the b-c junction capacitance of the heterojunction bipolar transistor manufactured by the manufacturing method is characterized in that: the emitter structure is arranged on the epitaxial layer, and the passivation layer covers the epitaxial layer and the emitter structure; the passivation layer is provided with a first opening on the epitaxial layer, the line width of the first opening is 0.22-0.28 mu m, and the base metal is arranged in the first opening and extends to the surface of the passivation layer covering two sides of the first opening.
The invention has the beneficial effects that:
1) through the arrangement of the double-line-width base metal, under the condition that the base resistance Rb is not increased, the b-c junction area (Abc) is reduced, the effect of reducing the b-c junction capacitance (Cbc) is achieved, and therefore the highest oscillation frequency (fmax) is improved;
2) the line width of a photoresist window formed by the existing process is reduced through the process of shrinking and reflowing the second photoresist, so that the bottom line width of the base metal with small size can be obtained, the top line width of the base metal is not changed, the size controllability is strong, and the method is suitable for practical production and application.
Drawings
FIG. 1 is a process flow diagram of example 1;
FIG. 2 is a schematic diagram of the heterojunction bipolar transistor structure obtained in example 1;
fig. 3 is a schematic diagram of a heterojunction bipolar transistor structure obtained by a comparative example.
Detailed Description
The invention is further explained below with reference to the figures and the specific embodiments. The drawings are only schematic and can be easily understood, and the specific proportion can be adjusted according to design requirements. The definitions of the top and bottom relationships of the relative elements and the front and back sides of the figures described herein are understood by those skilled in the art to refer to the relative positions of the components and thus all of the components may be flipped to present the same components and still fall within the scope of the present disclosure.
Example 1
Referring to the process flow diagram of fig. 1, a method for reducing the b-c junction capacitance of a heterojunction bipolar transistor is specifically described by taking the formation of a base metal with a bottom line width of about 0.25 μm as an example:
first, a chip structure including an epitaxial layer 1, an emitter structure (an emitter mesa 2 and an emitter metal 3) and a passivation layer 4 is provided after partial processing is completed. The above structure is processed by a known process, wherein after the emitter metal 3 is formed, 1 layer of 20-80 nm SiN or SO is deposited by PVCVD 2 As passivation layer 4, the resulting structure is shown in fig. 1 a;
then, coating a first photoresist 5 with the thickness of 0.5-1.0 μm on the chip structure, wherein the first photoresist 5 is a positive photoresist AR80 (from Tokyo reaction), exposing by using an I-line photoetching machine, and developing by using TMAH (concentration of 2.38%) developing solution to obtain a first window 51 with a first line width a of 0.45 +/-0.05 μm, and the obtained structure is shown as a graph 1 b;
coating a layer of 0.3-0.5 μm second photoresist 6 by spin coating, wherein the second photoresist 6 is R200 photoresist (from Anzhi); then, a hot plate is used for heating reaction (the temperature is 85-105 ℃, the time is 1 min-3 min), after the hot plate is used for baking, the R200 reacts with the first photoresist 5 below the hot plate, a water-insoluble reaction layer with the thickness of 0.05-0.075 mu m is formed and attached to the surface of the first photoresist 5, and the R200 which is not in contact with the first photoresist 5 does not react; deionized water with the temperature of 90-120 ℃ is adopted, R200 is dissolved in water after water washing, the opening area is obvious, and the second photoresist 6 around the first window 51 area forms insoluble substances, so that the first window 51 is reduced to a second line width of 0.3-0.35 mu m; baking by using an oven (at 120-150 ℃ for 30-60 min), wherein the backflow action causes the original trapezoidal photoresist to slightly flow, so that the sharp corner on the surface forms a fillet, and the photoresist at the bottom slightly flows to the side edge by about 0.025 mu m, thereby reducing the first window 51 to a third line width b of 0.25 mu m +/-0.03 mu m after natural cooling, and obtaining a structure as shown in fig. 1 c;
removing the passivation layer 4 in the first window 51 by wet or dry etching, wherein the etching stop method is not limited to grabbing an end point or controlling time, so as to obtain the first opening 41 with the third line width b, and then removing the first photoresist 5 and the second photoresist 6 attached to the first photoresist 5 by using an organic solvent such as NMP, so as to obtain the structure shown in fig. 1 d;
coating a third photoresist 7, wherein the third photoresist can be a positive photoresist or a negative photoresist, forming a second window 71 on the first opening 41 through exposure and development, the second window 71 has a fourth line width c, the fourth line width c is larger than the third line width b, optimally, the first opening 41 is positioned in the middle of the second window 71, the fourth line width c is larger than the third line width b by more than 0.4 μm, and the fourth line width c can be adjusted according to the actual requirement on the base metal width, so that the obtained structure is as shown in fig. 1 e;
and (3) carrying out evaporation on the base metal 8, wherein the used metal components are Pt/Ti/Pt/Au/Ti, the thickness of each metal component is 10-500 nm, the specific thickness is adjusted according to design requirements, then removing the third photoresist 7 to obtain the base metal 8 in contact with the epitaxial layer 1 at the first opening 41, and the structure is shown in figure 1 f.
Referring to fig. 2, the resulting heterojunction bipolar transistor structure comprises an epitaxial layer 1, an emitter structure (emitter mesa 2 and emitter metal 3), a passivation layer 4 and a base metal 8. The emitter electrode platform 2 and the emitter electrode metal 3 are arranged on the epitaxial layer 1, and the passivation layer 4 covers the epitaxial layer 1 and the emitter electrode structure; the passivation layer 4 is provided with a first opening 41 on the epitaxial layer 1, and the base metal 8 is disposed in the first opening 41 and extends to cover the surface of the passivation layer 4 at two sides of the first opening 41, that is, the obtained base metal 8 has a bottom line width b (same as a third line width) and a top line width c (same as a fourth line width). In this embodiment, the base-emitter-base structure (2B1E) is formed, where the distance between the bottom edge and the top edge of the base metal 8 is x (i.e., x is (c-B)/2), the line width of the emitter mesa 2 is d, the distance between the base top metal and the edge of the base mesa is e, the distance between the base bottom metal and the emitter mesa is f, and the B-c junction width is 2(e + c + f-x) + d.
In addition, other conventional subsequent processes are not described in detail.
Comparative example
Referring to fig. 3, a second opening 42 with a line width c is formed directly on the passivation layer 4 by one-step photoresist, and then the base metal 8' is deposited to obtain the structure. In the figure, the bottom and top linewidths of the base metal 8' are the same, both being the same as the top linewidth c of example 1 (without affecting the base resistance Rb); similarly, if the line width of the emitter mesa 2 is d, the distance from the base top metal to the edge of the base mesa is e, and the distance from the base bottom metal to the emitter mesa is f (which affects the reliability of the product, so the comparative example is the same as example 1), the b-c junction width is 2(e + c + f) + d.
It can be seen that, compared with the comparative example, in the embodiment 1, on the premise of not influencing the base resistance Rb, the b-c junction width is reduced by 2x, so that the b-c junction area is reduced, and the effect of reducing the b-c junction capacitance (Cbc) is achieved.
Furthermore, it is expected that the same effect will be obtained for the emitter-base-emitter structure.
The above embodiments are merely provided to further illustrate the structure and the manufacturing method for reducing the junction capacitance of the heterojunction bipolar transistor b-c according to the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention fall within the protection scope of the technical solution of the present invention.
Claims (8)
1. A manufacturing method for reducing heterojunction bipolar transistor b-c junction capacitance is characterized in that: manufacturing base metal on the chip structure which is partially processed; the chip structure with the completed partial manufacture procedure comprises an epitaxial layer, and a passivation layer and an emitter electrode structure which are arranged on the epitaxial layer, wherein the emitter electrode structure comprises an emitter electrode platform and emitter electrode metal, and the passivation layer is deposited behind the emitter electrode metal; the preparation of the base metal comprises the following steps:
1) coating a first photoresist with the thickness of 0.5-1.0 mu m on the chip structure, and forming a first window with a first line width through exposure and development;
2) coating a second photoresist with the thickness of 0.3-0.5 μm, and heating at 85-105 ℃ for 1-3 min;
3) after the cleaning is carried out by using deionized water at the temperature of 90-120 ℃, the line width of the first window is reduced to a second line width;
4) baking at 120-150 ℃ for 30-60 min, and naturally cooling, wherein the line width of the first window is reduced to a third line width;
5) etching and removing the passivation layer in the first window to obtain a first opening with a third line width, and removing the light resistance;
6) coating a third photoresist, forming a second window on the first opening through exposure and development, wherein the line width of the second window is larger than that of the first opening;
7) and depositing metal to form base metal in the second window and the first opening, and removing the photoresist.
2. The method of manufacturing according to claim 1, wherein: the method of manufacturing according to claim 1, wherein: the passivation layer is made of SiN or SiO 2 The thickness is 20-80 nm.
3. The method of manufacturing according to claim 1, wherein: the first photoresist is a positive photoresist AR80, and the second photoresist is an R200 photoresist.
4. The method of manufacturing according to claim 1, wherein: the line width of the second window is larger than the line width of the first opening by more than 0.4 μm.
5. The method of manufacturing according to claim 1, wherein: the base metal is formed by sequentially depositing Pt/Ti/Pt/Au/Ti by an evaporation process, and the thickness of each metal component is 10-500 nm.
6. The method of manufacturing according to claim 1, wherein: the first line width is 0.4-0.5 μm, the second line width is 0.3-0.35 μm, and the third line width is 0.22-0.28 μm.
7. The method of manufacturing according to claim 6, wherein: in the step 1), the first photoresist is exposed by an I-line photoetching machine, and then developed by TMAH developing solution with the concentration of 2% -2.5%.
8. A structure for reducing the b-c junction capacitance of a heterojunction bipolar transistor manufactured by the manufacturing method of any one of claims 1 to 7, wherein: the emitter structure is arranged on the epitaxial layer, and the passivation layer covers the epitaxial layer and the emitter structure; the passivation layer is provided with a first opening on the epitaxial layer, the line width of the first opening is 0.22-0.28 mu m, and the base metal is arranged in the first opening and extends to the surface of the passivation layer covering two sides of the first opening.
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| US5716859A (en) * | 1995-12-22 | 1998-02-10 | The Whitaker Corporation | Method of fabricating a silicon BJT |
| US6444535B1 (en) * | 2001-05-09 | 2002-09-03 | Newport Fab, Llc | Method to reduce emitter to base capacitance and related structure |
| JP2006294700A (en) * | 2005-04-06 | 2006-10-26 | Toshiba Corp | Hetero-junction bipolar transistor |
| CN104900503B (en) * | 2015-04-28 | 2018-05-01 | 厦门市三安集成电路有限公司 | A kind of production method of the T-shaped grid of high ionic mobility transistor |
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