CN113066910B - Blue light semiconductor device and preparation method thereof - Google Patents
Blue light semiconductor device and preparation method thereof Download PDFInfo
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
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- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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Abstract
The invention relates to a blue light semiconductor device and a preparation method thereof, and the blue light semiconductor device comprises a graphical sapphire substrate and an epitaxial lamination layer arranged on the surface of the substrate, wherein the epitaxial lamination layer comprises an n-type layer close to the substrate, an active layer and a p-type layer far away from the substrate, and the epitaxial lamination layer is provided with an etching step which is etched to the n-type layer along the p-type layer; the metal/graphene composite transparent electrode layers which are periodically stacked are arranged on the surface of the p-type layer, the n electrode arranged on the surface of the n-type layer and the p electrode arranged on the surface of the p-type layer; the passivation layer wraps the epitaxial lamination layer, the composite transparent electrode layer, the n electrode and the p electrode, the DBR layer is arranged on the surface of the passivation layer, and the protection layer is arranged on the surface of the DBR layer; the solder balls are respectively connected with the n electrode and the p electrode to the substrate. The device structure and the preparation method thereof provided by the invention improve the light-emitting efficiency of the device, reduce the junction temperature and the void ratio, and the device has good thermal stability and high long-term reliability.
Description
Technical Field
The invention relates to a semiconductor light-emitting element, in particular to a blue light semiconductor device and a preparation method thereof.
Background
Compared with traditional light sources (incandescent lamps and fluorescent lamps), the LED has the advantages of fast response time, low pollution, high light efficiency, long service life, low energy consumption, small volume and the like, so the LED has wide application in various fields such as signal lamps, backlight sources, automobile lamps, common illumination, lasers and the like.
The GaN-based LED with the flip structure has the advantages of low thermal resistance, large current, low packaging cost, close arrangement and the like, the temperature resistance and the reliability of the chip are better than those of a chip with a normal structure and a chip with a vertical structure, the manufacturing cost is moderate, the GaN-based LED with the flip structure can be used for a light source with high power and high reliability, the GaN-based LED with the flip structure is favored by the industry, and the research heat is not reduced so far.
At present, the main factors limiting the GaN-based flip-chip LED include the following: 1: with the increasing power of the LED, the non-radiative recombination of holes and electrons in the active layer is increased, and the amount of heat released is increased, which requires that the transparent electrode on the surface of the LED chip has very good transparency and conductivity, and the conventional transparent conductive thin film tin-doped indium oxide (ITO) is usually used as the transparent electrode for the current diffusion layer on the p-type GaN of the LED. However, due to the lack of indium, the cost for preparing the ITO transparent electrode is higher and higher, and the ITO is chemically unstable in the presence of acid or alkali, the preparation temperature is high, and the like, the use of these oxides faces serious problems; researchers find that the combination of graphene/metal is improved in improving the transmittance, but still needs to be improved. 2: reliability of the light-reflecting layer and the light-reflecting electrode. The early GaN-based flip LED adopts an Ag film as a p-GaN reflective electrode, a TiW protective layer is sputtered to limit the migration of Ag, but the Ag reflective electrode flip LED still has overlarge leakage current and can lead the lamp to be dead in the aging process, the migration of Ag cannot be completely avoided, and researchers adopt ITO transparent electrode media and DBRs to replace the Ag film as a flip LED reflective structure later, so that the reflectivity and the light-emitting efficiency of the device are improved to some extent. At present, the high-power GaN-based flip LED is gradually used in a high-temperature environment, so that the stability of a chip is highly required, and how to construct a transparent electrode and a reflecting layer have extremely important significance on the stability of the chip. 3: solder quality and welding quality can affect the thermal resistance and the service life of the flip LED chip, for example, AuSn eutectic welding and solder paste reflow welding have the problems of controlling the welding voidage, and the welding voidage can cause the problems of increasing the thermal resistance of the chip, reducing the service life and the like.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention mainly aims to provide a blue light semiconductor device which can improve the light-emitting efficiency of the device, reduce the junction temperature and the void ratio, has good thermal stability and high long-term reliability and a preparation method thereof. Based on the purpose, the invention at least provides the following technical scheme:
the preparation method of the blue light semiconductor device comprises the following steps:
sequentially epitaxially growing an epitaxial lamination layer comprising an n-type layer, an active layer and a p-type layer on the patterned sapphire substrate;
forming an ohmic contact metal film layer on the p-type layer, and etching the ohmic contact metal film layer to form an ohmic contact metal film region of a specific region;
transferring a single-layer or multi-layer graphene film to the surface of an ohmic contact metal film area to form a periodic metal/graphene composite transparent electrode;
sequentially and repeatedly executing the ohmic contact metal film region forming step and the graphene film transferring step for 1-5 times to form a metal/graphene composite transparent electrode with 2-6 periods on the surface of the p-type layer;
etching the epitaxial lamination layer until the n-type layer is exposed by taking the metal/graphene composite transparent electrode as a self-aligned mask;
etching the scribing channel;
preparing an n electrode on the surface of the n-type layer, and preparing a p electrode on the surface of the metal/graphene composite transparent electrode;
depositing passivation layers on the surfaces and the side faces of the epitaxial lamination layer, the metal/graphene composite transparent electrode, the p electrode, the n electrode, the DBR layer on the surface of the passivation layer, and depositing a protection layer on the surface of the DBR layer;
etching the protective layer, the DBR layer and the passivation layer on the surfaces of the n electrode and the p electrode to form inverted trapezoid openings to the n electrode and the p electrode;
and depositing solder to the inverted trapezoidal openings to connect the n electrode and the p electrode to the substrate.
Further, the method comprises the steps of defining a pad area before depositing the solder, carrying out electron beam evaporation on the Ti/Al/Ti/Pt/Au laminated layer in the pad area, and then annealing in an inert gas atmosphere to form a reflection type p pad metal layer and a reflection type n pad metal layer;
then Sn with the thickness of 20-30 mu m is selected0.965Ag0.03C0.005Solder paste connects the reflective p-pad metal layer and the reflective n-pad metal layer to the substrate, and reflows the solder paste in four temperature zonesAnd curing the interconnection of the pad metal layer and the substrate, wherein the maximum temperature of reflow soldering is 250 ℃.
Further, in the step of forming the ohmic contact metal film region, depositing a 1-5nm metal Au, Ag, Pt or Ni film by an electron beam evaporation method, annealing in a nitrogen atmosphere to form ohmic contact with the p-type layer, and etching the metal film to form the ohmic contact metal film region of the specific region;
the step of transferring the graphene film to the surface of the ohmic contact metal film region comprises: depositing a graphene layer on a copper foil by a CVD method, spin-coating PMMA with the thickness of about 1.5 mu m on the graphene layer, and then adopting FeCl3And corroding the copper foil, after the copper foil is completely corroded, cleaning the remaining PMMA/graphene film by using deionized water, transferring the PMMA/graphene film to the surface of the region of the ohmic contact metal film, and removing PMMA by using a hot acetone solution so as to transfer the graphene film to the surface of the region of the ohmic contact metal film.
Further, PECVD is adopted to deposit SiO with the thickness of 200nm2As a passivation layer, 7.5 pairs of first TiO were sequentially deposited by electron beam evaporation2/SiO2Lamination and 8.5 pairs of second TiO2/SiO2Laminated with a first TiO layer2/SiO2TiO in the stack2Has a thickness of 45.4nm and SiO2Is 75.6nm thick, second TiO2/SiO2TiO in the stack2Has a thickness of 56.8nm and SiO2Has a thickness of 94.5 nm.
The present invention also provides a blue light semiconductor device, comprising,
patterning the sapphire substrate;
the epitaxial lamination is arranged on the surface of the substrate and comprises an n-type layer close to the substrate, an active layer and a p-type layer far away from the substrate, the epitaxial lamination is provided with an etching step, and the etching step is etched to the n-type layer along the p-type layer;
the metal/graphene composite transparent electrode layer is arranged on the surface of the p-type layer in a periodic laminated mode and comprises a metal layer in ohmic contact with the p-type layer and an electrode period unit formed by single-layer or multi-layer graphene laminated on the ohmic contact metal layer;
the n electrode is arranged on the surface of the n-type layer, and the p electrode is arranged on the surface of the p-type layer;
the passivation layer wraps the epitaxial lamination layer, the composite transparent electrode layer, the n electrode and the p electrode, and the DBR layer is arranged on the surface of the passivation layer;
and the solder balls are respectively connected with the n electrode and the p electrode to the substrate.
Further, the number of the electrode period units is 2-6; the ohmic contact metal layer is made of Au, Ag, Pt or Ni, and the thickness of the ohmic contact metal layer is 1-5 nm; preferably, the material of the ohmic contact metal layer is Ni, and the thickness of the material is 1 nm; the graphene is a single layer.
Further, the surface of the DBR layer is provided with SiNxThe thickness of the protective layer is 100nm, the passivation layer is silicon dioxide, and the thickness of the passivation layer is 200 nm; the DBR layer consists of 7.5 pairs of first TiO2/SiO2Stack and 8.5 pairs of second TiO2/SiO2Laminated with a first TiO layer2/SiO2TiO in the stack2Has a thickness of 45.4nm and SiO2Is 75.6nm thick, second TiO2/SiO2TiO in the stack2Has a thickness of 56.8nm and SiO2Has a thickness of 94.5 nm.
Furthermore, the passivation layer, the DBR layer and the protective layer which are positioned on the surfaces of the p electrode and the n electrode are provided with openings, the included angle between the side wall of each opening and the surface of the electrode is less than 45 degrees, and the bonding pad is arranged in each opening and is connected with the p electrode and the n electrode to the substrate.
Furthermore, a reflection-type n bonding pad is arranged between the n electrode and the welding ball, a reflection-type p bonding pad is arranged between the p electrode and the welding ball, the reflection-type n bonding pad and the reflection-type p bonding pad extend to the surface of the protective layer of the welding ball area along the surfaces of the n electrode and the n electrode, and the reflection-type n bonding pad and the reflection-type p bonding pad are Ti/Al/Ti/Pt/Au composite metal layers.
Further, the epitaxial stack is embodied asA GaN buffer layer, an undoped GaN layer, an n-GaN layer, and 8 periods of In sequentially stacked0.21Ga0.79An N/GaN quantum well layer, a p-AlGaN barrier layer and a p-GaN layer, In0.21Ga0.79The thickness of the N well layer is 2.6nm, and the thickness of the GaN barrier layer is 10 nm.
Compared with the prior art, the invention has at least the following beneficial effects:
the flip blue light device disclosed by the invention adopts the metal/graphene composite transparent electrodes which are periodically stacked and the DBR medium layer which is specially designed to realize high light transmittance and reflectivity, and the optical power of the device is about 10% higher than that of the traditional high-power flip GaN-based blue light LED with the same size. In addition, the metal/graphene composite transparent electrode and the p-type layer form good ohmic contact, so that the internal resistance and the surface junction temperature of a chip are reduced. In the preferred scheme of the invention, the reflection p and n bonding pad metal layers are used for further reflecting a small amount of light rays penetrating through the DBR, so that the light extraction efficiency of the device is improved, the stability is improved, the void ratio, the thermal resistance and the junction temperature of the device are all reduced, and the chip has better mechanical stability, excellent thermal performance and long-term reliability due to the use of the reflection p and n bonding pad metal layers.
Drawings
Fig. 1 is a schematic structural diagram of a flip blue LED chip according to embodiment 1 of the present invention.
Fig. 2 is a schematic structural diagram of a flip blue LED chip according to embodiment 2 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings, and the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by persons of ordinary skill in the art without any creative effort belong to the protection scope of the present invention.
The present invention will be described in further detail below. FIG. 1 shows a structure of a blue LED flip chip according to embodiment 1 of the present inventionAs shown in fig. 1, the blue light semiconductor device of the present invention includes a patterned sapphire substrate 1, and an epitaxial stack disposed on a surface of the sapphire substrate 1, where the epitaxial stack includes an n-type layer close to the substrate, an active layer, and a p-type layer far from the substrate, and the epitaxial stack has an etching step, and the etching step is etched along the p-type layer to the n-type layer. In this embodiment, the epitaxial stack consists of a GaN buffer layer, an undoped GaN layer, a Si-doped n-GaN layer, 8 periods of In0.21Ga0.79The N/GaN quantum well layer 3, the p-AlGaN barrier layer 4 and the p-GaN layer 5. In fig. 1, the GaN buffer layer, the undoped GaN layer, and the Si-doped n-GaN layer are not illustrated separately, and layer 2 in the figure is a stack of these three layers.
The thickness of the undoped GaN layer was 1.5 μm, the thickness of the n-GaN layer was 2 μm, and In was In the quantum well layer0.21Ga0.79The thickness of the N well layer is 2.6nm, and the thickness of the GaN barrier layer is 10 nm. The thickness of the p-AlGaN barrier layer is 40nm, and the thickness of the p-GaN layer 5 is 200 nm.
In this embodiment, the etching step is etched to the n-GaN layer along the p-GaN layer 5, exposing the n-GaN.
The metal/graphene composite transparent electrode layers which are periodically stacked are arranged on the surface of the p-type layer and are formed by alternately stacking ohmic contact metal layers 6 and graphene layers 7. The ohmic contact metal layer 6 and the graphene layer 7 constitute electrode period units, the number of which is 2-6, and preferably 3. The material of the ohmic contact metal layer 6 is Au, Ag, Pt or Ni with a thickness of 1-5nm, preferably, the material of the ohmic contact metal layer is Ni with a thickness of 1 nm. The graphene layer 7 is single-layer or multi-layer graphene, and preferably, the graphene layer 7 is single-layer graphene. In this embodiment, the composite transparent electrode layer is disposed on the surface of the p-GaN layer 5, and is formed by alternately stacking 3 periods of the ohmic contact metal Ni and the single-layer graphene 7.
The p-electrode 8 is arranged on the surface of the p-type layer, and the n-electrode 9 is arranged on the surface of the n-type layer. In this embodiment, the p-electrode 8 is disposed on the surface of the p-GaN layer 5, and the n-electrode 9 is disposed on the surface of the n-GaN layer. The p-electrode 8 and the n-electrode 9 are laminated by Cr/Ti/Al metal, wherein the thickness of a Cr layer is 10nm, the thickness of a Ti layer is 20nm, and the thickness of an Al layer is 1000 nm.
The dielectric layer 10 formed by laminating the passivation layer, the DBR layer and the protective layer wraps the epitaxial lamination layer, the composite transparent electrode layer, the n electrode and the p electrode. The passivation layer covers the side walls and exposed surfaces of the epitaxial lamination layer, the composite transparent electrode layer, the n electrode and the p electrode, the DBR layer is arranged on the surface of the passivation layer, and the protection layer is arranged on the surface of the DBR layer to increase the passivation effect. As shown in FIG. 1, in this embodiment, the passivation layer is made of SiO2The thickness is 200 nm. DBR layer is composed of 7.5 pairs of first TiO2/SiO2Stack and 8.5 pairs of second TiO2/SiO2Laminated and laminated, first TiO2/SiO2TiO in the stack2Has a thickness of 45.4nm and SiO2Is 75.6 nm. Second TiO 22/SiO2TiO in the stack2Has a thickness of 56.8nm and SiO2Has a thickness of 94.5 nm. Protective layer is made of SiNXPassivation of the protective layer, SiNXThe thickness of the protective layer was 100 nm.
An inverted trapezoidal hole is formed in the dielectric layer 10 to expose the surfaces of the p electrode 8 and the n electrode 9, and the included angle between the side wall of the inverted trapezoidal hole and the surfaces of the p electrode 8 and the n electrode 9 is less than 45 degrees so as to ensure the uniformity of subsequent solder filling. In this embodiment, the surfaces of the p-electrode 8 and the n-electrode 9 are in the horizontal direction.
As shown in fig. 1, the solder ball is connected to the electrode surface through the inverted trapezoidal hole, the p-electrode 8 is connected to the substrate 13 through the solder ball 11, and the n-electrode 9 is connected to the substrate 13 through the solder ball 12.
Fig. 2 is a schematic structural diagram of a flip blue LED chip according to embodiment 2 of the present invention, as shown in the figure, in an inverted trapezoidal hole, a reflective n pad 15 is disposed between an n electrode 9 and a solder ball 12, a reflective p pad 14 is disposed between a p electrode 8 and a solder ball 11, a reflective p pad metal layer 14 and a reflective n pad metal layer 15 are disposed on the surface of the inverted trapezoidal hole, and extend to the surface of a protective layer in a solder ball region along the surfaces of the p electrode 8 and the n electrode 9, and the reflective n pad metal layer and the reflective p pad metal layer are Ti/Al/Ti/Pt/Au composite metal layers. Preferably, the thickness of the Ti layer is 0.5nm, the thickness of the Al layer is 600nm, the thickness of the Ti layer is 45nm, the thickness of the Pt layer is 50nm, and the thickness of the Au layer is 100 nm. The reflective p-pad metal layer 14 is connected to the substrate 13 through the solder balls 11, and the reflective n-pad metal layer 15 is connected to the substrate 13 through the solder balls 12. The substrate is preferably a copper-clad AlN ceramic substrate.
Correspondingly, the invention also provides a preparation method of the blue light semiconductor device, and the structure of the blue light semiconductor device can be understood more deeply through the preparation method. The preparation method comprises the following steps.
A four-inch patterned sapphire substrate is selected, and an epitaxial lamination layer comprising an n-type layer, an active layer and a p-type layer is epitaxially grown on the sapphire substrate in sequence by adopting a metal organic compound chemical vapor deposition process. In one embodiment, the epitaxial stack is composed of a GaN buffer layer, an undoped GaN layer, a Si-doped n-GaN layer, 8 periods of In0.21Ga0.79N/GaN quantum well, p-AlGaN barrier layer and p-GaN layer. The thickness of the non-doped GaN layer is 1.5um, the thickness of the n-GaN layer is 2 μm, In is In the quantum well0.21Ga0.79The thickness of the N well layer is 2.6nm, and the thickness of the GaN barrier layer is 10 nm. The thickness of the p-AlGaN barrier layer is 40nm, and the thickness of the p-GaN layer is 200 nm.
And forming an ohmic contact metal film layer on the p-type layer, and etching the ohmic contact metal film layer to form an ohmic contact metal film region of a specific region. In one embodiment, a metal Au, Ag, Pt or Ni film with the thickness of 1nm-5nm is deposited on the surface of the p-GaN layer by adopting an electron beam evaporation method. Metallic Ni is preferred, with a thickness of 1 nm. Annealing for 5min in a nitrogen atmosphere to form ohmic contact with p-GaN, defining a metal film region by adopting positive photoresist, removing the developed primer by using oxygen plasma treatment, then placing the film in a corrosive liquid to remove redundant metal films, and finally washing the film clean by using deionized water to form the ohmic contact metal film region of a specific region.
Transferring a single-layer or multi-layer graphene film to the surface of the ohmic contact metal film area to form a metal/graphene composite transparent electrode of one period. In one embodiment, a CVD method is selected to prepare 1-3 layers of graphene on a copper foil, preferably 1 layer of graphene. After PMMA with the thickness of about 1.5um is spin-coated on the prepared graphene, FeCl is used3Corroding the copper foil substrate, wherein only PMMA/graphite is left after the copper foil is completely corrodedCleaning a PMMA/graphene film with deionized water, transferring the PMMA/graphene film to the surface of p-GaN on an epitaxial lamination layer, removing PMMA with a hot acetone solution, cleaning, and etching redundant graphene through photoetching and oxygen plasma to realize the patterning of the graphene film and form a periodic metal/graphene structure.
And sequentially and repeatedly executing the ohmic contact metal film region forming step and the graphene film transferring step for 1-5 times to form a metal/graphene composite transparent electrode with 2-6 periods on the surface of the p-type layer. Preferably, repeating for 2 times to obtain the metal/graphene composite transparent electrode with the period of 3.
And etching the epitaxial lamination layer until the n-type layer is exposed by taking the metal/graphene composite transparent electrode as a self-aligned mask. In a specific embodiment, the metal/Gr region is defined by positive photoresist photoetching as a self-aligned mask, ICP is used for dry etching, and the reaction gas is Cl2、BCl3Ar, the etching depth is about 1.2um, and the n-GaN layer is exposed; and removing the glue, cleaning with a glue removing solution to remove residual glue, and then flushing for spin-drying.
And etching the scribing channel. Defining an etching protection area by adopting positive photoresist photoetching, wherein the protection area covers the whole chip, and only a chip gap is reserved as a scribing channel; performing dry etching by adopting ICP (inductively coupled plasma), wherein the etching depth is about 5um, the sapphire substrate is exposed, each chip is isolated, and a subsequent evaporation passivation layer can cover the side surface of each chip to prevent electric leakage during flip chip bonding; and removing the photoresist, and cleaning with the photoresist solution.
And preparing an n electrode on the surface of the n-type layer, and preparing a p electrode on the surface of the metal/graphene composite transparent electrode. In one embodiment, negative photoresist is used to define the p-electrode and n-electrode regions; depositing a Cr/Ti/Al laminated layer by an electron beam evaporation method to be used as a p electrode and an n electrode, wherein the thickness of the Cr layer is 10nm, the thickness of the Ti layer is 20nm, and the thickness of the Al layer is 1000 nm; stripping and removing the photoresist, removing the photoresist and the redundant metal electrodes by using a blue film, cleaning by using a photoresist removing liquid to remove residual photoresist, and then flushing for spin-drying.
Depositing a passivation layer on the surfaces and the side surfaces of the epitaxial lamination layer, the metal/graphene composite transparent electrode, the p electrode and the n electrodeAnd depositing a DBR layer on the surface of the passivation layer, and depositing a protective layer on the surface of the DBR layer to form a dielectric layer wrapping the surface of the chip. In one embodiment, PECVD is used to deposit 200nm thick SiO2And as a passivation layer, the passivation layer wraps the surfaces and the side faces of the epitaxial lamination layer, the metal/graphene composite transparent electrode, the p electrode, the n electrode and the like. Depositing 32 layers of TiO on the surface of the passivation layer by adopting electron beam evaporation2/SiO2The DBR layer of the film system is composed of 7.5 pairs of first TiO2/SiO2Stack and 8.5 pairs of second TiO2/SiO2Laminated with a first TiO layer2/SiO2TiO in the stack2Has a thickness of 45.4nm and SiO2Is 75.6nm thick, second TiO2/SiO2TiO in the stack2Has a thickness of 56.8nm and SiO2Has a thickness of 94.5 nm. Evaporating a layer of SiN on the surface of the DBR by adopting PECVD (plasma enhanced chemical vapor deposition)XAnd the protective layer is used for increasing the passivation effect, and the thickness of the protective layer is 100 nm.
And etching the protective layer, the DBR layer and the passivation layer on the surfaces of the n electrode and the p electrode to form inverted trapezoid openings to the n electrode and the p electrode. In one embodiment, the passivation layer opening pattern is defined using positive photoresist lithography. And then, dry etching is carried out by adopting ICP (inductively coupled plasma), and the dielectric layer at the opening part of the photoresist is completely etched until the n electrode and the p electrode are completely exposed. And forming an inverted trapezoidal opening in the dielectric layer after etching, wherein in order to ensure the connection uniformity of the solder ball, the p electrode and the n electrode in the opening, the inclined surface of the opening, namely the side wall is required to be as gentle as possible, and as shown in fig. 1, the included angle between the side wall of the opening and the horizontal direction is less than 45 degrees. And then removing the glue, cleaning with a glue removing solution to remove residual glue, and then flushing for spin-drying.
Solder is deposited to the inverted trapezoidal shaped openings to connect the n-electrode and the p-electrode to the substrate. In one embodiment, the pad region is defined by negative photoresist lithography; evaporating AuSn solder into the open pores by thermal evaporation to form solder balls, wherein the content of Au is 80%, and the content of Sn is 20%; stripping and removing the photoresist, removing the photoresist and the redundant solder by using a blue film, cleaning by using a photoresist removing liquid to remove residual photoresist, and then flushing for spin-drying; then annealing for 1min at 230 ℃ in a nitrogen atmosphere; after the chip is adhered to the substrate by using the soldering flux, the AuSn welding flux is melted by high-temperature heating to realize chip-substrate interconnection.
In another embodiment, a pad area is defined prior to depositing solder to the inverted trapezoidal shaped opening, a Ti/Al/Ti/Pt/Au stack is electron beam evaporated at the pad area, followed by annealing in an inert gas atmosphere to form a reflective p-pad metal layer and a reflective n-pad metal layer. In this embodiment, as shown in fig. 2, a pad area is defined by negative photoresist lithography, and then a Ti/Al/Ti/Pt/Au stack is evaporated by an electron beam, where the Ti layer is 0.5nm thick, the Al layer is 600nm thick, the Ti layer is 45nm thick, the Pt layer is 50nm thick, and the Au layer is 100nm thick; stripping and removing the photoresist, removing the photoresist and the redundant metal layer by using a blue film, cleaning by using a photoresist removing liquid to remove residual photoresist, and then flushing for spin-drying; annealing the chip for 1min at 230 ℃ in a nitrogen atmosphere; using a dispensing die bonder to bond Sn with the thickness of 20um-30um0.965Ag0.03C0.005(SAC305) solder paste (preferably 20um) is dotted on the copper-clad AlN ceramic substrate, the chip reflection type p pad metal layer and the n pad metal layer are bonded on the copper-clad AlN ceramic substrate through the SAC305 solder paste, then the chip is placed on a conveyor belt of a lead-free reflow soldering machine, the SAC305 solder paste is solidified through a four-temperature-zone reflow soldering process to realize interconnection of the pad metal layer and the substrate, and the highest temperature of reflow soldering is 250 ℃.
In the two embodiments, when the central wavelength of the device is 452nm, the light transmittance of the metal/graphene composite transparent electrode is as high as 89.7%, the reflectivity of the DBR is as high as more than 90%, and the optical power is about 10% higher than that of a conventional high-power flip-chip GaN-based blue-light LED with the same size, which indicates that the structure enhances the light extraction efficiency. When 350mA current is injected, the forward voltage of the chip is about 3.23V, which shows that the metal/graphene composite transparent electrode and the p-GaN form good ohmic contact, and the internal resistance and the surface junction temperature of the chip are reduced. Embodiment 2 is a preferred scheme of the present invention, the reflective p-pad metal layer and the reflective n-pad metal layer can further reflect a small amount of light transmitted through the DBR, and the light extraction efficiency of the device is further improved, and tests show that the device structure of embodiment 2 has better stability than that of embodiment 1, specifically, the device void ratio is lower than that of embodiment 1, the thermal resistance and the junction temperature of the device are lower than those of embodiment 1, and the light decay of the device of embodiment 2 is only 1.8% after accelerated aging at 100 ℃ for more than 1000 hours, which shows that the chip with the Ti/Al/Ti/Pt/Au reflective pad has better mechanical stability, excellent thermal performance and long-term reliability.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (7)
1. The preparation method of the blue light semiconductor device is characterized by comprising the following steps:
sequentially epitaxially growing an epitaxial lamination layer comprising an n-type layer, an active layer and a p-type layer on the patterned sapphire substrate;
forming an ohmic contact metal film layer on the p-type layer, and etching the ohmic contact metal film layer to form an ohmic contact metal film region of a specific region;
transferring a single-layer or multi-layer graphene film to the surface of the ohmic contact metal film area to form a metal/graphene composite transparent electrode of one period;
sequentially and repeatedly executing the ohmic contact metal film region forming step and the graphene film transferring step for 1-5 times to form a metal/graphene composite transparent electrode with 2-6 periods on the surface of the p-type layer;
etching the epitaxial lamination layer until the n-type layer is exposed by taking the metal/graphene composite transparent electrode as a self-aligned mask;
etching the scribing channel;
preparing an n electrode on the surface of the n-type layer, and preparing a p electrode on the surface of the metal/graphene composite transparent electrode;
depositing passivation layers on the surfaces and the side surfaces of the epitaxial lamination layer, the metal/graphene composite transparent electrode, the p electrode, the n electrode, the DBR layer on the surface of the passivation layer, and depositing SiN on the surface of the DBR layerxA protective layer;
etching the protective layer, the DBR layer and the passivation layer on the surfaces of the n electrode and the p electrode to form an inverted trapezoidal opening from the side wall of the opening to the n electrode and the p electrode, wherein the included angle between the side wall of the opening and the horizontal direction is less than 45 degrees;
depositing solder to the inverted trapezoidal openings to connect the n-electrode and the p-electrode to the substrate;
further comprising, prior to depositing solder, defining a pad area where the Ti/Al/Ti/Pt/Au stack is electron beam evaporated, followed by annealing in an inert gas atmosphere to form a reflective p-pad metal layer and a reflective n-pad metal layer;
then Sn with the thickness of 20-30 mu m is selected0.965Ag0.03C0.005Connecting the reflection-type p pad metal layer and the reflection-type n pad metal layer to the substrate by using solder paste, and solidifying the interconnection between the pad metal layer and the substrate by using reflow soldering of a four-temperature zone, wherein the highest temperature of the reflow soldering is 250 ℃;
wherein, PECVD is adopted to deposit SiO with the thickness of 200nm2As a passivation layer, the DBR layer was deposited with 7.5 pairs of the first TiO layer in sequence by electron beam evaporation2/SiO2Stack and 8.5 pairs of second TiO2/SiO2Laminated with a first TiO layer2/SiO2TiO in the stack2Has a thickness of 45.4nm and SiO2Is 75.6nm thick, second TiO2/SiO2TiO in the stack2Has a thickness of 56.8nm and SiO2Has a thickness of 94.5 nm.
2. The preparation method according to claim 1, wherein in the step of forming the ohmic contact metal film region, a 1-5nm metal Au, Ag, Pt or Ni film is deposited by an electron beam evaporation method, and is annealed in a nitrogen atmosphere to form ohmic contact with the p-type layer, and the metal film is etched to form the ohmic contact metal film region of a specific region;
the step of transferring the graphene film to the surface of the ohmic contact metal film region comprises the following steps: depositing a graphene layer on a copper foil by a CVD method, spin-coating PMMA with a thickness of about 1.5 μm on the graphene layer, and then using FeCl3Corroding the copper foil, after the copper foil is completely corroded, cleaning the rest PMMA/graphene film by using deionized water, and transferring the PMMA/graphene filmAnd removing PMMA (polymethyl methacrylate) by adopting a hot acetone solution to the surface of the ohmic contact metal film area so as to transfer the graphene film to the surface of the ohmic contact metal film area.
3. A blue light semiconductor device, comprising,
the sapphire substrate is patterned to form a pattern,
the epitaxial lamination is arranged on the surface of the substrate and comprises an n-type layer close to the substrate, an active layer and a p-type layer far away from the substrate, the epitaxial lamination is provided with an etching step, and the etching step is etched to the n-type layer along the p-type layer;
the metal/graphene composite transparent electrode layer is arranged on the surface of the p-type layer in a periodic laminated mode and comprises a metal layer in ohmic contact with the p-type layer and an electrode period unit formed by single-layer or multi-layer graphene laminated on the ohmic contact metal layer;
the n electrode is arranged on the surface of the n-type layer, and the p electrode is arranged on the surface of the p-type layer;
passivation layer, DBR layer and SiNxA protective layer, wherein the epitaxial lamination layer, the composite transparent electrode layer, the n electrode and the p electrode are wrapped by the passivation layer, the DBR layer is arranged on the surface of the passivation layer, and the SiNxThe protective layer is positioned on the surface of the DBR layer, the passivation layer is silicon dioxide, and the thickness of the passivation layer is 200 nm; the DBR layer consists of 7.5 pairs of first TiO2/SiO2Stack and 8.5 pairs of second TiO2/SiO2Laminated with a first TiO layer2/SiO2TiO in the stack2Has a thickness of 45.4nm and SiO2Is 75.6nm thick, second TiO2/SiO2TiO in the stack2Has a thickness of 56.8nm and SiO2Is 94.5nm, and SiNxThe thickness of the protective layer is 100 nm;
passivation layer, DBR layer and SiNxAn inverted trapezoidal opening exposing the n electrode and the p electrode is arranged in the protective layer, the included angle between the side wall of the opening and the surface of the electrode is less than 45 degrees,
the solder balls are arranged in the openings and respectively connect the n electrode and the p electrode to the substrate;
the reflection type n bonding pad is arranged between the n electrode and the solder ball, the reflection type p bonding pad is arranged between the p electrode and the solder ball, the reflection type n bonding pad and the reflection type p bonding pad extend to the surface of the protective layer of the solder ball area along the surfaces of the n electrode and the n electrode, and the reflection type n bonding pad and the reflection type p bonding pad are Ti/Al/Ti/Pt/Au composite metal layers.
4. The blue semiconductor device according to claim 3, wherein the number of the electrode period units is 2 to 6; the ohmic contact metal layer is made of Au, Ag, Pt or Ni, and the thickness of the ohmic contact metal layer is 1-5 nm.
5. The blue light semiconductor device according to claim 4, wherein the graphene is a single layer.
6. The blue light semiconductor device according to claim 3 or 4, wherein the material of the ohmic contact metal layer is Ni, and the thickness thereof is 1 nm.
7. The blue semiconductor device according to any one of claims 3 to 5, wherein the epitaxial stack is specifically a GaN buffer layer, an undoped GaN layer, an n-GaN layer, and 8 periods of In stacked In this order0.21Ga0.79An N/GaN quantum well layer, a p-AlGaN barrier layer and a p-GaN layer, In0.21Ga0.79The thickness of the N well layer is 2.6nm, and the thickness of the GaN barrier layer is 10 nm.
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