CN113066423A

CN113066423A - LED display drive control method and device

Info

Publication number: CN113066423A
Application number: CN201911416556.8A
Authority: CN
Inventors: 蔡胜强; 林智远; 谢相伟; 颜青青
Original assignee: TCL Research America Inc
Current assignee: TCL Corp; TCL Research America Inc
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2021-07-02

Abstract

The application is suitable for the technical field of display screen driving, and provides a control method and a device for LED display driving, wherein the control method comprises the following steps: determining a driving mode of each LED in the LED array based on the brightness data of the current frame to obtain first driving data and second driving data; inputting first driving data to the LED array to drive the LED array for the first time; and inputting second driving data to the LED array to drive the LED array for the second time, wherein the first driving mode and the second driving mode respectively correspond to one of a PAM driving mode and a PWM driving mode. PAM and PWM drive jointly, can realize the reliable demonstration of LED array when LED array high gray scale and low gray scale, can effectively promote the grey scale homogeneity of LED array to can realize accurate grey scale control, promote the display effect of LED array.

Description

LED display drive control method and device

Technical Field

The application belongs to the technical field of display screen driving, and particularly relates to a method and a device for controlling LED display driving.

Background

At present, the LED display screen is widely applied due to the advantages of small space, high splicing property, high brightness, long display life, good visual angle and the like. However, compared to other display technologies, such as liquid crystal, OLED (organic light-Emitting Diode), etc., the LED display still has room for improvement in resolution, gray scale uniformity, etc.

The existing display control method of the LED display screen is generally a PWM (Pulse Width Modulation) drive control method, but when the LED display screen displays a high gray scale, the PWM drive control method may cause a certain fluctuation of the current of the LED display screen, and the displayed gray scale has a deviation, resulting in a poor display effect of the LED display screen.

Disclosure of Invention

In view of this, embodiments of the present application provide a method and an apparatus for controlling LED display driving, so as to solve the problem that the display effect of the display screen is not good under the control of the existing display control method of the display screen.

A first aspect of an embodiment of the present application provides an LED display driving control method, including:

determining a driving mode of each LED in the LED array based on brightness data of a current frame to obtain first driving data and second driving data, wherein the first driving data comprises gray scale data of the LEDs determined as the first driving mode, and the second driving data comprises gray scale data of the LEDs determined as the second driving mode;

inputting first driving data to the LED array to drive the LED array for the first time;

and inputting second driving data to the LED array to drive the LED array for the second time, wherein the first driving mode is one of a PAM driving mode and a PWM driving mode, and the second driving mode is the other one of the PAM driving mode and the PWM driving mode.

Optionally, the determining a driving mode of each LED in the LED array based on the brightness data of the current frame to obtain first driving data and second driving data includes:

determining a driving mode of each LED in the LED array based on the brightness data of the current frame and a preset value;

and obtaining the first driving data and the second driving data based on the driving mode of the LED and the brightness data of the current frame.

Optionally, the brightness data of the current frame includes gray scale data of each LED in the LED array; the step of determining the driving mode of each LED in the LED array based on the brightness data of the current frame and a preset value includes:

when the gray-scale value of the LED is larger than or equal to the preset value, a PAM driving mode is adopted; and/or

And when the gray-scale value of the LED is smaller than the preset value, a PWM driving mode is adopted.

Optionally, obtaining the first driving data and the second driving data based on the determination result and the luminance data of the current frame includes:

grouping the LEDs in the LED array based on the determination result to obtain a first group and a second group;

and obtaining first driving data and second driving data based on the grouping result and the brightness data of the current frame.

Optionally, the obtaining the first driving data and the second driving data based on the grouping result and the luminance data of the current frame includes:

obtaining the first driving data based on the gray scale data of the LED determined as the PAM driving mode;

obtaining the second driving data based on gray scale data of the LEDs determined as the PWM driving mode, wherein the first driving data comprises the gray scale data of the LEDs determined as the PAM driving mode and virtual gray scale data of the LEDs determined as the PWM driving mode, the virtual gray scale data of each LED determined as the PWM driving mode is 0, the second driving data comprises the gray scale data of the LEDs determined as the PWM driving mode and the virtual gray scale data of the LEDs determined as the PAM driving mode, and the virtual gray scale data of each LED determined as the PAM driving mode is 0.

obtaining the first driving data based on gray scale data of the LED determined as the PWM driving mode;

obtaining the second driving data based on the gray scale data of the LED determined as the PAM driving mode, wherein the first driving data comprises the gray scale data of the LED determined as the PWM driving mode and the virtual gray scale data of the LED determined as the PAM driving mode, the virtual gray scale data of each LED determined as the PAM driving mode is 0, the second driving data comprises the gray scale data of the LED determined as the PAM driving mode and the virtual gray scale data of the LED determined as the PWM driving mode, and the virtual gray scale data of each LED determined as the PWM driving mode is 0.

Optionally, each LED in the LED array is respectively connected to a sub-control channel, where the sub-control channel includes a first sub-control channel and a second sub-control channel, and the inputting of the first driving data to the LED array drives the LED array for the first time includes:

inputting a line scanning signal to a corresponding LED of the LED array through the first sub-control channel;

inputting a row data signal to the LED array through the first sub-control channel, inputting gray scale data to each LED, and lighting the LED corresponding to the first driving mode, wherein the LED corresponding to the second driving mode does not emit light.

Optionally, when the first driving is finished, inputting second driving data to the LED array to drive the LED array for the second time, where the driving includes:

inputting a line scanning signal to the LED array through the second sub-control channel;

inputting a row data signal to the LED array through the second sub-control channel, inputting gray scale data to each LED, and lighting the LED corresponding to the second driving mode, wherein the LED corresponding to the first driving mode keeps lighting during the second driving.

A second aspect of an embodiment of the present application provides an LED display drive control apparatus, including an FPGA;

the FPGA is used for determining a driving mode of each LED in the LED array based on brightness data of a current frame to obtain first driving data and second driving data, the first driving data comprise gray scale data of the LEDs determined as the first driving mode, and the second driving data comprise gray scale data of the LEDs determined as the second driving mode;

the LED driving circuit is also used for inputting first driving data to the LED array to drive the LED array for the first time;

the LED driving circuit is also used for inputting second driving data to the LED array to drive the LED array for the second time; the first driving mode is one of a PAM driving mode and a PWM driving mode, and the second driving mode is the other of the PAM driving mode and the PWM driving mode.

Optionally, the LED display driving control apparatus further includes: the control channel is also connected with the LED array;

the driving module is used for receiving the data of the FPGA and transmitting corresponding signals to the control channel;

the control channel is used for transmitting the signal sent by the driving module to the LED array.

Optionally, the first driving data includes first sub-driving data of each LED, the second driving data includes second sub-driving data of each LED, the control channel includes a plurality of sub-control channels, each sub-control channel corresponds to one LED, the sub-control channels include a first sub-control channel, a second sub-control channel, and a lighting control unit, the first sub-control channel is used for transmitting the first sub-driving data, the second sub-control channel is used for transmitting the second sub-driving data, and the first sub-control channel and the second sub-control channel are respectively connected to the lighting control unit.

Optionally, the first sub-control channel includes a first electronic switch device, a first capacitor and a second electronic switch device, the control end of the first electronic switch device is connected to the scan signal output end of the driving module, the input end of the first electronic switch device is connected to the data signal input end of the driving module, the output end of the first electronic switch device is connected to one end of the first capacitor, the control end of the second electronic switch device is connected to the lighting signal output end of the driving module, the input end of the second electronic switch device is connected to one end of the first capacitor, and the output end of the second electronic switch device is connected to the control end of the lighting control unit.

Optionally, the first driving mode is a PAM driving mode, the second driving mode is a PWM driving mode, the second sub-control channel includes a third electronic switching device, a first operational amplifier, a second capacitor and a fourth electronic switching device, an input terminal of the third electronic switching device is connected to the dc voltage output terminal of the driving module, a control terminal of the third electronic switching device is connected to the scan signal output terminal of the driving module, an output terminal of the third electronic switching device is connected to the inverting input terminal of the first operational amplifier, a non-inverting input terminal of the first operational amplifier is configured to receive a triangular wave signal, an output terminal of the first operational amplifier is connected to one end of the second capacitor, a control terminal of the fourth electronic switching device is connected to the lighting signal output terminal of the driving module, and an input terminal of the fourth electronic switching device is connected to one end of the second capacitor, an output end of the fourth electronic switching device is connected with a control end of the lighting control unit.

Optionally, the lighting control unit includes a fifth electronic switching device, and the fifth electronic switching device is disposed on the LED power supply circuit.

Optionally, the FPGA comprises a first data signal output and a second data signal output;

the driving module comprises a first processor, a digital-to-analog converter, a second processor, a scanning unit and a signal generating unit;

the first data signal output end is connected with the data signal input end of the first processor, the data signal output end of the first processor is connected with the digital-to-analog converter, and the voltage output end of the digital-to-analog converter outputs the direct-current voltage;

the second data signal output end is connected with the data signal input end of the second processor, the data signal output end of the second processor is connected with the scanning unit, and the scanning unit is connected with the control end of the first electronic switching device, the input end of the first electronic switching device and the control end of the third electronic switching device;

and the triangular wave signal output end of the signal generating unit is used for outputting the triangular wave signal.

Optionally, the scanning unit includes a row scanning chip and a column scanning chip, the row scanning chip is configured to output a row scanning signal, and the column scanning chip is configured to output a column scanning signal.

Compared with the prior art, the embodiment of the application has the advantages that: and determining a driving mode of each LED in the LED array based on the brightness data of the current frame, and then, performing PAM driving on the LEDs belonging to the PAM driving mode and performing PWM driving on the LEDs belonging to the PWM driving mode. The PAM driving mode is essentially a current amplitude control mode, the LED array is controlled according to the current amplitude, current fluctuation can be avoided when the high gray scale of the LED array is displayed through a mode of directly controlling the current amplitude, and further deviation of the gray scale displayed by the display screen is avoided. Therefore, the method of jointly driving the LED array by PAM and PWM can realize reliable display of the LED array at both high gray scale and low gray scale of the LED array, and can effectively improve the uniformity of the gray scale of the LED array, thereby realizing accurate gray scale control and improving the display effect of the LED array.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.

Fig. 1 is a schematic flowchart of a method for controlling LED display driving according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of an LED display driving control device according to a second embodiment of the present application;

fig. 3 is a schematic structural diagram of a sub-control channel of an LED display driving control apparatus according to a second embodiment of the present application;

fig. 4 is a schematic structural diagram of a first sub-control channel, a second sub-control channel and a lighting control unit in an LED display drive control device provided in the second embodiment of the present application;

fig. 5 is a schematic structural diagram of an FPGA in an LED display drive control device according to a second embodiment of the present application;

fig. 6 is a schematic structural diagram of a driving module in an LED display driving control apparatus according to a second embodiment of the present application;

fig. 7 is a schematic structural diagram of a digital-to-analog converter in an LED display drive control apparatus according to a second embodiment of the present application;

fig. 8 is a schematic structural diagram of a signal generating unit in an LED display drive control device according to a second embodiment of the present application;

fig. 9 is a schematic structural diagram of a scanning unit in an LED display drive control apparatus according to a second embodiment of the present application;

fig. 10 is a driving timing control diagram of the LED display driving control apparatus according to the second embodiment of the present application;

fig. 11 is a schematic waveform diagram of a PWM signal of an LED display driving control apparatus according to a second embodiment of the present application;

fig. 12 is a schematic structural diagram of a power module of an LED display driving control apparatus according to a second embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In order to explain the technical means described in the present application, the following description will be given by way of specific embodiments.

As shown in fig. 1, the present embodiment provides a method for controlling LED display driving, including:

step S101: determining a driving mode of each LED in the LED array based on the brightness data of the current frame to obtain first driving data and second driving data, wherein the first driving data comprises gray scale data of the LEDs determined as the first driving mode, and the second driving data comprises gray scale data of the LEDs determined as the second driving mode.

In this embodiment, the driving mode of each LED in the LED array is determined by the FPGA based on the luminance data of the current frame, the FPGA is connected to the system on chip SOC, the system on chip SOC is used for receiving and processing a video signal, a video signal output end of the system on chip SOC is connected to the FPGA, the system on chip SOC outputs the processed video signal, such as a high resolution signal of 4k or more, to the FPGA, and the FPGA determines the driving mode of each LED in the LED array based on the luminance data of the current frame.

Generally, the luminance data of each frame is represented by gray scale, and in this embodiment, the luminance data of the current frame includes gray scale data of each LED in the LED array. And when the gray scale value of the LED is larger than or equal to a preset value, the gray scale value of the LED is shown to be a high gray scale value, and a PAM (pulse amplitude modulation) driving mode is adopted for the LED with the high gray scale value, and/or when the gray scale value of the LED is smaller than the preset value, the gray scale value of the LED is shown to be a low gray scale value, and a PWM (pulse width modulation) driving mode is adopted for the LED with the low gray scale value. The LED display driving control method provided in this embodiment may include the above two control processes, or may include only one of the two control processes. In order to realize drive control for both the high-gray-scale LED and the low-gray-scale LED, in this embodiment, the LED display drive control method includes the above two control processes.

The preset value is a preset gray scale threshold value, which is specifically set according to actual conditions, and according to a determination method for high gray scales and low gray scales in the prior art, in this embodiment, the preset gray scale threshold value is 512. It should be understood by those skilled in the art that the preset gray level threshold may be set to other specific values besides 512, such as specific values within a value range centered at 512.

Therefore, according to the size relationship with the preset value, the LEDs in the LED array can be divided into two groups, namely a first group and a second group, wherein the first group can be a high gray scale group including each high gray scale LED; the second group is a low gray scale group comprising LEDs with low gray scales.

Dividing the driving mode based on the two groups of divided LEDs and the brightness data of the current frame to obtain a first driving mode and a second driving mode, wherein the first driving mode and the second driving mode have a corresponding relation with the PAM driving mode and the PWM driving mode, such as: if the first drive mode is a PAM drive mode, the second drive mode is a PWM drive mode; if the first driving mode is the PWM driving mode, the second driving mode is the PAM driving mode.

When the first drive mode is the PAM drive mode and the second drive mode is the PWM drive mode, obtaining first drive data based on the gray scale data of the LED determined as the PAM drive mode, and obtaining second drive data based on the gray scale data of the LED determined as the PWM drive mode.

Wherein the first driving data includes gray scale data of the LED determined as the PAM driving mode and virtual gray scale data of the LED determined as the PWM driving mode, the virtual gray scale data being defined for the purpose of: the virtual gray scale data of each LED determined as the PWM driving mode is 0. Specifically, the method comprises the following steps: when the high-gray-scale-value LED is driven by adopting the PAM driving mode, because the low-gray-scale-value LED is driven by adopting the PWM driving mode, the virtual gray-scale data of the low-gray-scale-value LED is set, and the virtual gray-scale data is 0, namely when the high-gray-scale-value LED is driven by adopting the PAM driving mode, the low-gray-scale-value LED is controlled not to be lightened.

The second driving data includes gray scale data of the LED determined as the PWM driving mode and virtual gray scale data of the LED determined as the PAM driving mode, the virtual gray scale data being defined for the purpose of: the virtual gray scale data of each LED determined as the PAM driving mode is 0. Specifically, the method comprises the following steps: when the LED with the low gray-scale value is driven by adopting the PWM driving mode, because the LED with the high gray-scale value is driven by adopting the PAM driving mode, the virtual gray-scale data of the LED with the high gray-scale value is set, and the virtual gray-scale data is 0, namely when the LED with the low gray-scale value is driven by adopting the PWM driving mode, the LED with the high gray-scale value is controlled not to be lightened.

When the first drive mode is the PWM drive mode and the second drive mode is the PAM drive mode: first drive data is obtained based on the gray-scale data of the LED determined as the PWM drive mode, and second drive data is obtained based on the gray-scale data of the LED determined as the PAM drive mode.

Wherein the first driving data includes gray scale data of the LED determined as the PWM driving mode and virtual gray scale data of the LED determined as the PAM driving mode, the virtual gray scale data being defined for the purpose of: the virtual gray scale data of each LED determined as the PAM driving mode is 0. Specifically, the method comprises the following steps: when the LED with the low gray-scale value is driven by adopting the PWM driving mode, because the LED with the high gray-scale value is driven by adopting the PAM driving mode, the virtual gray-scale data of the LED with the high gray-scale value is set, and the virtual gray-scale data is 0, namely when the LED with the low gray-scale value is driven by adopting the PWM driving mode, the LED with the high gray-scale value is controlled not to be lightened.

The second driving data includes gray scale data of the LED determined as the PAM driving mode and virtual gray scale data of the LED determined as the PWM driving mode, the virtual gray scale data being defined for the purpose of: the virtual gray scale data of each LED determined as the PWM driving mode is 0. Specifically, the method comprises the following steps: when the high-gray-scale-value LED is driven by adopting the PAM driving mode, because the low-gray-scale-value LED is driven by adopting the PWM driving mode, the virtual gray-scale data of the low-gray-scale-value LED is set, and the virtual gray-scale data is 0, namely when the high-gray-scale-value LED is driven by adopting the PAM driving mode, the low-gray-scale-value LED is controlled not to be lightened.

Step S102: and inputting first driving data to the LED array to drive the LED array for the first time.

In order to input a row scanning signal and a column scanning signal to the LED array to drive each LED in the LED array to scan, first driving data is input through the first sub-control channel for first driving, and preferably, the first driving data further includes a high level signal for turning on the first sub-control channel, and after turning on, a data signal is input.

And inputting a row scanning signal to the LED array through the first sub-control channel, and inputting a column data signal to the LED array through the first sub-control channel. And then, inputting gray scale data to each LED respectively, wherein the LED corresponding to the first driving mode is lightened, and the LED corresponding to the second driving mode does not emit light.

If the first drive pattern is a PAM drive pattern, then: when the LEDs with high gray scale values are driven in a PAM driving mode, inputting a row scanning signal and a column scanning signal to the LED array, scanning each LED, inputting corresponding gray scale data to each LED after scanning is finished, lighting the LEDs with high gray scale values, and not lighting the LEDs with low gray scale values because the virtual gray scale data of the LEDs with low gray scale values is 0. When the high-gradation LEDs are turned on, only the high-gradation LEDs are turned on, and the low-gradation LEDs are not turned on.

If the first driving mode is the PWM driving mode, then: when the LEDs with low gray scale values are driven in a PWM driving mode, row scanning signals and column scanning signals are input into the LED array, each LED is scanned, after scanning is finished, corresponding gray scale data are input into each LED, the LEDs with the low gray scale values are lightened, and the LEDs with the high gray scale values are not lightened because the virtual gray scale data of the LEDs with the high gray scale values are 0. When the low-gradation LEDs are turned on, only the low-gradation LEDs are turned on, and the high-gradation LEDs are not turned on.

Step S103: and inputting second driving data to the LED array to drive the LED array for the second time, wherein the first driving mode is one of a PAM driving mode and a PWM driving mode, and the second driving mode is the other one of the PAM driving mode and the PWM driving mode.

The first driving process and the second driving process are in sequence, the first driving process is carried out first, and the second driving process is carried out after the first driving process is finished.

After the first driving process is finished, similarly to step S102, in order to input a row scanning signal and a column scanning signal to the LED array to scan each LED in the LED array, the LED array includes a second sub-control channel, and the second sub-control channel is similarly to the first sub-control channel, and the two channels may be two different channels or may be the same channel. And inputting a row scanning signal and a column data signal to the LED array through a second sub-control channel. Then, inputting gray scale data to each LED, wherein the LED corresponding to the second driving mode is lit, and the LED corresponding to the first driving mode keeps lighting, specifically:

if the first driving mode in step S102 is the PAM driving mode, and the second driving mode is the PWM driving mode, then: when the LEDs with low gray-scale values are driven in the PWM driving mode, row scanning signals and column scanning signals are input into the LED array, each LED is scanned, after scanning is finished, corresponding gray-scale data are input into each LED, each LED with the low gray-scale value is lightened, and in the first driving process, the LED corresponding to the PAM driving mode keeps shining, so that after the LEDs with the low gray-scale values are lightened, all the LEDs of the whole LED array are lightened, and the driving control of the LED array is finished.

If the first driving mode in step S102 is the PWM driving mode, and the second driving mode is the PAM driving mode, then: when the LEDs with high gray-scale values are driven in the PAM driving mode, row scanning signals and column scanning signals are input into the LED array, each LED is scanned, after scanning is finished, corresponding gray-scale data are input into each LED, the LEDs with the high gray-scale values are lightened, and in the first driving process, the LEDs corresponding to the PWM driving mode keep shining, so that after the LEDs with the high gray-scale values are lightened, all the LEDs of the whole LED array are lightened, and the driving control of the LED array is finished.

Therefore, a driving pattern of each LED in the LED array is determined based on the luminance data of the current frame, and then, the LEDs belonging to the PAM driving pattern are PAM-driven and the LEDs belonging to the PWM driving pattern are PWM-driven. The PAM driving mode is essentially a current amplitude control mode, the LED array is controlled according to the current amplitude, current fluctuation can be avoided when the high gray scale of the LED array is displayed through a mode of directly controlling the current amplitude, and further deviation of the gray scale displayed by the display screen is avoided. Therefore, the method of jointly driving the LED array by PAM and PWM can realize reliable display of the LED array at both high gray scale and low gray scale of the LED array, and can effectively improve the uniformity of the gray scale of the LED array, thereby realizing accurate gray scale control and improving the display effect of the LED array.

Fig. 2 is a schematic structural diagram of an LED display driving control device according to a second embodiment of the present application. For convenience of explanation, only portions related to the embodiments of the present application are shown.

The LED display driving control device comprises an FPGA201, a driving module 202 and a control channel 203, wherein the FPGA201 is connected with the driving module 202, the driving module 202 is connected with the control channel 203, and the control channel 203 is connected with an LED array 204. The driving module 202 is configured to receive data of the FPGA201, where the data includes first driving data, second driving data, a lighting signal, and the like, the driving module 202 transmits a corresponding signal to the control channel 203, and the control channel 203 is configured to transmit the signal sent by the driving module 202 to the LED array 204.

The first driving data includes first sub-driving data of the respective LEDs, and the second driving data includes second sub-driving data of the respective LEDs.

The control channel comprises a plurality of sub-control channels, the number of the sub-control channels is the same as that of the LEDs in the LED array, namely, the number of the LEDs is the same as that of the sub-control channels. Moreover, each sub-control channel corresponds to an LED. As shown in fig. 3, any one of the sub-control channels includes a first sub-control channel 2031, a second sub-control channel 2032, and a lighting control unit 2033. The first sub-control channel 2031 is configured to transmit first sub-driving data, the second control channel 2032 is configured to transmit second sub-driving data, and the first sub-control channel 2031 and the second sub-control channel 2032 are respectively connected to the lighting control unit 2033.

The driving module 202 outputs the first sub-driving data to the first sub-control channel 2031, and the first sub-control channel 2031 controls the lighting control unit 2033 according to the first sub-driving data; the driving module 202 outputs the second sub-driving data to the second sub-control channel 2032, and the second sub-control channel 2032 controls the lighting control unit 2033 according to the second sub-driving data.

The FPGA201 is configured to be connected to a system on chip, the system on chip is configured to receive and process a video signal, and the system on chip outputs the processed video signal, such as a high-resolution signal of 4k or more, to the FPGA 201. The system on chip and the FPGA201 can be communicatively connected through an vbo interface. The FPGA201 receives the video signal and processes the video signal. The FPGA201 is configured to determine a driving mode of each LED in the LED array based on the brightness data of the current frame, and obtain first driving data and second driving data, where the first driving data includes gray scale data of the LEDs determined as the first driving mode, and the second driving data includes gray scale data of the LEDs determined as the second driving mode.

The first sub-control channel 2031 is used for inputting first driving data to the LED array 204 to drive the LED array 204 for the first time.

The second sub-control channel 2032 is used for inputting second driving data to the LED array 204 to drive the LED array 204 for a second time.

The lighting control unit 2033 is connected to the LED array 204, and is configured to light the LEDs corresponding to the first driving mode and the LEDs corresponding to the second driving mode in the LED array 204. The LED array 204 includes M rows and N columns of LEDs, where M ≧ 1 and N ≧ 1. Typically, M and N are both positive integers greater than 1, i.e., the LED array 204 includes a plurality of rows and columns of LEDs.

The FPGA201 receives the luminance data of the current frame, determines the driving mode of each LED according to the luminance data, which is a first driving mode and a second driving mode, respectively, the FPGA201 outputs first driving data corresponding to the first driving mode to the driving module 202, the driving module 202 outputs to the first sub-control channel 2031, and the first sub-control channel 2031 controls the lighting control unit 2033 according to the first driving data to control the lighting of the corresponding LED; after the first driving process is finished, the FPGA201 outputs the second driving data corresponding to the second driving mode to the driving module 202, the driving module 202 outputs the second driving data to the second sub-control channel 2032, and the second sub-control channel 2032 controls the lighting control unit 2033 according to the second driving data to control the lighting of the corresponding LED.

The first drive mode is one of a PAM drive mode and a PWM drive mode, and the second drive mode is the other of the PAM drive mode and the PWM drive mode.

When the FPGA201 receives the luminance data of the current frame, it starts to drive the LEDs in the first driving mode, and then drives the LEDs in the second driving mode. The second driving process follows the first driving process, that is, the LEDs corresponding to the first driving mode are lit after the first driving scan is completed, the LEDs corresponding to the second driving mode are lit after the second driving scan is completed, and the first driving process and the second driving process are completed in one frame (for example, 8 ms). When receiving the luminance data of the current frame, the FPGA201 controls the first sub-control channel 2031 to input first driving data to the LED array 204 to drive the LED array 204 for the first time, and after the first driving is finished, controls the second sub-control channel 2032 to output second driving data to the LED array 204 to drive the LED array 204 for the second time.

Adopt two sub-control channel, first sub-control channel 2031 is used for realizing the first drive process alone, and second sub-control channel 2032 is used for realizing the second drive process alone, and the first drive process and the second drive process are independently accomplished respectively through different sub-control channel, can promote the drive reliability of the first drive process and the second drive process, avoid appearing adopting same circuit structure to realize the chaotic condition of drive that twice drive process brought.

Fig. 4 shows a circuit configuration of the first sub-control channel 2031, the second sub-control channel 2032, and the lighting control unit 2033. As shown in fig. 4, the first sub-control channel 2031 comprises a first electronic switching device 301, a first capacitor 302, and a second electronic switching device 303. The control end of the first electronic switch device 301 is connected to the scan signal output end of the driving module 202, the input end of the first electronic switch device 301 is connected to the data signal input end of the driving module 202, the output end of the first electronic switch device 301 is connected to one end of the first capacitor 302, one end of the first capacitor 302 is connected to the input end of the second electronic switch device 303, and the control end of the second electronic switch device is connected to the lighting signal output end of the driving module 202 for accessing a lighting signal.

The second sub-control channel 2032 comprises a third electronic switching device 304, a first operational amplifier 305, a second capacitance 306, and a fourth electronic switching device 307. The input end of the third electronic switching device 304 is connected to the dc voltage output end of the driving module 202, and is configured to receive a dc voltage, the control end of the third electronic switching device 304 is connected to the scan signal output end of the driving module 202, the output end of the third electronic switching device 304 is connected to the inverting input end of the first operational amplifier 305, the non-inverting input end of the first operational amplifier 305 is configured to receive a triangular wave signal, the output end of the first operational amplifier 305 is connected to one end of the second capacitor 306, one end of the second capacitor 306 is connected to the input end of the fourth electronic switching device 307, and the control end of the fourth electronic switching device 307 is connected to the lighting signal output end of the driving module 202, and is configured to access a lighting signal.

The lighting control unit 2033 includes a fifth electronic switching device 308, the fifth electronic switching device 308 is disposed on the LED power supply circuit 310, and the LED309 is disposed on the LED power supply circuit 310.

The output terminal of the second electronic switching device 303 and the output terminal of the fourth electronic switching device 307 are connected to the control terminal of the fifth electronic switching device 308.

Fig. 5 shows a specific structural component of the FPGA 201. The FPGA201 includes two vbo interfaces, i.e., vbo interface 402 and vbo interface 403, and vbo interface 402 and vbo interface 403 are two video signal input terminals of the FPGA 201. The FPGA201 includes two LVDS interfaces, which are an LVDS interface 405 and an LVDS interface 406, respectively, and the LVDS interface 405 and the LVDS interface 406 are two data signal output terminals of the FPGA201, respectively. The LVDS interface 405 is used to connect with the LED array 204, and output data signals for the LED array 204; the LVDS interface 406 is used to connect to the LED array 204 and output data signals for the LED array 204. The FPGA201 comprises a plurality of GPIO interfaces 404 which are GPIO interfaces 404, and the specific number is set according to actual conditions. In order to store image data information, the FPGA201 is connected with memories, namely a four-way ddr3 storage unit 408 and a one-way flash storage unit 407.

As shown in fig. 6, the driving module includes a first processor 502, a digital-to-analog converter (i.e., DAC module) 503, a second processor 505, a scanning unit 506, and a signal generating unit 507. The data signal input end of the first processor 502 is connected to the first interface 501, and the first interface 501 is one of the GPIO interfaces 404 and is configured to receive the data signal processed by the FPGA 201. The data signal output terminal of the first processor 502 is connected to the digital-to-analog converter 503, and the voltage output terminal of the digital-to-analog converter 503 is used for outputting a required voltage, i.e. a dc voltage required by the input terminal of the third electronic switching device 304. The data signal input end of the second processor 505 is connected to the second interface 504, and the second interface 504 is another GPIO interface 404 for receiving the data signal processed by the FPGA 201. The data signal output terminal of the second processor 505 is connected to the scan unit 506, and the scan unit 506 is used for outputting a scan signal and is connected to the control terminal of the first electronic switching device 301, the input terminal of the first electronic switching device 301, and the control terminal of the third electronic switching device 304. The first processor 502 and the second processor 505 may both be FPGA processors. Therefore, the FPGA201 outputs two paths of data signals, one path of data signal is sent to the first processor 502, and the first processor 502 processes the data signal, transmits the processed data signal to the digital-to-analog converter 503, and converts the processed data signal into a voltage signal; the other path is sent to a second processor 505, the second processor 505 outputs the data signal after processing to a high or low level TTL signal, and transmits the TTL signal to a scanning unit 506, and the scanning unit 506 outputs row and column scanning signals after processing.

The signal generating unit 507 is mainly configured to generate a triangular wave signal Vt, and output the triangular wave signal Vt to the non-inverting input terminal of the first operational amplifier 305 through the triangular wave signal output terminal.

Fig. 7 is a schematic structural diagram of the digital-to-analog converter 503, which mainly uses a D/a digital-to-analog conversion chip 601, where the model of the D/a digital-to-analog conversion chip 601 is DAC 7512. Wherein vcc is powered by 3.3v, din is a data signal output by the first processor 502, and the/sync signal and the clk clock signal are respectively connected to the first processor 502 for data signal transmission control. When the/sync synchronous signal is at low level, data transmission is effective, vo is the output voltage after data signal processing, wherein vo is vcc dini/4096, vcc voltage is 3.3v, din is the input binary data signal, and vo output voltage is between 0-3.3 v. The FPGA201 inputs a data signal to din of the D/a digital-to-analog conversion chip 601, and the D/a digital-to-analog conversion chip 601 outputs a dc voltage vo according to the input data signal.

Fig. 8 is a specific circuit configuration diagram of the signal generating unit 507, and the signal generating unit is composed of 2-way operational amplifiers. As shown in fig. 8, the signal generating unit 507 includes a second operational amplifier 701, a third operational amplifier 702 and a voltage regulator tube 703, the inverting input terminal of the second operational amplifier 701 is grounded, the non-inverting input terminal of the second operational amplifier 701 is connected to the output terminal of the third operational amplifier 702 through a first resistor 704, the non-inverting input terminal of the second operational amplifier 701 is connected to the voltage regulator tube 703 through a second resistor 705, the output terminal of the second operational amplifier 701 is connected to one end of a fourth resistor 707, the other end of the fourth resistor 707 is connected to one end of a third resistor 706, the other end of the third resistor 706 is connected to the inverting input terminal of the third operational amplifier 702, the connecting end of the fourth resistor 707 and the third resistor 706 is connected to the voltage regulator tube, the inverting input terminal of the third operational amplifier 702 is connected to the output terminal of the third operational amplifier 702 through a third capacitor 709, the non-inverting input terminal of the third operational amplifier 702 is grounded through, the output terminal of the third operational amplifier 702 is the triangular wave signal output terminal of the signal generating unit 507.

Depending on the characteristics of the operational amplifiers, at the time of power-up, the voltages at the non-inverting input and inverting input of the third operational amplifier 702 are 0, and the voltage at the output of the third operational amplifier 702 (noted as Uom) is 0. The voltage at the output end of the second operational amplifier 701 is Uz, where Uz is the voltage at both ends of the voltage regulator tube 703, the third resistor 706 and the third capacitor 709 form an integration circuit, the output end of the second operational amplifier 701 charges the third capacitor 709, and the voltage of the output voltage Uom of the third operational amplifier 702 increases continuously with the charging of the third capacitor 709. Wherein the vcc voltage is 3.3v, the capacitance of the third capacitor 709 is 0.1uf, the resistance of the fifth resistor 708 is 10k Ω, the resistance of the fourth resistor 707 is 2k Ω, the resistance of the third resistor 706 is 2.5k Ω, and the resistances of the first resistor 704 and the second resistor 705 are both 10k Ω. When the vcc output is 0v, the output voltage of the second operational amplifier 701 is 0, the third capacitor 709 discharges, the output voltage Uom decreases, and the triangular wave signal Vt is generated. Setting the first resistor 704 as R1, the second resistor 705 as R2, the third resistor 706 as R3, the fourth resistor 707 as R4, and the third capacitor 709 as C5, the frequency of the triangular wave is R2/R4R1R3C 5. The signal generation unit 507 may have other conventional circuit configurations as long as it can generate a triangular wave signal, in addition to the circuit configuration shown in fig. 8.

Fig. 9 is a specific structural diagram of the scanning unit 506, the scanning unit 506 includes a row scanning chip 801 and a column scanning chip 802, and both the row scanning chip 801 and the column scanning chip 802 are shift registers (specifically, 74HC595 shift registers). The line scanning chip outputs two line scanning signals which are a first line scanning signal and a second line scanning signal respectively, the first line scanning signal is p _ scan, the second line scanning signal is w _ scan, the p _ scan corresponds to a PAM driving stage, the w _ scan corresponds to a PWM driving stage, namely the p _ scan is a scanning signal driven by PAM, and the w _ scan is a scanning signal driven by PWM. The column scan chip 802 outputs a column scan signal, which is a p _ data signal. The control terminal of the first electronic switching device 301 is input p _ scan, the input terminal of the first electronic switching device 301 is input p _ data, the control terminal of the third electronic switching device 304 is input w _ scan, and the input terminal of the third electronic switching device 304 is input Vd.

The ds, sh, st and/oe terminals of the 74HC595 shift register are connected to the second processor 505 in fig. 6, the ds terminal is a data input terminal, sh and st control the signal shift output of the 74HC595 shift register, and the/oe terminal is an enable terminal of the 74HC595 shift register. Since the LED array 204 typically includes a plurality of rows and columns of LEDs, the 74HC595 shift register is provided in plurality. A plurality of 74HC595 shift registers are respectively cascaded through an h _ s end and a v _ s end, and data is transmitted to the next 74HC595 shift register, so that control of multiple rows and multiple columns is realized.

The p _ scan and w _ scan are processed and output by the line scanning chip 801, and cascade next 74HC595 shift registers through an h _ s terminal to output a scanning level signal of each line, wherein h _ q0-h _ q7 are output terminals of the level signal.

The data signal shown in fig. 10 is a data signal output by the FPGA201, and the data signal includes two portions, one portion corresponds to the PAM driving phase, and the other portion corresponds to the PWM driving phase. The pdata part in the data signal is a PAM driving stage control instruction corresponding to a PAM driving stage, the PAM driving stage control instruction is output to the row scanning chip 801 and the column scanning chip 802, the row scanning chip 801 outputs p _ scan after being processed, the column scanning chip 802 outputs p _ data level signals after being processed, and v _ q0-v _ q7 are output ends of the level signals. In addition, when wdata in the data signal shown in fig. 10 arrives, the first processor 502 controls the digital-to-analog converter 503 to output a dc voltage; as another embodiment, the dac 503 may not be controlled and may output the dc voltage at all times.

The switch1 signal and the switch2 signal in fig. 10 are two lighting signals emitted by the FPGA201 and are emitted by the GPIO interface 404 of the FPGA 201. Wherein the switch1 signal is output to the control terminal of the fourth electronic switching device 307 and the switch2 signal is output to the control terminal of the second electronic switching device 303. When the output switch2 signal is at a high level, the second electronic switching device 303 is turned on, the first capacitor 302 discharges, the fifth electronic switching device 308 is turned on, and the LED309 is lit; after the p _ data level signal is transmitted, when the output switch1 signal is at a high level, the fourth electronic switch device 307 is turned on, the second capacitor 306 discharges, the fifth electronic switch device 308 is turned on, and the LED309 is turned on. In order to realize that the GPIO interface 404 outputs the switch1 signal and the switch2 signal, the GPIO interface 404 may be two interfaces, one of which outputs the switch1 signal and the other of which outputs the switch2 signal.

As shown in fig. 10, the high gray scale portion is first controlled by PAM driving, and the LED array is scanned by p _ scan1-p _ scan200, only the first electronic switching device 301 is turned on and operated, and the third electronic switching device 304 is turned off and not operated. The emission time instant of p _ scan1-p _ scan200 is at the time corresponding to the PAM driving phase and in the first half of the current frame picture duration. The pdata signal in fig. 10 is inputted into fig. 4 through the column scan chip 802 in fig. 9, and charges the first capacitor 302 in fig. 4. After the scan is completed, the switch2 signal output by the FPGA is at high level, the second electronic switching device 303 is turned on, the first capacitor 302 is discharged, the fifth electronic switching device 308 is turned on, and the LED309 is turned on. The time when the switch2 signal changes to high level may be the end time of the scanning process of the LED array by the p _ scan1-p _ scan200, that is, the time corresponding to half of the duration of the current frame picture. After the PAM driving stage in fig. 10 is completed, the low gray scale part is controlled by PWM driving, and the LED array is scanned by w _ scan1-w _ scan200, only the third electronic switching device 304 is turned on and operated, and the first electronic switching device 301 is turned off and not operated. The emission time of w _ scan1-w _ scan200 is at the time corresponding to the PWM driving phase, and is in the second half of the current frame picture duration. The wdata data signal in fig. 10 is transmitted from the FPGA201 to the first processor 502 in fig. 6, and is transmitted to the digital-to-analog converter 503 in fig. 6, the D/a digital-to-analog conversion chip 601 in fig. 7 processes the output voltage Vd, and compares with the triangular wave signal Vt to obtain the PWM duty cycle signal shown by the dotted line in fig. 11, and the PWM duty cycle shown by the dotted line in fig. 11 can be controlled by controlling the output voltage Vd, so as to control the charging time of the second capacitor 306 in the low gray scale stage. The second capacitor 306 is controlled to be charged by the action of the PWM driving stage, and after the scanning is finished, the switch1 signal is at a high level, the fourth electronic switching device 307 in fig. 4 is turned on, the second capacitor 306 is discharged, the fifth electronic switching device 308 is turned on, and the LED309 is turned on. The time when the switch1 signal changes to high level is the PWM scan end time, i.e., the end time of the scan process performed by the w _ scan1-w _ scan200LED array, i.e., the time when the duration of the current frame picture is about to end. Moreover, by controlling the charging of the first capacitor 302 and the second capacitor 306, the on-time of the fifth electronic switching device 308 can be controlled, so as to control the lighting time of the LED309 within 1 frame of picture, thereby achieving more accurate gray scale control, achieving the purpose of controlling the gray scale number of the LED309, and effectively improving the uniformity and display effect of the gray scale of the LED 309.

In addition, the control device may further include a power module for supplying power to related components in the control device, and fig. 12 shows a specific circuit structure of the power module, which mainly includes a transformer 901, a rectifier bridge 902, a first DC/DC module 903, a second DC/DC module 904, and an LDO chip 905. The primary winding of the transformer 901 is connected with alternating current, the secondary winding of the transformer 901 is connected with one end of a rectifier bridge 902, the other end of the rectifier bridge 902 is provided with a voltage stabilizing capacitor 907, the other end of the rectifier bridge 902 is connected with the input end of a first DC/DC module 903 through a fuse 906, the first output end of the first DC/DC module 903 is connected with a second DC/DC module 904, and the second output end of the first DC/DC module 903 is connected with an LDO chip 905. The transformer 901 converts 220v alternating current into smaller voltage, the rectifier bridge 902 converts the smaller alternating current into direct current voltage, the voltage stabilizing capacitor 907 is mainly used for stabilizing voltage, and the fuse 906 is used for preventing short circuit of a power supply. The first DC/DC module 903 adopts G5312 and 8-channel LTC3375 power supply chips, a first output end and a second output end of the first DC/DC module 903 output 12V voltage, the first DC/DC module 903 is also provided with a third output end which outputs voltages Vg, Vb, Vr and the like, and the first DC/DC module 903 is used for supplying power for an on-chip system and an LED array. The second DC/DC module 904 employs a TPS51716 power chip for converting 12V to 1.5V, primarily to power the four-way ddr3 memory cells 408. The LDO chip 905 mainly uses the AMS1117 chip, generates 5V and 3.3V voltages, and mainly supplies power to the first processor 502, the second processor 505, and the FPGA 201.

Therefore, the PAM drive and the PWM drive are commonly controlled to control the LED lighting time, and in a 1-frame, when in the PAM drive phase, the LED array is scanned to charge the first capacitor 302. Then, the high-gradation LED is controlled to be turned on. Then, in a PWM driving stage, the LED array is scanned, and a PWM level signal with a certain duty ratio is obtained through comparison, so as to charge the second capacitor 306. Then, the low-gray-scale LED is controlled to be turned on, and the high-gray-scale LED is continuously turned on.

In the above embodiment, PAM driving is performed on the high-gray-scale LED first, and then PWM driving is performed on the low-gray-scale LED, which is a specific implementation, and as another implementation, PAM driving may be performed on the low-gray-scale LED first, and then PAM driving is performed on the high-gray-scale LED.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may be modified or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. An LED display drive control method, comprising:

2. The LED display driving control method according to claim 1, wherein the determining a driving mode of each LED in the LED array based on the luminance data of the current frame to obtain the first driving data and the second driving data comprises:

3. The LED display drive control method according to claim 2, wherein the luminance data of the current frame includes grayscale data of each LED in the LED array; the step of determining the driving mode of each LED in the LED array based on the brightness data of the current frame and a preset value includes:

4. The LED display driving control method according to claim 3, wherein obtaining first driving data and second driving data based on the determination result and the luminance data of the current frame comprises:

5. The method according to claim 4, wherein the first driving mode is a PAM driving mode, the second driving mode is a PWM driving mode, and the obtaining of the first driving data and the second driving data based on the grouping result and the luminance data of the current frame comprises:

6. The LED display driving control method according to claim 4, wherein the first driving mode is a PWM driving mode, the second driving mode is a PAM driving mode, and the obtaining of the first driving data and the second driving data based on the grouping result and the luminance data of the current frame comprises:

7. The LED display driving control method according to claim 3 or 4, wherein each LED in the LED array is connected to a sub-control channel, the sub-control channel comprises a first sub-control channel and a second sub-control channel,

the inputting of the first driving data to the LED array to drive the LED array for the first time includes:

8. The LED display driving control method according to claim 7, wherein inputting second driving data to the LED array to drive the LED array for a second time at the end of the first driving comprises:

9. The LED display drive control device is characterized by comprising an FPGA;

10. The LED display drive control device according to claim 9, further comprising: the control channel is also connected with the LED array;

11. The LED display driving control device according to claim 10, wherein the first driving data includes first sub-driving data of each LED, the second driving data includes second sub-driving data of each LED, the control channel includes a plurality of sub-control channels, each sub-control channel corresponds to one LED, the sub-control channels include a first sub-control channel, a second sub-control channel and a lighting control unit, the first sub-control channel is used for transmitting the first sub-driving data, the second sub-control channel is used for transmitting the second sub-driving data, and the first sub-control channel and the second sub-control channel are respectively connected to the lighting control unit.

12. The LED display drive control apparatus according to claim 11, wherein the first sub-control channel includes a first electronic switching device, a first capacitor and a second electronic switching device, a control terminal of the first electronic switching device is connected to a scan signal output terminal of the driving module, an input terminal of the first electronic switching device is connected to a data signal input terminal of the driving module, an output terminal of the first electronic switching device is connected to one terminal of the first capacitor, a control terminal of the second electronic switching device is connected to a lighting signal output terminal of the driving module, an input terminal of the second electronic switching device is connected to the one terminal of the first capacitor, and an output terminal of the second electronic switching device is connected to a control terminal of the lighting control unit.

13. The LED display drive control apparatus according to claim 12, wherein the first drive mode is a PAM drive mode, the second drive mode is a PWM drive mode, the second sub-control channel includes a third electronic switching device, a first operational amplifier, a second capacitor and a fourth electronic switching device, an input terminal of the third electronic switching device is connected to the dc voltage output terminal of the drive module, a control terminal of the third electronic switching device is connected to the scan signal output terminal of the drive module, an output terminal of the third electronic switching device is connected to the inverting input terminal of the first operational amplifier, a non-inverting input terminal of the first operational amplifier is configured to receive a triangular wave signal, an output terminal of the first operational amplifier is connected to one terminal of the second capacitor, and a control terminal of the fourth electronic switching device is connected to the lighting signal output terminal of the drive module, the input end of the fourth electronic switching device is connected with one end of the second capacitor, and the output end of the fourth electronic switching device is connected with the control end of the lighting control unit.

14. The LED display drive control device according to claim 13, wherein the lighting control unit includes a fifth electronic switching device provided on an LED power supply circuit.

15. The LED display drive control device according to claim 13, wherein the FPGA comprises a first data signal output and a second data signal output;

16. The LED display drive control device according to claim 15, wherein the scanning unit includes a row scanning chip for outputting a row scanning signal and a column scanning chip for outputting a column scanning signal.