CN113064843A - Manufacturing method of solid state disk and solid state disk - Google Patents

Manufacturing method of solid state disk and solid state disk Download PDF

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Publication number
CN113064843A
CN113064843A CN202110313340.XA CN202110313340A CN113064843A CN 113064843 A CN113064843 A CN 113064843A CN 202110313340 A CN202110313340 A CN 202110313340A CN 113064843 A CN113064843 A CN 113064843A
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data
nand flash
flash chip
solid state
state disk
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倪黄忠
刘玉
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Shenzhen Shichuangyi Electronic Co ltd
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Shenzhen Shichuangyi Electronic Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Read Only Memory (AREA)

Abstract

The invention provides a manufacturing method of a solid state disk, which comprises the following steps: providing an SSD controller and a first NAND FLASH chip connected with the SSD controller, wherein the number of data channels of the SSD controller is at least 8; providing a preprocessed cache module and connecting the preprocessed cache module with the SSD controller, wherein the cache module consists of at least two different cache units; determining the data size of data transmitted to the first NAND FLASH chip by the cache module; classifying data with a data size smaller than a preset size into first class data, and classifying data with a data size larger than the preset size into second class data; and respectively transmitting the first type data and the second type data to different positions in the first NAND FLASH chip for storage. The invention also provides the solid state disk. According to the invention, through the optimized design of the data channel and the like, the storage capacity of the solid state disk is increased, and meanwhile, the data transmission speed, the data processing efficiency and the service life of the solid state disk are effectively improved.

Description

Manufacturing method of solid state disk and solid state disk
Technical Field
The invention belongs to the technical field of solid state disks, and particularly relates to a manufacturing method of a solid state disk and the solid state disk.
Background
A Solid State Disk (SSD), also called an electronic hard Disk or a Solid State Drive, is a hard Disk composed of a control unit (SSD controller) and a Solid State storage unit (NANDFLASH granule). Compared with the traditional mechanical hard disk, the solid state hard disk has the characteristics of quick reading and writing, light weight, low energy consumption, small size and the like, is popular with more and more consumers, and is widely applied in life.
Generally, the storage capacity, the data read-write speed, the service life and other performances of the solid state disk are all determined by the number of data channels of the SSD controller, however, the current SSD controller is generally formed by a 2 data channel or a 4 data channel structure, which results in the maximum storage capacity of the solid state disk being 1TB, which is smaller than the storage capacity of the conventional solid state disk, and meanwhile, the data read-write speed is not very high, especially, the concurrency speed of a small file and the service life of the small file are not high enough, which affects the use range of the solid state disk.
Disclosure of Invention
The embodiment of the invention provides a manufacturing method of a solid state disk and the solid state disk, and aims to solve the technical problems of small storage capacity, low data reading and writing speed and short service life of the conventional solid state disk.
The embodiment of the invention is realized in such a way that a manufacturing method of a solid state disk comprises the following steps:
providing an SSD controller and a first NAND FLASH chip connected with the SSD controller, wherein the number of data channels of the SSD controller is at least 8;
providing a preprocessed cache module and connecting the preprocessed cache module with the SSD controller, wherein the cache module consists of at least two different cache units;
determining the data size of the data transmitted to the first NAND FLASH chip by the cache module, classifying the data with the data size smaller than a preset size into a first class of data, and classifying the data with the data size larger than the preset size into a second class of data; and
and respectively transmitting the first type data and the second type data to different positions in the first NAND FLASH chip for storage.
Further, the cache module comprises at least a second NAND FLASH chip and a DRAM chip disposed in parallel with the second NAND FLASH chip, and the providing and connecting a preprocessed cache module to the SSD controller comprises:
converting the TLC particles in the second NAND FLASH chip into SLC particles through a conversion algorithm;
selecting a preset number of data channels from the SSD controller to be connected with the second NAND FLASH chip; and
at least two of the DRAMs arranged in parallel are provided and connected with the SSD controller, wherein the bus of the DRAM chip is at least 16 bits.
Further, the converting the TLC particles in the second NAND FLASH chip into SLC particles by a conversion algorithm includes:
two of the three bits of the TLC particles in the second NAND FLASH chip were discarded so that only one bit of the TLC particles remained and were converted to SLC particles.
Further, the determining the data size of the data transmitted by the cache module to the first NAND FLASH chip, classifying the data with the data size smaller than a preset size as a first class of data, and classifying the data with the data size larger than the preset size as a second class of data includes:
setting a data classification algorithm in the first NAND FLASH chip;
and the SSD controller operates the data classification algorithm to determine the data size of the data transmitted to the first NAND FLASH chip by the cache module, classifies the data with the data size smaller than a preset size into first-class data, and classifies the data with the data size larger than the preset size into second-class data.
Further, the transmitting the first type data and the second type data to different locations in the first NAND FLASH chip for storage includes:
temporarily storing the first type of data in the cache module, and transmitting the first type of data to a first set position in the first NAND FLASH chip for storage after the first type of data is accumulated to a set size; and
after the second type of data is temporarily stored in the cache module, the second type of data is directly transmitted to a second set position in the first NAND FLASH chip for storage.
The invention also provides a solid state disk which is manufactured by the manufacturing method of the solid state disk.
The embodiment of the invention has the advantages that the number of the data channels of the SSD controller is at least 8, compared with the existing 2-data-channel or 4-data-channel solid state disk, the number of the data channels is greatly increased, the SSD controller of multiple data channels can control a large-capacity multi-package storage module, further the storage capacity of the solid state disk is increased, the data transmission speed and other performances are improved, the cache module consisting of at least two different cache units is arranged, the data input into the solid state disk can be cached, the data transmission speed of the solid state disk is effectively improved, meanwhile, the data input into the solid state disk is classified according to the data size, so that the data with different sizes are transmitted according to the preset transmission line and are correspondingly stored to different positions in the first NAND FLASH chip, the data processing efficiency and the service life of the solid state disk are effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of a solid state disk according to an embodiment of the present invention;
fig. 2 to 6 are schematic flow charts illustrating a method for manufacturing a solid state disk according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Generally, the storage capacity, the data read-write speed, the service life and other performances of the solid state disk are all determined by the number of data channels of the SSD controller, however, the current SSD controller is generally formed by a 2-data-channel or 4-data-channel structure, which results in the maximum storage capacity of the solid state disk being 1TB, which is smaller than that of the conventional solid state disk, and at the same time, the data read-write speed is not very high, especially the concurrency speed of a small file and the service life of the small file are not high enough, which affects the application range of the solid state disk.
According to the invention, the SSD controller with the number of at least 8 data channels is provided, the cache module consisting of at least two different cache units is added for caching data, the multi-mechanism mapping algorithm is added for classifying the data, and through the optimized design, the storage capacity of the solid state disk is increased, and simultaneously the data processing efficiency, the data transmission speed and the service life of the solid state disk are effectively improved.
Example one
Referring to fig. 1 and fig. 2, a method for manufacturing a solid state disk 100 according to an embodiment of the invention includes the steps of:
s1: providing an SSD controller 10 and a first NAND FLASH chip 20 connected to the SSD controller 10, wherein the number of data channels of the SSD controller 10 is at least 8;
s2: providing a preprocessed cache module 30 and connecting the preprocessed cache module with the SSD controller 10, wherein the cache module 30 consists of at least two different cache units 31;
s3: determining the data size of the data transmitted by the cache module 30 to the first NAND FLASH chip 20, classifying the data with the data size smaller than the preset size as the first type of data, and classifying the data with the data size larger than the preset size as the second type of data; and
s4: the first type data and the second type data are respectively transmitted to different positions in the first NAND FLASH chip 20 for storage.
In the manufacturing method of the solid state disk 100 according to the embodiment of the present invention, the number of the data channels of the SSD controller 10 provided is at least 8, and compared with the existing solid state disk with 2 data channels or 4 data channels, the number of the data channels of the solid state disk according to the embodiment of the present invention is greatly increased, so that the performance such as the storage capacity and the data transmission speed of the solid state disk 100 can be improved, and the buffer module 30 composed of at least two different buffer units 31 is arranged, so that the data input into the solid state disk 100 can be buffered, the data transmission speed of the solid state disk 100 is effectively improved, meanwhile, the data input into the solid state disk 100 is also classified according to the size of the data, so that the data with different sizes are transmitted according to the preset transmission line, and correspondingly store the data to different positions in the first NAND FLASH chip 20, thereby effectively improving the data processing efficiency and the service life of the solid state disk 100.
Specifically, the solid state disk 100 further includes a PCB substrate for disposing the SSD controller 10, the first NAND FLASH chip 20, and the cache module 30, and in a process of manufacturing the solid state disk 100, a PCB substrate may be provided first, and then the prepared SSD controller 10, the first NAND FLASH chip 20, and the cache module 30 are directly disposed at a set position on the PCB substrate and correspondingly connected, and a specific disposition sequence and position may be specifically selected according to a manufacturing process.
The SSD controller 10 of the number of multiple channels can control a large-capacity multi-die storage unit (such as the first NAND FLASH chip 20 described above), thereby increasing the storage capacity of the SSD. In the embodiment of the present invention, the number of the selected data channels of the SSD controller 10 is 8, which controls the production cost of the solid state disk 100 on the basis of ensuring that the data transmission and processing speed of the solid state disk 100 is effectively increased. Of course, in other embodiments, the SSD controller 10 with 16 data channels or 32 data channels may be selected according to actual requirements, and is not limited herein.
In addition, since the data processing speed of the first NAND FLASH chip 20 is lower than that of the SSD controller 10, in order to avoid the influence on the data transmission and processing efficiency of the solid state disk 100 caused by the fact that the data processing speed of the SSD controller 10 is higher and the first NAND FLASH chip 20 is difficult to completely match with the SSD controller 10, in the embodiment of the present invention, the buffer module 30 is added as a buffer to temporarily store the data written in the first NAND FLASH chip 20 through the processing of step S2.
Therefore, after the data is sorted in the cache module 30, the data is written into the first NAND FLASH chip 20, so that the smoothness of data writing can be improved, the data writing is not blocked when the solid state disk 100 transmits a large file, and the transmission speed of the solid state disk 100 to a continuous large file can be greatly improved.
Furthermore, the Buffer module 30 is a Buffer in the solid state disk 100, and the Buffer is a data "temporary storage area" set up to increase the data writing completion speed. After the data in the cache module 30 is written into the first NAND FLASH chip 20, the original data originally cached in the first NAND FLASH chip 20 is emptied, so as to avoid the cache effect of the cache module 30 being affected by too much data cached in the cache module 30 and avoid the data transmission of the solid state disk 100 being affected.
It should be noted that the preprocessing performed on the cache module 30 specifically includes respectively preprocessing at least two different cache units 31, and the at least two different cache units 31 are connected in parallel to form the cache module 30, so that the cache module 30 has at least two different cache attributes, thereby improving the cache capacity of the cache module 30, and further improving the capacity of the solid state disk 100 for processing more data at the same time. Common cache units 31 such as external DRAM cache, SRAM cache, SLC cache, etc. the NAND FLASH chip may also be used as the cache unit 31 after some processing.
In steps S3 and S4, the SSD controller 10 or the cache module 30 may specifically determine the size of the written data to determine whether the currently transmitted data belongs to a small file (first type data) or a continuous large file (second type data), and after determining the file type, store the large file and the small file in a block (block, i.e., different location) of the first NAND FLASH, so as to avoid the mutual influence of the random storage of the large file and the small file in the first NAND FLASH chip 20, and ensure normal data transmission of the solid state disk 100.
Example two
Further, referring to fig. 1 and fig. 3, the buffer module 30 at least includes a second NAND FLASH chip and a DRAM chip connected in parallel with the second NAND FLASH chip, and the step S1 includes the steps of:
s11: converting the TLC particles in the second NAND FLASH chip into SLC particles through a conversion algorithm;
s12: selecting a preset number of data channels from the SSD controller 10 to connect with the second NAND FLASH chip; and
s13: at least two DRAM chips arranged in parallel are provided and connected to the SSD controller 10, wherein the bus of the DRAM chips is at least 16 bits.
In the embodiment of the present invention, the cache module 30 is composed of a second NAND FLASH chip that is preprocessed and a DRAM chip that is disposed in parallel therewith. In other embodiments, the cache module 30 may also be composed of at least two other cache units 31, which is not limited herein.
Specifically, the preprocessing for the second NAND FLASH chip is:
the solid state disk 100 stores data through flash memory particles in NAND FLASH chips, wherein, the existing relatively common NAND flash memory particles are TLC particles, TLC (Trinary-Level Cell) particles can store 3bits of data (3bits/Cell) per Cell, and the NAND FLASH chip formed by TLC particles has a large storage capacity and a low cost, but has poor data transmission performance and a short service life, and can only withstand 3 thousand program and erase cycles.
However, SLC (Single-Level Cell) particles can store 1bit data (1bit/Cell) per Cell, resulting in a NAND FLASH chip formed therefrom having a low storage capacity and a high cost, but having a good data transmission performance and a long service life, and being able to withstand 10 ten thousand programming and erasing cycles.
In principle, the architecture of SLC grain is two charge values, 0 and 1, i.e. each Cell (grain) can only access 1bit of data, similar to a switch circuit, although it is simple but stable. Whereas TLC particles can store 8 fill point values at once (000, 001, 010, 011, 100, 101, 110, 111), and therefore are higher in density and lower in cost.
In the embodiment of the invention, in consideration of better storage performance and lower cost of the TLC particles and better data transmission performance and service life of the SLC particles, the TLC particles in the second NAND FLASH chip are converted into the SLC particles by the conversion algorithm, and although the storage capacity of the second NAND FLASH chip is low, the single-bit data 0 or 1 is faster to judge whether the data is 0 or 1 for the SSD controller 10, so that the data transmission speed is faster.
Because the SLC particles are single bit data, only 2 level values exist, while for TLC particles 8 level values are needed for distinction and a higher voltage is needed, and the high voltage weakens the thickness of the insulating layer in the second NAND Flash chip architecture, which causes the service life of the second NAND Flash chip to be affected. Therefore, in the embodiment of the present invention, all the TLC particles in the second NAND FLASH chip are converted into SLC particles through the pretreatment, so as to increase the transmission speed of the particle buffer and prolong the service life of the solid state disk 100.
In step S12, when the SSD controller 10 is designed to have hardware, a preset number of data channels are selected to connect to the second NAND FLASH chip in the cache module 30, so that the SSD controller 10 is connected to the second NAND FLASH chip, and the data cache function of the second NAND FLASH chip is implemented.
In one embodiment, the predetermined number may range from 1 to 2, so as to ensure that the SSD controller 10 has enough data channels to connect to the first NAND FLASH chip 20 and transmit data, without affecting the basic data transmission function of the SSD controller 10, and perform efficient data buffering and transmission via the second NAND FLASH chip.
The pretreatment of the DRAM chip comprises the following steps:
in step S13, the external volatile DRAM chip of the SSD controller 10 and the second NAND FLASH chip together form the buffer module 30, and the Bus (Bus) is a common communication trunk for information transmission among various functional components of the computer, and is a transmission line bundle composed of wires, which can be used for data transmission, and the more the Bus, the faster the data transmission speed. Since the bus of the conventional DRAM chip is 4 bits, 8 bits, and 16 bits, the transmission speed of the conventional DRAM chip is limited.
In the embodiment of the present invention, the bus of the DRAM chip is expanded to at least 32 bits, that is, at least 2 16 DRAM chips are connected in parallel to reach 32 bits, and the obtained cache module 30 has a larger capacity, a smaller volume, a shorter transmission time, and a faster transmission speed, so that various performances of the solid state disk 100 are effectively improved, and the cost is controlled to a certain extent.
In other embodiments, the number of DRAM chips and the number of buses may be other, and are not limited to the above 2 and 16 bits, and may be specifically configured in a specific embodiment, and are not specifically limited herein.
EXAMPLE III
Further, referring to fig. 1 and 4, step S11 includes the steps of:
s111: two of the three bits of the TLC particles in the second NAND FLASH chip were discarded so that only one bit of the TLC particles remained and were converted to SLC particles.
Specifically, two bits of the three bits of the TLC particles in the second NAND FLASH chip are discarded, wherein the process of discarding bits is the above conversion algorithm, and the discarding bits may be to delete or shield any two bits of the TLC particles, or to disable any two bits of the TLC particles, so that the original TLC particles are converted from the original 3-bit-storable data to only 1-bit-storable data, so that the TLC particles only retain one bit and are converted into SLC particles.
In one embodiment, if any two bits of the TLC particle are deleted; in another embodiment, if any two bits of the shielded TLC particles are present; in yet another embodiment, if any two bits in the TLC particles fail;
of course, in other embodiments, the TLC particles may be converted into SLC particles by other suitable means, and is not limited to the above step S111, and is not limited thereto.
Example four
Further, referring to fig. 1 and 5, step S3 includes the steps of:
s31: setting a data classification algorithm within the first NAND FLASH chip 20;
s32: the SSD controller 10 runs a data classification algorithm to determine the data size of the data transmitted from the cache module 30 to the first NAND FLASH chip 20, classifies the data with the data size smaller than the preset size as the first type of data, and classifies the data with the data size larger than the preset size as the second type of data.
Specifically, the data classification algorithm of the embodiment of the present invention is burned into the first NAND FLASH chip 20 during the production process, rather than being stored in the SSD controller 10, so as to avoid the influence on the operation processing performance of the SSD controller 10, and the first NAND FLASH chip 20 itself is a memory, so that the data classification algorithm can be preferably stored and supplied to the SSD controller 10 connected thereto for reading and running.
When the solid state disk 100 is in operation, the SSD controller 10 runs the data classification algorithm at the same time, and since the data written into the solid state disk 100 passes through the SSD controller 10, the SSD controller 10 can conveniently and directly monitor the type of the file to be transmitted, determine whether the data is a small file or a continuous large file, that is, whether the data belongs to the first type of data or the second type of data, perform different processing on the different types of data, and ensure that the data is transmitted accurately and orderly.
In one embodiment, the preset size is set to 64kb, that is, data smaller than 64kb is small files (first type data), and data greater than or equal to 64kb is large files (second type data), so as to complete classification of all data. In other embodiments, the predetermined size of the data may be other, and is not limited to 64kb, which may be selected in practical embodiments.
EXAMPLE five
Further, referring to fig. 1 and fig. 6, step S4 includes the steps of:
s41: temporarily storing the first type of data in the cache module 30, and transmitting the first type of data to a first set position in the first NAND FLASH chip 20 for storage when the first type of data is accumulated to a set size; and
s42: after the second type of data is temporarily stored in the buffer module 30, the second type of data is directly transmitted to the second setting position in the first NAND FLASH chip 20 for storage.
Specifically, after the SSD controller 10 classifies the currently transmitted data, the first type of data and the second type of data are transmitted and stored in different manners, so that the first type of data and the second type of data are respectively stored in different blocks of the first NAND FLASH chip 20, and when the classification of the different types of data is completed, the first type of data and the second type of data can be accurately and sequentially controlled and managed at the first setting position and the second setting position.
When the data is small files (first type data), the small files (first type data) are temporarily stored in the cache module 30, and when the number of the small files (first type data) reaches a certain value, that is, when the small files (first type data) are accumulated to a set size, the small files (first type data) are transmitted to a blcok (first set position) of a first NAND FLASH together, so that the situation that the small files (first type data) are randomly stored in the blcok of a first NAND FLASH during single transmission and the capacity space of the solid state disk 100 is insufficient is avoided, the data in the block needs to be moved back and forth to free up a new storage space to store the subsequently transmitted data.
The second type of data is a continuous large file, and therefore, after being temporarily cached in the cache module 30, the second type of data can be directly transmitted to the second set position of the first NAND FLASH chip 20, and then the data does not need to be moved and sorted, so that the transmission speed of the data can be effectively increased.
EXAMPLE six
Referring to fig. 1, an embodiment of the invention further provides a solid state disk 100 manufactured by the method for manufacturing the solid state disk 100.
In the solid state disk 100 of the embodiment of the present invention, the number of the data channels of the SSD controller 10 of the solid state disk 100 is at least 8, which greatly increases the number of the data channels compared to the existing solid state disk with 2 data channels or 4 data channels, and the SSD controller 10 of multiple data channels can control a large-capacity multi-package storage module, thereby increasing the storage capacity of the solid state disk 100 and improving the performance such as data transmission speed, and the like, and the cache module 30 composed of at least two different cache units 31 is provided, so that data input to the solid state disk 100 can be cached, and the data transmission speed of the solid state disk 100 is effectively improved.
Meanwhile, the solid state disk 100 according to the embodiment of the present invention may further classify the input data according to the size of the data, so that the data with different sizes are transmitted according to the preset transmission line and are correspondingly stored to different positions in the first NAND FLASH chip 20, thereby effectively improving the data processing efficiency and the service life of the solid state disk 100.
In the description herein, references to the description of the terms "example one," "example two," etc. mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. A method for manufacturing a solid state disk, the method comprising:
providing an SSD controller and a first NAND FLASH chip connected with the SSD controller, wherein the number of data channels of the SSD controller is at least 8;
providing a cache module which is connected with the SSD controller after being preprocessed, wherein the cache module consists of at least two different cache units;
determining the data size of the data transmitted by the cache module to the first NAND FLASH chip;
classifying data with a data size smaller than a preset size into first class data, and classifying data with a data size larger than the preset size into second class data; and
and respectively transmitting the first type data and the second type data to different positions in the first NAND FLASH chip for storage.
2. The method of claim 1, wherein the cache module comprises at least a second NAND FLASH chip and a DRAM chip connected in parallel with the second NAND FLASH chip, and the providing a cache module connected to the SSD controller after preprocessing comprises:
converting the TLC particles in the second NAND FLASH chip into SLC particles through a conversion algorithm;
selecting a preset number of data channels from the SSD controller to be connected with the second NAND FLASH chip; and
at least two DRAM chips arranged in parallel are provided and connected with the SSD controller, wherein the bus of the DRAM chips is at least 16 bits.
3. The method for manufacturing the solid state disk of claim 2, wherein the step of converting the TLC particles in the second NAND FLASH chip into SLC particles through a conversion algorithm comprises:
two of the three bits of the TLC particles in the second NAND FLASH chip were discarded so that only one bit of the TLC particles remained and were converted to SLC particles.
4. The method for manufacturing the solid state disk of claim 1, wherein the determining the data size of the data transmitted by the cache module to the first NAND FLASH chip, classifying the data with the data size smaller than a preset size as a first class of data, and classifying the data with the data size larger than the preset size as a second class of data comprises:
setting a data classification algorithm in the first NAND FLASH chip;
and the SSD controller operates the data classification algorithm to determine the data size of the data transmitted to the first NAND FLASH chip by the cache module, classifies the data with the data size smaller than a preset size into first-class data, and classifies the data with the data size larger than the preset size into second-class data.
5. The method for manufacturing the solid state disk of claim 1, wherein the transmitting the first type of data and the second type of data to different positions in the first NAND FLASH chip for storage respectively comprises:
temporarily storing the first type of data in the cache module, and transmitting the first type of data to a first set position in the first NAND FLASH chip for storage after the first type of data is accumulated to a set size; and
after the second type of data is temporarily stored in the cache module, the second type of data is directly transmitted to a second set position in the first NAND FLASH chip for storage.
6. Solid state disk, characterized in that it is manufactured by a method of manufacturing a solid state disk according to claims 1-5.
CN202110313340.XA 2021-03-24 2021-03-24 Manufacturing method of solid state disk and solid state disk Pending CN113064843A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113611353A (en) * 2021-08-18 2021-11-05 合肥大唐存储科技有限公司 Method and device for realizing hard disk test, computer storage medium and terminal

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104142894A (en) * 2013-05-06 2014-11-12 华为技术有限公司 Data reading-writing method, storage controller and computer
WO2015051711A1 (en) * 2013-10-13 2015-04-16 张维加 Computer accelerating device using novel usb protocol based on multi-channel slc nand and dram cache
CN107291381A (en) * 2017-05-18 2017-10-24 记忆科技(深圳)有限公司 The implementation method and solid state hard disc of a kind of dynamic accelerating region of solid state hard disc
CN110597457A (en) * 2019-08-06 2019-12-20 深圳市金泰克半导体有限公司 Solid state disk, control method of solid state disk and controller
CN112416880A (en) * 2021-01-22 2021-02-26 南京群顶科技有限公司 Method and device for optimizing storage performance of mass small files based on real-time merging

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104142894A (en) * 2013-05-06 2014-11-12 华为技术有限公司 Data reading-writing method, storage controller and computer
WO2015051711A1 (en) * 2013-10-13 2015-04-16 张维加 Computer accelerating device using novel usb protocol based on multi-channel slc nand and dram cache
CN107291381A (en) * 2017-05-18 2017-10-24 记忆科技(深圳)有限公司 The implementation method and solid state hard disc of a kind of dynamic accelerating region of solid state hard disc
CN110597457A (en) * 2019-08-06 2019-12-20 深圳市金泰克半导体有限公司 Solid state disk, control method of solid state disk and controller
CN112416880A (en) * 2021-01-22 2021-02-26 南京群顶科技有限公司 Method and device for optimizing storage performance of mass small files based on real-time merging

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113611353A (en) * 2021-08-18 2021-11-05 合肥大唐存储科技有限公司 Method and device for realizing hard disk test, computer storage medium and terminal

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