CN113060700A - Nano-channel high-precision processing method based on graphene anisotropic etching principle and application thereof - Google Patents

Nano-channel high-precision processing method based on graphene anisotropic etching principle and application thereof Download PDF

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CN113060700A
CN113060700A CN202110301444.9A CN202110301444A CN113060700A CN 113060700 A CN113060700 A CN 113060700A CN 202110301444 A CN202110301444 A CN 202110301444A CN 113060700 A CN113060700 A CN 113060700A
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王海东
周要洪
赵帅伊
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Tsinghua University
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Abstract

The invention discloses a nano-channel high-precision processing method based on a graphene anisotropic etching principle and application thereof. The method comprises the following steps: (1) layer-by-layer formation of SiO on a silicon substrate2A layer, a single graphene layer, and a strip photoresist layer, wherein the shape and size of the nanochannels to be obtained are controlled based on: SiO 22The thickness of the layer; the shape and size of the single graphene layer; the shape and size of the strip-shaped photoresist layer; single layer stoneThe position, shape and size of the overlapping area of the graphene layer and the strip-shaped photoresist layer; (2) wet etching with hydrofluoric acid solution to remove SiO uncovered by belt-shaped photoresist layer on silicon substrate2SiO of layers and overlapping regions2Layers to form nanochannels in the overlapping regions. The method is simple and convenient to operate, high in machining precision, and the manufactured nano channel is controllable in three-dimensional size, can be integrally formed, does not need a bonding process, is good in sealing performance, and is not prone to leakage when a fluid medium moves along the nano channel.

Description

Nano-channel high-precision processing method based on graphene anisotropic etching principle and application thereof
Technical Field
The invention belongs to the research and development field of nano devices, and particularly relates to a nano channel high-precision processing method based on a graphene anisotropic etching principle and application thereof.
Background
The preparation technology of the three-dimensional micro/nano channel has wide application in a plurality of fields, such as high heat flow density chip heat dissipation, single molecule detection, nano drug research and development, micro-fluidic chip and the like. For the field of heat dissipation with high heat flux density, with the development of the microelectronic industry And the MEMS (Micro-electro-mechanical Systems) technology, the high heat flux density brought by the high integration of the electronic chip limits the further improvement of the chip performance, so how to realize the fast And efficient heat dissipation of the electronic chip becomes a research hotspot, And in many researches, the liquid cooling technology based on the nano-channel is greatly concerned, because the liquid cooling mode can provide larger heat dissipation amount than the traditional air cooling mode (Schmidt, R, et al. first International Conference on Micro channels And Minichannels, 2003), meanwhile, it is noticed that different geometrical shapes of the nano-channel have different heat exchange effects, for example, for the rectangular nano-channel (the cross section of the nano-channel along the length direction is rectangular), a larger depth-width ratio can bring a better heat exchange effect (Khan W a, et al. two-IEEE connected And nuclear reactor Thermal reactor), 2006.), so in order to further explore the heat exchange effects of nanochannels with different geometric sizes and shapes, a high-precision nanochannel preparation method is particularly critical. For the single molecule detection technology based on the nanochannel, the principle is that when a molecule to be detected passes through the nanochannel, information such as the structure of the molecule to be detected can be analyzed by monitoring the change of the nanochannel current in the process (M Tsutsui, et al scientific Reports, 2012), and the most important structure of the measurement device is the nanochannel through which the molecule to be detected passes, and the uniformity (generally, the high uniformity along the length direction of the nanochannel) and the sealing property of the nanochannel directly affect the signal-to-noise ratio of the detection signal, so that the development of an accurate and effective nanochannel preparation process will have a positive effect on the field. In the field of nano drug development, people need to accurately deliver nano drugs to affected parts, which is helpful for rapid dissolution and absorption of drugs, and the use of nano channels can realize accurate delivery of drugs and develop a nano drug monitoring mechanism with higher specificity and sensitivity (spring M, et al. The nano-channel technology has wide and important application prospect in the fields of nano-drug development and precise medical treatment. Furthermore, in recent years, flow and transport properties in nanoscale microchannels have been studied intensively (Sofos F, et al microfluidics and nanofluidics, 2012), and different nanochannel interfaces, size designs and specific electric double-layer, ultra-slip phenomena therein will influence the effect of ion transport and separation (Zhu Y, et al. In summary, the development of a method for preparing a nanochannel, which can precisely control the three-dimensional size of the nanochannel, has a simple and convenient process and strong practicability, is a key core technology for efficient heat dissipation, nano-medicine and nano-fluidic devices.
At present, the commonly used preparation method of the nano-channel comprises the following steps: direct bonding, high energy beam processing, nanoimprint lithography, and the like. The preparation of the nano-channel by the direct bonding method is generally divided into two steps, wherein the nano-channel (without a cover plate) is prepared by a reactive ion etching method in the first step, and the cover plate is bonded in the second step, wherein the cover plate can be made of glass, photoresist and the like. The transverse dimension of a channel processed by reactive ion etching (shanina a. kelly, et al, lab on a chip,2016.) is limited by the wavelength of uv (ultraviolet rays) light, the width of the channel is generally limited to micron level (Phan, et al, asme 2009 Second International Conference on Micro/Nanoscale Heat and Mass transfer. 2009.). The Nanoimprint lithography (NIL: Nanoimprint lithography) is a preparation method combining Nanoimprint lithography and lithography, and the principle thereof is as follows: a technique of realizing micro-nano structure pattern replication by imprinting a mold containing a micro-nano structure on a material to be processed with the aid of a polymer such as a photoresist, etc. (Chou, et al. journal of vacuum science & technology B, 1996). The method generally comprises three steps: processing an imprinting template, transferring a pattern and processing a substrate, namely processing a mold by means of etching and the like, covering the surface of a material to be processed with a polymer such as photoresist and the like as a buffer layer, imprinting the mold on the surface of the material to be processed to generate mechanical deformation, irradiating the mold by ultraviolet light and the like to solidify the mold, and finally removing the buffer layer to obtain a micro-nano structure material with the same structure as the mold, for example, when the mold is a channel obtained by adopting a reactive ion etching method, the channel obtained by the nano-imprinting lithography technology is also the same channel as the channel obtained by the nano-imprinting lithography technology, but the method cannot obtain a closed nano-channel, and needs to combine a bonding technology to add a cover plate to the nano-channel, so that the nano-channel is easily blocked and leaked due to uneven surface roughness of the cover plate (Guo, et al. High-energy beam processing methods (high-energy beams generally refer to electron beams, proton beams, focused ion beams, femtosecond laser beams, and the like) utilize direct irradiation of the high-energy beams on a material to cause physical and chemical changes of the material, so that nanochannels (Choi S, et al.
Therefore, a simple and reliable nano-channel processing method is not available at present, and the development of the related technology of the nano-channel is limited.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the invention aims to provide a nano-channel high-precision processing method based on the graphene anisotropic etching principle and application thereof. The method is simple and convenient to operate and high in machining precision, the three-dimensional size of the prepared nano channel is controllable, the prepared nano channel has good uniformity, the nano channel can be integrally formed, a bonding process is not needed, the sealing performance is good, and liquid leakage is not prone to occurring when a fluid medium moves along the nano channel.
The present application is proposed based on the following findings of the inventors: the single-layer graphene can provide a high-speed transport channel for ions in a hydrofluoric acid solution, so that the chemical reaction rate at the graphene/silicon dioxide interface is obviously higher than that of a silicon dioxide interface without graphene coverage, the characteristic of anisotropic etching is caused, silicon dioxide below a graphene layer is completely etched, the etching surface is regular, and multiple experiments prove that the etching method has a good effect and high robustness.
To this end, according to a first aspect of the invention, the invention proposes a method of preparing a nanochannel. According to an embodiment of the invention, the method comprises:
(1) layer-by-layer formation of SiO on a silicon substrate2A layer, a single graphene layer, and a strip photoresist layer, wherein the shape and size of the nanochannels to be obtained are controlled based on:
the SiO2The thickness of the layer;
the shape and size of the single graphene layer;
the shape and size of the strip-shaped photoresist layer;
the position, shape and size of the overlapping region of the single graphene layer and the strip-shaped photoresist layer;
(2) wet etching to remove SiO uncovered by the belt-shaped photoresist layer on the silicon substrate by adopting hydrofluoric acid solution2SiO of the layer and the overlap region2A layer to form a nanochannel in the overlap region.
According to the method for preparing the nano-channel, disclosed by the embodiment of the invention, the characteristic that silicon dioxide is anisotropically etched when hydrofluoric acid is immersed in graphene is utilized, and the nano-channel can be prepared only by one-step wet etching, so that the method is simple and convenient to operate and high in processing precision. The height of the nano-channel is determined by the thickness of a silicon dioxide layer etched by hydrofluoric acid, and the width and the length of the nano-channel are determined by the overlapping area of the single-layer graphene layer and the strip-shaped photoresist layer; after wet etching, the photoresist layer forms a natural cover plate of the nano-channel, and the cover plate is not required to be additionally arranged for bonding, so that the problems of uneven channel depth, easy liquid leakage, blockage and the like caused by cover plate bonding in the existing nano-channel preparation method can be effectively avoided, and the processing precision of the nano-channel and the yield of the nano-fluidic chip are improved to a great extent; in addition, the method can also design the nanochannel graph with any shape according to the requirement, greatly simplifies the design and processing process of the nanochannel, and has wide application prospect in the fields of high heat flux density chip heat dissipation, single molecule detection, nano-drug research and development, microfluidic chip and the like. In conclusion, the method is simple and convenient to operate and high in machining precision, the prepared nano channel is controllable in three-dimensional size, good in uniformity, capable of being integrally formed, free of a bonding process and good in sealing performance, and liquid leakage is not prone to occurring when the fluid medium moves along the nano channel.
In addition, the method for preparing a nanochannel according to the above-described embodiment of the present invention may also have the following additional technical features:
in some embodiments of the invention, at least one of the following conditions is satisfied: the SiO2Uniform layer thickness of the SiO2The thickness of the layer is 1 to 500 nm; the distances of the overlapping area in the length direction and the width direction of the belt-shaped photoresist layer are respectively and independently 500 nm-10 mu m; the distance of the single graphene layer in the width/length direction of the strip-shaped photoresist layer is not less than the width/length of the strip-shaped photoresist layer, and the distance in the length/width direction of the strip-shaped photoresist layer is less than the length/width of the strip-shaped photoresist layer; the edges of the single graphene layer and/or the strip-shaped photoresist layer respectively and independently comprise at least one selected from a straight line, a curve, a wavy line or a zigzag line; the concentration of the hydrofluoric acid solution is 3-6 wt%; the nano-channel is a nano-channel with a regular or irregular structure.
In some embodiments of the invention, step (1) further comprises at least one of: (1-1) subjecting the silicon substrate to thermal oxidation or chemical vapor deposition to form the SiO2A layer; (1-2) forming a single graphene layer on a copper foil by using a chemical vapor deposition method; forming a polymethyl methacrylate support layer on the single graphene layer; removing the copper foil by adopting an etching method; transferring the single graphene layer to the SiO using the support layer2Removing the support layer; (1-3) controlling the shape and size of the strip-shaped photoresist layer by using an electron beam lithography method, and/or controlling the shape and size of the single graphene layer by using the photoresist layer and an oxygen plasma environment.
In some embodiments of the invention, step (1-3) further comprises: forming a first photoresist layer over the single graphene layer, developing the first photoresist layer into a first strip-shaped photoresist layer using electron beam lithography; removing the graphene layer uncovered by the first strip-shaped photoresist by adopting an oxygen plasma environment so as to obtain a strip-shaped graphene layer; and removing the first strip-shaped photoresist layer, forming a second photoresist layer on the strip-shaped graphene layer, developing the second photoresist layer into a second strip-shaped photoresist layer by using an electron beam lithography method, and defining the position, the shape and the size of the nano channel by using the strip-shaped graphene layer and the second strip-shaped photoresist layer.
In some embodiments of the invention, at least one of the following conditions is satisfied: the included angle between the second strip-shaped photoresist layer and the strip-shaped graphene layer is 1-90 degrees; the included angle between the second strip-shaped photoresist layer and the strip-shaped graphene layer is 45-90 degrees; the second strip-shaped photoresist layers are arranged at intervals in the length direction of the strip-shaped graphene layer and respectively and independently form an overlapping region with the strip-shaped graphene layer; the edges of the graphene strip layers and/or the second photoresist strip layers each independently include at least one selected from a straight line, a curved line, a wavy line, or a zigzag line.
In some embodiments of the invention, at least one of the following conditions is satisfied: the second strip-shaped photoresist layer is perpendicular to the strip-shaped graphene layer; the edges of the strip graphene layer and the second strip photoresist layer in the overlapping region are straight lines; the second strip-shaped photoresist layers are arranged on the strip-shaped graphene layer, and a plurality of overlapped regions which are spaced and have the same shape are formed on the second strip-shaped photoresist layers.
In some embodiments of the invention, comprising: 1) on the silicon liningFormation of SiO on the bottom2A layer; 2) forming a single-layer graphene layer on the copper foil by using a chemical vapor deposition method; forming a polymethyl methacrylate support layer on the single graphene layer; removing the copper foil by adopting an etching method; transferring the single graphene layer to the SiO using the support layer2Removing the support layer; 3) forming a first photoresist layer over the single graphene layer, developing the first photoresist layer into a first strip-shaped photoresist layer using electron beam lithography; removing the graphene layer which is not covered by the first strip-shaped photoresist layer by adopting an oxygen plasma environment so as to obtain a strip-shaped graphene layer; 4) removing the first strip-shaped photoresist layer and forming a second photoresist layer on the strip-shaped graphene layer, developing the second photoresist layer into a second strip-shaped photoresist layer by using an electron beam lithography method, and defining the position, the shape and the size of a nano channel by using the strip-shaped graphene layer and the second strip-shaped photoresist layer; 5) and (3) placing the silicon substrate obtained in the step 4) in a hydrofluoric acid solution for wet etching so as to form the nano-channel.
According to a second aspect of the invention, a nanochannel is provided. According to an embodiment of the present invention, the nanochannel is obtained using the method of preparing a nanochannel described above. Compared with the prior art, the nano channel has the advantages of high processing precision, controllable three-dimensional size, better uniformity, capability of being integrally formed, no need of a bonding process, better sealing property and difficult leakage when a fluid medium moves along the nano channel.
According to a third aspect of the present invention, the present invention provides the use of the nanochannel and/or the preparation method described above in the fields of chip heat dissipation, single molecule detection, nanomedicine development, microfluidic chip. Compared with the prior art, the nano-channel and the method for preparing the nano-channel are used in the fields of high-heat-flux-density chip heat dissipation, single-molecule detection, nano-drug research and development, micro-fluidic chips and the like, so that the problems of uneven channel depth, easy leakage, blockage and the like caused by cover plate bonding in the existing nano-channel preparation method can be effectively avoided, and the processing precision of the nano-channel and the yield of products such as high-efficiency heat dissipation devices, nano-medicines, nano-fluidic chips and the like are improved to a great extent; in addition, the nano-channel graph with any shape can be designed according to requirements, the design and the processing process of the nano-channel are greatly simplified, and the method has great advantages and wide application prospect.
According to a fourth aspect of the invention, a nanodevice is presented. According to an embodiment of the present invention, the nano device has the nano channel and/or the nano channel obtained by the preparation method. Compared with the prior art, the nanometer channel in the nanometer device has higher precision, better uniformity and sealing performance, is not easy to leak when the fluid medium moves along the nanometer channel, and has more excellent product performance.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow diagram of a method of fabricating a nanochannel according to one embodiment of the present invention.
FIGS. 2-9 are flow diagrams of a process for fabricating nanochannels according to one embodiment of the present invention, wherein FIG. 2 is a process for forming SiO on a silicon substrate2A schematic diagram of a three-dimensional layered structure of a layer and a single graphene layer; fig. 3 is a schematic diagram of a three-dimensional layered structure in which a first photoresist layer is formed on a single graphene layer; FIG. 4 is a schematic illustration of a three-dimensional layered structure for developing the first photoresist layer into a first strip-like photoresist layer; fig. 5 is a schematic diagram of a three-dimensional layered structure of a graphene layer obtained after processing a single graphene layer in an oxygen plasma environment; FIG. 6 is a schematic diagram of a three-dimensional layered structure with the first strip of photoresist layer removed; fig. 7 is a schematic diagram of a three-dimensional layered structure in which a second photoresist layer is formed on a graphene layer in strips; FIG. 8 is a schematic view of a three-dimensional layered structure for developing the second photoresist layer into a second strip-shaped photoresist layer; fig. 9 is a schematic diagram of the three-dimensional structure of the nanochannel obtained after hydrofluoric acid etching.
Fig. 10 is a process flow diagram for fabricating a nanochannel according to yet another embodiment of the present invention, wherein (a) in fig. 10 is a front view in the B direction and a side view in the a direction when a single graphene layer is transferred onto a silicon dioxide layer; fig. 10 (B) is a front view in a direction B and a side view in a direction a after a first strip-shaped photoresist layer is formed on a single graphene layer; fig. 10 (c) is a front view in the B direction and a side view in the a direction after removing the first strip photoresist layer and forming a strip graphene layer; fig. 10 (d) is a front view in the B direction and a side view in the a direction after forming a second strip photoresist layer on the strip graphene layer; fig. 10 (e) is a front view in the direction B and a side view in the direction a of the finished nanochannel obtained by wet etching with a hydrofluoric acid solution.
Figure 11 is a top view (image after high magnification by light microscopy) of a finished nanochannel fabricated according to one embodiment of the present invention.
Reference numerals: 10-a silicon substrate; 20-SiO2A layer; 30-a single graphene layer; 31-a graphene layer in strips; 40-strip photoresist layer; 41-a first photoresist layer; 411-first strip photoresist layer; 42-a second photoresist layer; 421-second strip-shaped photoresist layer; 50-nanochannel; w-the width of the nanochannel; the length of the L-nanochannel; height of the H-nanochannel.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, it is to be understood that the terms "length", "width", "thickness", "upper", "lower", "front", "rear", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
According to the first aspect of the invention, the invention provides a method for preparing a nano channel, which is simple and convenient to operate and high in processing precision, the prepared nano channel is controllable in three-dimensional size, has better uniformity, can be integrally formed, does not need a bonding process, is better in sealing property, and is not easy to leak when a fluid medium moves along the nano channel. The method for fabricating the nanochannel according to the above embodiment of the present invention will be described in detail with reference to fig. 1 to 11. According to an embodiment of the invention, the method comprises:
s100: layer-by-layer formation of SiO on a silicon substrate2A layer, a single graphene layer, and a strip photoresist layer, wherein the shape and size of the nanochannels to be obtained are controlled based on: SiO 22The thickness of the layer; the shape and size of the single graphene layer; the shape and size of the strip-shaped photoresist layer; position, shape and size of overlapped region of single graphene layer and strip-shaped photoresist layer
According to an embodiment of the present invention, referring to fig. 8, SiO may be formed layer by layer on a silicon substrate 102The layer 20, the single graphene layer 30 and the strip photoresist layer 40, the desired nanochannel can be obtained by controlling the position, shape and size of the overlapping region of the single graphene layer 30 and the strip photoresist layer 40. As shown in FIG. 9, the height of the nanochannels 50 formed in the present invention may be made of SiO etched by hydrofluoric acid2Layer thickness determination, referring to fig. 8 and 11, the shape, width W, and length L of the nanochannel may be determined by the overlapping region of the single graphene layer 30 and the strip photoresist layer 40; after wet etching, the photoresist layer 40 may form a natural cover plate of the nanochannel,the method has the advantages that a cover plate is not needed to be additionally arranged for bonding, the problems of uneven channel depth, easy liquid leakage, easy blockage and the like caused by the bonding of the cover plate in the existing preparation method of the nano channel can be effectively solved, and the processing precision of the nano channel and the yield of the nano flow control chip are improved to a great extent.
According to a specific embodiment of the present invention, SiO is used in the present invention2The graphene layer formed on the layer 20 should be single-layer graphene, and the inventor finds that anisotropic etching can be better realized only by the single-layer graphene, so that a high-speed transport channel can be provided for ions in a subsequent hydrofluoric acid etching process by forming the single-layer graphene layer, the chemical reaction rate at the graphene/silicon dioxide interface is obviously higher than that at a silicon dioxide interface without graphene coverage, anisotropic etching is realized, the shape and the size of a nano channel can be controlled more favorably, and the condition of excessive etching at the boundary of the nano channel is avoided. Note that, the graphene layers in the present invention are all referred to as single graphene layers. In addition, it should be noted that, since the thickness of the single graphene layer is extremely small, the height H of the finally formed nanochannel is negligibly affected.
According to an embodiment of the present invention, SiO with uniform thickness can be formed on a silicon substrate2Layer of SiO2The thickness of the layer determines the height of the finally formed nanochannel, SiO2The uniformity of the thickness of the layer ensures the uniformity of the height of the finally formed nanochannels. In the present invention, SiO is2The thickness of the layer is not particularly limited and can be selected by the person skilled in the art according to the actual requirements, such as the intended use and height of the nanochannel to be obtained, preferably SiO2The layer may have a thickness of a few nanometers to a few hundred nanometers, e.g. 1 to 500nm, for example SiO2The thickness of the layer may be 1nm, 10nm, 20nm, 30nm, 50nm, 80nm, 100nm, 150nm, 200nm, 300nm, 400nm, 500nm, etc., since if the thickness of the silicon dioxide layer is too large, the corresponding etching time required subsequently is also long, and the situation that the geometry of the nanochannel is affected due to the too long etching time may occur.
According to the inventionIn one embodiment, referring to fig. 8 and 9, the shape and size of the finally formed nanochannel can be controlled by controlling the shape and size of the overlapped region of the single graphene layer and the strip photoresist layer, it should be noted that the shape and size of the overlapped region are not particularly limited, and those skilled in the art can select the overlapped region according to the actual needs of the application, shape, size, etc. of the desired nanochannel, only need to satisfy the requirement of forming the nanochannel after etching with hydrofluoric acid, for example, the distance between the overlapped region of the single graphene layer 30 and the strip photoresist layer 40 in the length direction (e.g. the direction B in fig. 8) and the width direction (e.g. the direction a in fig. 8) of the strip photoresist layer can be several hundreds of nanometers to several micrometers, such as 500nm to 10 μm, and the length and width of the overlapped region can be 500nm, such as 500nm, or 500nm, 600nm, 700nm, 800nm, 900nm, 1 μm, 3 μm, 5 μm, 7 μm, or 9 μm, etc. Furthermore, in order to avoid the SiO that can not form the through nanometer channel or the two sides of the overlapping region because the position, the shape and the size of the overlapping region are not proper2Layers (SiO as shown at 21 and 22 in FIG. 92Layer) is also etched away from forming SiO2In the case of the support layer and the nanochannel, the distance in the width/length direction of the graphene layer 30 may be made not less than the width/length of the photoresist layer 40 and the distance in the length/width direction of the photoresist layer 40 may be made less than the length/width of the photoresist layer 40, for example, the distance in the width direction (direction a in fig. 8) of the photoresist layer 40 may be made not less than the width of the photoresist layer 40 and the distance in the length direction (direction B in fig. 8) of the photoresist layer 40 may be made less than the length of the photoresist layer 40, and more preferably, the graphene layer 30 may be made continuous in the width direction of the photoresist layer 40.
According to still another embodiment of the present invention, the inventors found that the edge structures of the single-layer graphene layer 30 and the strip photoresist layer 40 determine the edge structures of the nanochannel and the edge structures of the overlapping region of the single-layer graphene layer 30 and the strip photoresist layer 40, and those skilled in the art can control the edge structures of the single-layer graphene layer 30 and the strip photoresist layer 40 according to the edge structures of the nanochannel to be obtained, for example, the edges of the single-layer graphene layer 30 and/or the strip photoresist layer 40 can be made to independently include at least one selected from a straight line, a curved line, a wavy line and a zigzag line, respectively, so as to obtain the nanochannel whose edge structure includes at least one selected from a straight line shape, an arc shape.
According to yet another embodiment of the present invention, SiO is formed on a silicon substrate2The layers may include: thermal oxidation or chemical vapor deposition of a silicon substrate to form SiO2Layer in which SiO can be precisely controlled by changing the thermal oxidation time of the silicon substrate or controlling the parameter conditions of chemical vapor deposition2The thickness of the layer.
According to yet another embodiment of the invention, at SiO2Forming a single graphene layer 30 on the layer 20 may include: forming a single-layer graphene layer on the copper foil by using a chemical vapor deposition method; forming a polymethyl methacrylate (PMMA) support layer on the single graphene layer; removing the copper foil by adopting an etching method; transfer of single graphene layers to SiO Using a support layer2The support layer is removed. For example, a chemical vapor deposition method may be adopted to prepare single-layer graphene on a copper foil, then spin-coat PMMA on the surface of the single-layer graphene as a support layer, remove the copper foil substrate with a copper etching solution, and transfer the single-layer graphene onto a silicon substrate with a silicon dioxide layer having a uniform thickness attached on the surface by using the PMMA support layer, so as to obtain a layered structure as shown in fig. 2, which is shown in fig. 10 (a) in a front view in a direction B and in a side view in a direction a.
According to an embodiment of the present invention, the shape and size of the strip-shaped photoresist layer 40 may be controlled by using an electron beam lithography method, and/or the shape and size of the single-layer graphene layer 30 may be controlled by using a photoresist layer and an oxygen plasma environment, and to obtain a nanochannel with higher accuracy, the shape and size of the single-layer graphene layer 30 and the strip-shaped photoresist layer 40 may be strictly controlled by using the electron beam lithography method and the oxygen plasma environment, so that the overlapping region of the two can be consistent with the desired nanochannel. Specifically, referring to fig. 3 to 8 and 10, a first photoresist layer 41 may be formed on the single graphene layer 30 in advance (as shown in fig. 3), and the first photoresist layer 41 may be developed into a first strip photoresist layer 411 (as shown in fig. 4) by using an electron beam lithography method; removing the graphene layer uncovered by the first strip-shaped photoresist layer 411 by using an oxygen plasma environment so as to obtain a strip-shaped graphene layer 31 (as shown in fig. 5); the first strip-shaped photoresist layer 411 (shown in fig. 6) is removed and a second photoresist layer 42 (shown in fig. 7) is formed on the strip-shaped graphene layer 31, the second photoresist layer 42 is developed into a second strip-shaped photoresist layer 421 (shown in fig. 8) by using an electron beam lithography, and the positions, shapes and sizes of the nanochannels are defined by the strip-shaped graphene layer 31 and the second strip-shaped photoresist layer 421. Specifically, the method comprises the following steps:
as shown in fig. 2 to 6, a layer of photoresist (a type may be ZEP520, and the photoresist below may be a type which is a positive photoresist, and the region exposed by the ultraviolet light is dissolved in the developing solution) may be spin-coated on the single graphene layer 30, the photoresist is developed into a shape of a micro-strip by using an electron beam lithography technique, and then exposed to an oxygen plasma environment, and the graphene not covered by the photoresist is etched away, so as to form a graphene strip with a micro-width, where it is to be noted that the width of the etched graphene strip determines the width of the nanochannel (as the width W in (b) and (c) in fig. 10), so that the width of the nanochannel can be precisely controlled by changing the width of the photoresist (the width of the etched graphene strip) exposed by the ultraviolet light and not dissolved by the developing solution in this step; the photoresist is then removed and the wafer is diced (the sample typically contains multiple repeating units before the dicing step) to yield a layered structure as shown in fig. 6, which is shown in fig. 10 (c) in a front view in the direction B and in a side view in the direction a. Further, as shown in fig. 7 to 8, a photoresist may be spin-coated on the surface of the graphene strip having the layered structure as shown in fig. 6, and the photoresist is developed into a shape of a micrometer strip by using an electron beam lithography technique (for example, when the overlapping region of the strip and the graphene strip is in a vertical relationship, the cross-sectional view of the finally obtained nanochannel along the height direction is a rectangle), where it should be noted that the width of the photoresist after development determines the length of the nanochannel (e.g., length L shown in fig. 10 (d), so that the length of the nanochannel can be precisely controlled by changing the width of the photoresist which is not dissolved by the developing solution after exposure to ultraviolet light in this step, and the layered structure as shown in fig. 8 is obtained, and its front view in the B direction and side view in the a direction are shown in fig. 10 (d)).
According to another embodiment of the present invention, the shape of the overlapping region of the photoresist layer and the graphene layer can be assisted to be controlled by controlling the included angle between the second strip-shaped photoresist layer 421 and the strip-shaped graphene layer 31, and it should be noted that the included angle between the second strip-shaped photoresist layer 421 and the strip-shaped graphene layer 31 is not particularly limited in the present invention, and can be selected by a person skilled in the art according to actual needs, for example, the included angle may be 1 to 90 degrees, specifically, 20 degrees, 30 degrees, 50 degrees, 60 degrees, 80 degrees, or 90 degrees, and for example, the included angle may be 45 to 90 degrees.
According to still another embodiment of the present invention, referring to fig. 8 and 11, one or more second strip photoresist layers 421 may be included, wherein the second strip photoresist layers 421 may be arranged at intervals in a length direction of the strip graphene layer and respectively and independently form an overlapping region with the strip graphene layer, so that a plurality of spaced nanochannels may be simultaneously formed in a subsequent hydrofluoric acid etching process, and as shown in fig. 11, two nanochannels 50 may be simultaneously formed.
According to still another embodiment of the present invention, the edge structures of the strip-shaped graphene layer 31 and the second strip-shaped photoresist layer 421 determine the edge structures of the overlapping region and the edge structures of the nanochannels, and one skilled in the art can control the edge structures of the strip-shaped graphene layer 31 and the second strip-shaped photoresist layer 421 according to the edge structures of the nanochannels to be obtained, for example, the edges of the strip-shaped graphene layer and/or the second strip-shaped photoresist layer can be made to independently include at least one selected from a straight line, a curved line, a wavy line or a zigzag line, so as to obtain the nanochannels whose edge structures include at least one selected from a straight line shape, an arc shape, a wave shape, a zigzag shape.
According to another embodiment of the present invention, the nanochannels have different applications and different requirements for their shapes, for example, when the nanochannels are used for high heat flux density heat dissipation of an electronic chip, the nanochannels with rectangular geometric shapes can be selected, and at this time, the second strip-shaped photoresist layer can be perpendicular to the strip-shaped graphene layer, and the edges of the overlapping regions of the strip-shaped graphene layer and the second strip-shaped photoresist layer are both straight lines, so as to obtain rectangular overlapping regions and nanochannels; in addition, depending on actual requirements such as use application, the second strip resist layer may be perpendicular to the strip graphene layer and the edge of the overlap region may be a straight line, and the overlap region may have a trapezoidal shape or the like. Further, the plurality of second strip-shaped photoresist layers 421 are included, and the plurality of second strip-shaped photoresist layers 421 and the strip-shaped graphene layer 31 form a plurality of overlapping regions which are respectively spaced and have the same shape, so that a plurality of nano-channels which are distributed at intervals and have the same three-dimensional size can be simultaneously formed through subsequent etching.
S200: wet etching with hydrofluoric acid solution to remove SiO uncovered by belt-shaped photoresist layer on silicon substrate2SiO of layers and overlapping regions2Layer forming nanochannels in the overlapping region
According to the embodiment of the invention, referring to fig. 8 and 9, when wet etching is carried out by using hydrofluoric acid solution, SiO in the area which is not covered by the strip-shaped photoresist layer on the silicon substrate2Layer and SiO of the region under the photoresist layer overlapping with the graphene layer2The layers are removed and only the regions 21 and 22 under the photoresist layer where no graphene layer is formed remain with SiO2Layer, SiO remaining on both sides of the overlap region2The layer serves as a support region for the nanochannel and the photoresist layer cover plate. The nano-channel prepared in the invention is integrally formed, namely the photoresist above the graphene forms a natural closed cover plate of the nano-channel, and the interface of the photoresist/graphene is firmly bonded, so that bonding between the cover plate and a channel substrate is not needed, namely the photoresist layer and a channel formed by etching below form a complete closed nano-channel, the sealing property is better, and the problems of uneven channel depth, easy liquid leakage, blockage and the like caused by cover plate bonding in the existing nano-channel preparation method can be effectively avoided.
According to an embodiment of the present invention, the concentration and the etching time of the hydrofluoric acid solution in the present invention are not particularly limited, and can be selected by those skilled in the art according to actual needs, for example, the concentration and the etching time of the hydrofluoric acid solution can be determined according to the size of the nano channel to be obtained, and for example, the concentration of the hydrofluoric acid solution can be 3 to 6 wt%, specifically 3 wt%, 3.5 wt%, 4 wt%, 4.5 wt%, 5 wt%, 5.5 wt%, or 6 wt%, and the etching time can be 1 to 60 minutes, specifically 5 minutes, 10 minutes, 15 minutes, or 30 minutes.
According to another embodiment of the present invention, the nanochannels finally formed in the present invention may be regular or irregular nanochannels, for example, the top view of the nanochannels may be rectangular, trapezoidal, S-shaped, drum-shaped, etc., and those skilled in the art can select the nanochannels according to actual needs.
According to another embodiment of the present invention, a hydrofluoric acid wet etching method can be used to etch away the silicon dioxide layer exposed on the surface (not covered by the photoresist strip) in the layered structure shown in fig. 8 and the silicon dioxide layer under the graphene strip, and it should be noted that the successful implementation of this step is based on the characteristic that graphene anisotropically etches silicon dioxide in hydrofluoric acid, and the anisotropic principle is that the graphene strip provides a high-speed transport channel for ions in hydrofluoric acid solution, resulting in a significantly higher chemical reaction rate at the graphene/silicon dioxide interface than at the silicon dioxide interface without graphene covering, so that the silicon dioxide layer under graphene is completely etched away, the silicon dioxide layer under photoresist not covered by graphene is hardly etched, and in this process, the photoresist layer over graphene is kept intact, at this point, it can be noted that the photoresist layer actually forms a natural closed cover plate, and forms a complete closed nano-channel with the channel formed by etching below. It is also noted here that the thickness of the silicon dioxide layer being etched determines the height of the nanochannels, and thus the height of the nanochannels can be precisely controlled by varying the thickness of the silicon dioxide layer. Finally, the nanochannel structure is exposed to an oxygen plasma environment to etch away the excess graphene strips at both ends of the nanochannel, resulting in the nanochannel structure shown in fig. 9, which is shown in fig. 10 (e) in a front view in the direction B and in a side view in the direction a.
According to yet another embodiment of the present invention, a method of fabricating a nanochannel may comprise: 1) formation of SiO on silicon substrate2A layer; 2) forming a single-layer graphene layer on the copper foil by using a chemical vapor deposition method; forming a polymethyl methacrylate support layer on the single graphene layer; removing the copper foil by adopting an etching method; transfer of single graphene layers to SiO Using a support layer2Removing the support layer; 3) forming a first photoresist layer over the single graphene layer, developing the first photoresist layer into a first strip-shaped photoresist layer using electron beam lithography; removing the graphene layer uncovered by the first strip-shaped photoresist by adopting an oxygen plasma environment so as to obtain a strip-shaped graphene layer; 4) removing the first strip-shaped photoresist layer and forming a second photoresist layer on the strip-shaped graphene layer, developing the second photoresist layer into a second strip-shaped photoresist layer by using an electron beam lithography method, and defining the position, the shape and the size of the nano channel by using the strip-shaped graphene layer and the second strip-shaped photoresist layer; 5) and (3) placing the silicon substrate obtained in the step 4) in a hydrofluoric acid solution for wet etching so as to form the nano-channel.
In summary, the method for preparing the nanochannel according to the above embodiment of the present invention has at least the following beneficial effects: 1) the preparation of the nanochannel can be completed only by one-step wet etching by utilizing the characteristic that silicon dioxide is anisotropically etched when hydrofluoric acid is immersed in graphene, so that the operation is simple and convenient, and the processing precision is high; 2) the three-dimensional size of the nano-channel can be accurately regulated, wherein the height of the nano-channel is determined by the thickness of a silicon dioxide layer etched by hydrofluoric acid, and the width and the length of the nano-channel are determined by the overlapping area of a single-layer graphene layer and a strip-shaped photoresist layer; 3) after wet etching, the photoresist layer forms a natural cover plate of the nano-channel, the photoresist/graphene interface is firmly bonded, no additional cover plate is needed for bonding, the sealing performance is better, the problems of uneven channel depth, easy liquid leakage, blockage and the like caused by cover plate bonding in the existing nano-channel preparation method can be effectively avoided, and the processing precision of the nano-channel and the yield of the nano-fluidic chip are improved to a great extent; 4) the method can also design the nanochannel graph with any shape according to the requirement, greatly simplifies the design and processing process of the nanochannel, and has wide application prospect in the fields of high heat flux chip heat dissipation, single molecule detection, nano-drug research and development, microfluidic chip and the like. In conclusion, the method is simple and convenient to operate and high in machining precision, the prepared nano channel is controllable in three-dimensional size, good in uniformity, capable of being integrally formed, free of a bonding process and good in sealing performance, and liquid leakage is not prone to occurring when the fluid medium moves along the nano channel.
According to a second aspect of the invention, a nanochannel is provided. According to an embodiment of the present invention, the nanochannel is obtained using the method of preparing a nanochannel described above. Compared with the prior art, the nano channel has the advantages of high processing precision, controllable three-dimensional size, better uniformity, capability of being integrally formed, no need of a bonding process, better sealing property and difficult leakage when a fluid medium moves along the nano channel. It should be noted that the features and effects described for the method for preparing the nanochannel are also applicable to the nanochannel, and are not described in detail herein.
According to a third aspect of the present invention, the present invention provides the use of the nanochannel and/or the preparation method described above in the fields of chip heat dissipation, single molecule detection, nanomedicine development, microfluidic chip. Compared with the prior art, the nano-channel and the method for preparing the nano-channel are used in the fields of high-heat-flux-density chip heat dissipation, single-molecule detection, nano-drug research and development, micro-fluidic chips and the like, so that the problems of uneven channel depth, easy leakage, blockage and the like caused by cover plate bonding in the existing nano-channel preparation method can be effectively avoided, and the processing precision of the nano-channel and the yield of products such as high-efficiency heat dissipation devices, nano-medicines, nano-fluidic chips and the like are improved to a great extent; in addition, the nano-channel graph with any shape can be designed according to requirements, the design and the processing process of the nano-channel are greatly simplified, and the method has great advantages and wide application prospect. It should be noted that the features and effects described for the above nanochannel and method of making a nanochannel are also applicable to this application, and are not described in detail here.
According to a fourth aspect of the invention, a nanodevice is presented. According to an embodiment of the present invention, the nano device has the nano channel and/or the nano channel obtained by the preparation method. Compared with the prior art, the nanometer channel in the nanometer device has higher precision, better uniformity and sealing performance, is not easy to leak when the fluid medium moves along the nanometer channel, and has more excellent product performance. It should be noted that the type of the nano-device is not particularly limited, and those skilled in the art can select the nano-device according to actual needs, for example, the nano-device can be a chip, a biosensor, a nano-fluidic device, etc. In addition, it should be noted that the features and effects described for the nanochannel and the method of fabricating a nanochannel described above are also applicable to the nanodevice, and are not repeated here.
The scheme of the invention will be explained with reference to the examples. It will be appreciated by those skilled in the art that the following examples are illustrative of the invention only and should not be taken as limiting the scope of the invention. The examples, where specific techniques or conditions are not indicated, are to be construed according to the techniques or conditions described in the literature in the art or according to the product specifications. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products commercially available.
Example 1
(1) Preparing single-layer graphene on a copper foil by adopting a traditional chemical vapor deposition method, then spin-coating PMMA (PMMA: polymethyl methacrylate, a high molecular polymer) on the surface of the single-layer graphene to be used as a supporting layer (for transferring graphene), removing a copper foil substrate by using a copper etching solution (wherein the etching solution is a mixed solution of copper sulfate, hydrochloric acid and water, and the concentrations of the copper sulfate and the hydrochloric acid are both 0.5mol/L), and then transferring the single-layer graphene to a silicon substrate with a silicon dioxide layer with uniform thickness attached on the surface, wherein the thickness of the silicon dioxide layer is 100nm, and the whole silicon wafer is a square of 10mm multiplied by 10 mm; the chip 1 was obtained as shown in fig. 10 (a).
(2) Then, a layer of photoresist (the model: ZEP520, the model: the photoresist below the graphene layer is positive photoresist, and the photoresist is dissolved in developing solution) with the thickness of 300nm is spin-coated on the graphene layer, the spin-coating speed is 6000 rpm, and the spin-coating time is about 40 seconds; developing the photoresist into a shape of a micron strip after ultraviolet exposure by adopting an electron beam lithography technology, wherein the model of an electron beam exposure device in the process is JBX-6300FS, the exposure current is 2000pA, the size of an exposure area is about 500 Mum multiplied by 500 Mum, and the exposure time is about 1.5 minutes, and then, the photoresist in the exposure area needs to be dissolved by a special developing solution (model: ZED-N50) so as to form the micron-wide photoresist strip, as shown in (b) in FIG. 10; and then exposed to an oxygen plasma environment, and the graphene not covered by the photoresist is etched away, so as to form a graphene strip with a width of micrometers, wherein the width W of the etched graphene strip determines the width of the nanochannel. Then, the photoresist is removed and the chip 2 is obtained by slicing, as shown in fig. 10 (c).
(3) And (3) spin-coating photoresist on the surface of the graphene strip of the chip 2, and then continuing to adopt an electron beam lithography technology to develop the photoresist into a shape of a micron strip, referring to fig. 8, when the strip pattern is in a vertical relation with the strip pattern in the step (2), the cross-sectional view of the finally prepared nano channel along the height direction is a rectangle, wherein it needs to be pointed out that the width of the photoresist after development determines the length L of the nano channel, and the relevant parameters of the step are consistent with those in the step (2). The chip 3 was obtained as shown in (d) of FIG. 10.
(4) Etching the silicon dioxide layer exposed on the surface of the chip 3 (uncovered by the photoresist strip) and the silicon dioxide layer below the graphene strip by adopting a hydrofluoric acid wet etching method, wherein the concentration of the hydrofluoric acid used in the process is 4.5 wt%, and the hydrofluoric acid needs to be immersed and etched for 10 minutes; after etching, the silicon dioxide layer uncovered by the photoresist and the silicon dioxide layer below the graphene are completely etched, the silicon dioxide layer uncovered by the graphene under the photoresist is hardly etched, in addition, the photoresist layer above the single-layer graphene is well preserved in the process, the photoresist layer forms a natural closed cover plate, and forms a complete closed nano-channel together with a channel formed by etching below the natural closed cover plate. It is also noted here that the thickness of the silicon dioxide layer being etched determines the height of the nanochannel. And finally, exposing the nano-channel to an oxygen plasma environment to etch away redundant graphene strips at two ends of the nano-channel, so as to obtain a chip 4, as shown in fig. 10 (e). And after the etching process is finished, cleaning the chip by using deionized water, and blow-drying by using dry nitrogen after the cleaning is finished to obtain a final nano-channel sample.
The picture of the final sample obtained in the embodiment after being subjected to high-power magnification by an optical microscope is shown in the attached drawing 11, wherein the upper and lower framed areas in the picture are two nanochannels which are successfully prepared, and the nanochannels prepared by the method have better uniformity; tests show that the nano channel has better sealing property.
It should be noted that the present invention is not limited to the above embodiments, and the method for processing a nanochannel based on the graphene anisotropic etching principle proposed by the present invention can be widely applied to the field and other fields related thereto, and can be implemented in various other embodiments, for example, the processing accuracy can be further improved by combining with other preparation processes, and therefore, the design concept of the present invention, and the preparation of a nanochannel by making some simple changes or alterations or mashup designs, will fall within the scope of the present invention.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (10)

1. A method of making a nanochannel, comprising:
(1) layer-by-layer formation of SiO on a silicon substrate2A layer, a single graphene layer, and a strip photoresist layer, wherein the shape and size of the nanochannels to be obtained are controlled based on:
the SiO2The thickness of the layer;
the shape and size of the single graphene layer;
the shape and size of the strip-shaped photoresist layer;
the position, shape and size of the overlapping region of the single graphene layer and the strip-shaped photoresist layer;
(2) wet etching to remove SiO uncovered by the belt-shaped photoresist layer on the silicon substrate by adopting hydrofluoric acid solution2SiO of the layer and the overlap region2A layer to form a nanochannel in the overlap region.
2. The method of claim 1, wherein at least one of the following conditions is satisfied:
the SiO2Uniform layer thickness of the SiO2The thickness of the layer is 1 to 500 nm;
the distances of the overlapping area in the length direction and the width direction of the belt-shaped photoresist layer are respectively and independently 500 nm-10 mu m;
the distance of the single graphene layer in the width/length direction of the strip-shaped photoresist layer is not less than the width/length of the strip-shaped photoresist layer, and the distance in the length/width direction of the strip-shaped photoresist layer is less than the length/width of the strip-shaped photoresist layer;
the edges of the single graphene layer and/or the strip-shaped photoresist layer respectively and independently comprise at least one selected from a straight line, a curve, a wavy line or a zigzag line;
the concentration of the hydrofluoric acid solution is 3-6 wt%;
the nano-channel is a nano-channel with a regular or irregular structure.
3. The method of any one of claims 1 or 2, wherein step (1) further comprises at least one of:
(1-1) subjecting the silicon substrate to thermal oxidation or chemical vapor deposition to form the SiO2A layer;
(1-2) forming a single graphene layer on a copper foil by using a chemical vapor deposition method; forming a polymethyl methacrylate support layer on the single graphene layer; removing the copper foil by adopting an etching method; transferring the single graphene layer to the SiO using the support layer2Removing the support layer;
(1-3) controlling the shape and size of the strip-shaped photoresist layer by using an electron beam lithography method, and/or controlling the shape and size of the single graphene layer by using the photoresist layer and an oxygen plasma environment.
4. The method of claim 3, wherein step (1-3) further comprises:
forming a first photoresist layer over the single graphene layer, developing the first photoresist layer into a first strip-shaped photoresist layer using electron beam lithography; removing the graphene layer which is not covered by the first strip-shaped photoresist layer by adopting an oxygen plasma environment so as to obtain a strip-shaped graphene layer;
and removing the first strip-shaped photoresist layer, forming a second photoresist layer on the strip-shaped graphene layer, developing the second photoresist layer into a second strip-shaped photoresist layer by using an electron beam lithography method, and defining the position, the shape and the size of the nano channel by using the strip-shaped graphene layer and the second strip-shaped photoresist layer.
5. The method of claim 4, wherein at least one of the following conditions is satisfied:
the included angle between the second strip-shaped photoresist layer and the strip-shaped graphene layer is 1-90 degrees;
the included angle between the second strip-shaped photoresist layer and the strip-shaped graphene layer is 45-90 degrees;
the second strip-shaped photoresist layers are arranged at intervals in the length direction of the strip-shaped graphene layer and respectively and independently form an overlapping region with the strip-shaped graphene layer;
the edges of the graphene strip layers and/or the second photoresist strip layers each independently include at least one selected from a straight line, a curved line, a wavy line, or a zigzag line.
6. The method of claim 5, wherein at least one of the following conditions is satisfied:
the second strip-shaped photoresist layer is perpendicular to the strip-shaped graphene layer;
the edges of the strip graphene layer and the second strip photoresist layer in the overlapping region are straight lines;
the second strip-shaped photoresist layers are arranged on the strip-shaped graphene layer, and a plurality of overlapped regions which are spaced and have the same shape are formed on the second strip-shaped photoresist layers.
7. A method according to any one of claims 4 to 6, comprising:
1) formation of SiO on silicon substrate2A layer;
2) forming a single-layer graphene layer on the copper foil by using a chemical vapor deposition method; forming a polymethyl methacrylate support layer on the single graphene layer; removing the copper foil by adopting an etching method; transferring the single graphene layer to the SiO using the support layer2Removing the support layer;
3) forming a first photoresist layer over the single graphene layer, developing the first photoresist layer into a first strip-shaped photoresist layer using electron beam lithography; removing the graphene layer uncovered by the first strip-shaped photoresist by adopting an oxygen plasma environment so as to obtain a strip-shaped graphene layer;
4) removing the first strip-shaped photoresist layer and forming a second photoresist layer on the strip-shaped graphene layer, developing the second photoresist layer into a second strip-shaped photoresist layer by using an electron beam lithography method, and defining the position, the shape and the size of a nano channel by using the strip-shaped graphene layer and the second strip-shaped photoresist layer;
5) and (3) placing the silicon substrate obtained in the step 4) in a hydrofluoric acid solution for wet etching so as to form the nano-channel.
8. A nanochannel according to any one of claims 1 to 7, wherein the nanochannel is produced by the production method according to any one of claims 1 to 7.
9. Use of the nanochannel according to claim 8 and/or the preparation method according to any one of claims 1 to 7 in the fields of chip heat dissipation, single molecule detection, nano-drug development, microfluidic chips.
10. A nano device, characterized in that the nano device has the nano channel of claim 8 and/or the nano channel obtained by the preparation method of any one of claims 1 to 7.
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