CN113014254A - Phase-locked loop circuit - Google Patents
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The present application relates to a phase-locked loop circuit, wherein the phase-locked loop circuit includes: a voltage controlled oscillator for generating a high frequency clock signal; the frequency divider is used for dividing the frequency of the high-frequency clock signal to obtain a low-frequency signal; the phase frequency detector is used for comparing the low-frequency signal with the reference signal in a time domain to obtain a time domain fast and slow signal; the charge pump circuit is used for converting the time domain fast and slow signals into current amplitude signals; a loop filter for converting the current amplitude signal into a voltage signal for feedback control of the voltage controlled oscillator; and the automatic frequency calibration circuit is connected with the voltage-controlled oscillator and used for determining a capacitor array control word of the voltage-controlled oscillator, wherein the capacitor array control word is used for adjusting the frequency of a high-frequency clock signal generated by the voltage-controlled oscillator. By the method and the device, the problem of low locking speed of the PLL in the related technology is solved, and fast frequency switching of the high-precision low-noise high-frequency clock signal generated by the PLL on the chip is realized.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a phase-locked loop circuit.
Background
The general crystal oscillator can not realize very high frequency due to the process and cost, and when high frequency application is needed, the high frequency is converted by a Voltage Controlled Oscillator (VCO), but the clock signal generated by the method is unstable, so that the stable and high frequency clock signal is realized by utilizing a phase-locked loop, and no residual frequency difference exists when locking. Phase Locked Loop (PLL) -based frequency synthesizers are important circuit components in a variety of applications, particularly in communication systems. To remove good signal purity (i.e., low phase noise and low spurs), lock-in speed is also an important design requirement. The fast lock function is especially important for systems requiring frequency hopping operation, and the frequency hopping settling speed greatly limits the speed of system mode switching.
In order to realize fast switching of two operating frequencies, the PLL module needs to realize a fast frequency switching function. The cut-off time is the sum of the Automatic Frequency Calibration (AFC) and the fine lock time. The typical PLL lock time is around tens of microseconds, which far exceeds the 2 microsecond cut-off time requirement here. It is therefore desirable to design a PLL fast lock technique. The PLL of the related art focuses more on the performances of wide coverage, low power consumption, low jitter, and the like, and the research on the fast locking technique of the PLL, especially for the wide frequency hopping distance, is not enough in the aspect of fast locking. In prior studies, there have been few designs that can compromise high accuracy with extremely fast lock speeds.
At present, no effective solution is provided for the problem of slow locking speed of the PLL in the related art.
Disclosure of Invention
The embodiment of the application provides a phase-locked loop circuit to at least solve the problem of slow locking speed of a PLL in the related art.
In a first aspect, an embodiment of the present application provides a phase-locked loop circuit, including:
a voltage controlled oscillator for generating a high frequency clock signal;
the frequency divider is connected with the voltage-controlled oscillator and is used for dividing the frequency of the high-frequency clock signal to obtain a low-frequency signal;
the phase frequency detector is connected with the frequency divider and used for comparing the low-frequency signal with the reference signal in a time domain to obtain a time domain fast-slow signal;
the charge pump circuit is connected with the phase frequency detector and is used for converting the time domain fast and slow signals into current amplitude signals;
the loop filter is connected with the charge pump circuit and is used for converting the current amplitude signal into a voltage signal so as to feedback control the voltage-controlled oscillator;
and the automatic frequency calibration circuit is connected with the voltage-controlled oscillator and used for determining a capacitor array control word of the voltage-controlled oscillator, wherein the capacitor array control word is used for adjusting the frequency of the high-frequency clock signal generated by the voltage-controlled oscillator.
In some of these embodiments, the automatic frequency calibration circuit comprises:
a main state machine and a processing state sub-state machine;
the main state machine uses a reference clock, enters an initial state in the first period, and enters a cyclic process of a counting state and a processing state when a starting signal is detected.
In some embodiments, in the counting state, rising edges of the high frequency clock signal output by the voltage controlled oscillator are counted.
In some embodiments, in the processing state, the count value in the count state is subtracted from the frequency division ratio of the frequency divider to obtain an error value, and the capacitor array control word of the voltage controlled oscillator is adjusted according to the error value.
In some of these embodiments, adjusting the capacitive array control word of the voltage controlled oscillator according to the error value comprises:
judging whether the capacitor array control word selects a left sub-tree or a right sub-tree according to the polarity of the error value;
and judging whether the control word of the sub-tree or the control word of the father node is selected by the capacitor array control word according to the error value.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the phase error compensation module is used for compensating the phase difference between the reference signal and the clock signal output by the frequency divider.
In some embodiments, the phase error compensation module is configured to:
after the automatic frequency calibration circuit determines a capacitor array control word of the voltage-controlled oscillator, performing first phase error compensation on the reference signal and a clock signal output by the frequency divider by changing the frequency division ratio of the frequency divider;
and when the frequency of the reference signal is the same as that of the clock signal output by the frequency divider, performing second phase error compensation on the reference signal and the clock signal output by the frequency divider by changing the frequency dividing ratio of the frequency divider, so that the frequency and the phase of the reference signal and the clock signal output by the frequency divider are synchronous.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the other charge pump circuit is connected with the loop filter and is used for synchronously charging and discharging one capacitor in the loop filter.
In some embodiments, the switching of the loop bandwidth of the phase-locked loop circuit is performed by switching a current control word of the charge pump circuit and switching a capacitance resistance control word of the loop filter.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the locking detection circuit is respectively connected with the frequency divider and the phase frequency detector and is used for judging the locking condition through digital signals acquired by the trigger.
Compared with the related art, the phase-locked loop circuit provided by the embodiment of the application generates a high-frequency clock signal through the voltage-controlled oscillator; the frequency divider divides the frequency of the high-frequency clock signal to obtain a low-frequency signal; the phase frequency detector compares the low-frequency signal with a reference signal in a time domain to obtain a time domain fast and slow signal; the charge pump circuit converts the time domain fast and slow signals into current amplitude signals; a loop filter converts the current amplitude signal into a voltage signal to feedback control the voltage-controlled oscillator; an automatic frequency calibration circuit determines a capacitor array control word of the voltage controlled oscillator; the phase error compensation module compensates the phase difference between the low-frequency signal and the reference signal at the key node twice, solves the problem of low locking speed of the PLL in the related technology, and realizes the rapid frequency switching of the on-chip high-precision low-noise high-frequency clock signal generated by the PLL.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present application;
FIG. 2a is a schematic diagram of a fast lock auto frequency calibration circuit and phase error compensation state machine according to the preferred embodiment of the present application;
figure 2b is a schematic diagram of a 4-way quadrature-phase divided-by-4 VCO clock according to the preferred embodiment of the present application;
FIG. 2c is a schematic illustration of a process flow of process states according to a preferred embodiment of the present application;
FIG. 3 is a schematic diagram of phase error compensation according to a preferred embodiment of the present application;
fig. 4 is a schematic diagram of a loop bandwidth switching technique according to a preferred embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present application without any inventive step are within the scope of protection of the present application.
It is obvious that the drawings in the following description are only examples or embodiments of the present application, and that it is also possible for a person skilled in the art to apply the present application to other similar contexts on the basis of these drawings without inventive effort. Moreover, it should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of ordinary skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments without conflict.
Unless defined otherwise, technical or scientific terms referred to herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar words throughout this application are not to be construed as limiting in number, and may refer to the singular or the plural. The present application is directed to the use of the terms "including," "comprising," "having," and any variations thereof, which are intended to cover non-exclusive inclusions; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to the listed steps or elements, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Reference to "connected," "coupled," and the like in this application is not intended to be limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as referred to herein means two or more. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. Reference herein to the terms "first," "second," "third," and the like, are merely to distinguish similar objects and do not denote a particular ordering for the objects.
Before the embodiments of the present application are explained in detail, the technical terms and abbreviations in the embodiments of the present application are explained as follows:
pll (phase Locked loop): phase-locked loop
Vco (voltage Controlled oscillator): voltage controlled oscillator
Afc (auto Frequency calibration): automatic frequency calibration
Pec (phase Error compensation): phase error compensation
PFD (Phase-Frequency Detector): phase frequency detector
Cp (charge pump): charge pump
Lf (loop filter): loop filter
Pdiv (programmable divider): programmable frequency divider
The embodiment of the application provides a phase-locked loop circuit.
Fig. 1 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present application, as shown in fig. 1, the phase-locked loop circuit including:
a voltage controlled oscillator for generating a high frequency clock signal;
the frequency divider is connected with the voltage-controlled oscillator and is used for dividing the frequency of the high-frequency clock signal to obtain a low-frequency signal;
the phase frequency detector is connected with the frequency divider and used for comparing the low-frequency signal with the reference signal in a time domain to obtain a time domain fast-slow signal;
the charge pump circuit is connected with the phase frequency detector and is used for converting the time domain fast and slow signals into current amplitude signals;
the loop filter is connected with the charge pump circuit and is used for converting the current amplitude signal into a voltage signal so as to feedback control the voltage-controlled oscillator;
and the automatic frequency calibration circuit is connected with the voltage-controlled oscillator and used for determining a capacitor array control word of the voltage-controlled oscillator, wherein the capacitor array control word is used for adjusting the frequency of the high-frequency clock signal generated by the voltage-controlled oscillator.
The PLL fast locking technique in the embodiment of the present application mainly includes two aspects: and the fast AFC and the PEC are integrated in an AFC module and are realized by matching with the PFD and the CP. The structure of the designed PLL is shown in fig. 1. The PLL clock generator is a typical negative feedback system with high feed forward gain and high precision and high linearity of the digital feedback path. After a high-frequency clock signal of a Voltage Controlled Oscillator (VCO) is subjected to digital frequency division to low frequency through a programmable frequency divider (PDIV), the high-frequency clock signal and a reference clock signal are advanced or lagged in a time domain through a Phase Frequency Detector (PFD), a time domain fast-slow signal is converted into a current amplitude signal through a charge pump Circuit (CP), a Loop Filter (LF) averages the current signal into a voltage signal, and then the voltage controlled oscillator is subjected to feedback control. In addition, in a serial communication link, the clock generator is very far from the transmitter and the receiver on-chip, and the driver is also an essential module for the clock circuit.
The VCO used in the embodiments of the present application is an LC-VCO structure. In order to realize the coverage of the wide band from 6.4GHz to 10GHz, the VCO capacitor needs to be designed into a 7bit array. The larger the control word value of the control array, the smaller the capacitance value, and the higher the output clock frequency of the VCO. The purpose of AFC is to automatically generate an optimal VCO capacitor array control word based on the current system operating environment.
In some of these embodiments, the automatic frequency calibration circuit comprises:
a main state machine and a processing state sub-state machine;
the main state machine uses a reference clock, enters an initial state in the first period, and enters a cyclic process of a counting state and a processing state when a starting signal is detected.
In some embodiments, in the counting state, rising edges of the high frequency clock signal output by the voltage controlled oscillator are counted.
In some embodiments, in the processing state, the count value in the count state is subtracted from the frequency division ratio of the frequency divider to obtain an error value, and the capacitor array control word of the voltage controlled oscillator is adjusted according to the error value.
In some of these embodiments, adjusting the capacitive array control word of the voltage controlled oscillator according to the error value comprises:
judging whether the capacitor array control word selects a left sub-tree or a right sub-tree according to the polarity of the error value;
and judging whether the control word of the sub-tree or the control word of the father node is selected by the capacitor array control word according to the error value.
The fast AFC consists of a main state machine and a process state sub-state machine, as shown in fig. 2 a. First, the AFC operates with the VCO control voltage forced to 400mV in order to create a stable environment for the AFC process, and 400mV is a more desirable locking voltage, thus improving the accuracy of the final control word code. The AFC main state machine uses a reference clock, and enters an initial state IDLE in the first period. When the start signal afc _ start signal is detected as high, a count-process loop may be entered. The AFC _ start signal is here determined by the enable signal and can only be asserted once in case the AFC function restarts out of control. One cycle of the AFC includes a counting phase and a processing phase.
The next state is the COUNT state AFC _ COUNT, in which the VCO output clock rising edge is counted. Since the maximum frequency here is 10GHz, there are high demands on the circuit. Thus 4 quadrature phase divided by 4 VCO clocks are selected as the sampled signal as shown in figure 2 b. In such a period, four paths of clocks are sampled by the reference clock at the same time, and the number of the rising edges added together is the number of the rising edges of the VCO output clock in a reference frequency, and under the condition of correct frequency, the number is equal to the preset frequency division ratio.
The counting state is to cooperate with the processing state, and the next state of AFC _ COUNT is the processing state AFC _ PROCESS. During this period, the last state count is processed. Specifically, as shown in fig. 2c, the count value of the current period is subtracted from the frequency dividing ratio to obtain an error value, and the error value is compared with the error value obtained last time. At the same time, the polarity of the error value is also recorded. It is determined by polarity whether the next control word should select the left or right sub-tree. If the error value is positive, it indicates that the VCO output clock frequency is too high, the current control word is too large, and the left sub-tree is selected in the next cycle, otherwise, the right sub-tree is selected. In the PROCESS state, the selection of the control word between the subtree and the parent node is determined by the magnitude of the error value under two control words. If the error value of the subtree is small, the control word value of the subtree is left, otherwise, the control word of the parent node is finally returned. The AFC searches downwards from the middle control word until an odd control word appears, and finally returns the control word recorded with the minimum error value, namely the optimal control word. This is the AFC technique that dichotomously finds the optimal control word. The AFC is completed by using a dichotomy, and 7-step counting-processing process is needed for outputting a control word by using the 7-bit AFC. The total time is 2T (IDLE + START) +7 x 2T (COUNT + PROCESS), for a total of 16 cycles of 832ns time, leaving enough time for the subsequent fine PLL lock.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the phase error compensation module is used for compensating the phase difference between the reference signal and the clock signal output by the frequency divider.
In some embodiments, the phase error compensation module is configured to:
after the automatic frequency calibration circuit determines a capacitor array control word of the voltage-controlled oscillator, performing first phase error compensation on the reference signal and a clock signal output by the frequency divider by changing the frequency division ratio of the frequency divider;
and when the frequency of the reference signal is the same as that of the clock signal output by the frequency divider, performing second phase error compensation on the reference signal and the clock signal output by the frequency divider by changing the frequency dividing ratio of the frequency divider, so that the frequency and the phase of the reference signal and the clock signal output by the frequency divider are synchronous.
The phase error compensation section has a total of two phase compensations as shown in fig. 3. First, at the end of AFC, there is a phase difference between the reference clock and the divider output clock. The PEC module detects the value of this phase difference and immediately changes the division ratio to compensate. However, the frequencies of the two clocks are different, so the phase difference is accumulated until the frequencies of the two clock signals are the same, the phase difference reaches the maximum value, namely the second compensation point, the phase difference is compensated by changing the frequency division ratio, the frequencies and the phases of the two clock signals are synchronous, and the locking is quickly finished under a certain margin. Here the detection of the phase difference is achieved by sampling the fast clock with the slow clock. The PEC starts counting rising edges of the divided by 4 VCO output clock when the rising edge of the PFD output UP signal arrives. The count value multiplied by 4 is regarded as the current phase difference. A check for phase error is made each time a cycle. If the phase error exceeds some threshold level, appropriate compensation phases are provided accordingly to reduce the phase error. Phase compensation is accomplished by dynamically changing the divide ratio to shift the output edges of the divider accordingly to change the phase. This process is repeated until the frequency error (and hence the integrated phase error) falls sufficiently small to eventually reach a lock-in condition.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the other charge pump circuit is connected with the loop filter and is used for synchronously charging and discharging one capacitor in the loop filter.
As shown in fig. 1, the capacitance of C2 in LF is usually large, several hundred picofarads, much larger than the values of C1 and C3, and the time constant is very large, which results in a long charging process of C2, which exceeds the AFC time. That is, after AFC is over, when the VCO control voltage is out of 400mV control, charge will flow backwards, and C1 will discharge C2 to charge, which directly results in a sudden drop of the VCO control voltage and loss of the fast locking function. To avoid this, a proprietary CP is required to charge and discharge C2 synchronously. The current value is calculated through the capacitance value proportional relation and the magnitude of the two CP currents.
In some embodiments, the switching of the loop bandwidth of the phase-locked loop circuit is performed by switching a current control word of the charge pump circuit and switching a capacitance resistance control word of the loop filter.
A simple analysis can conclude that the larger the loop bandwidth of the PLL, the shorter the lock time. But the noise performance cannot tolerate an excessive bandwidth when the PLL is operating normally. Therefore, the embodiments of the present application provide a loop bandwidth switching technique, as shown in fig. 4, the switching process is completed by CP current control word switching and LF rc array control word switching. The CP and the LF are matched with the switching loop bandwidth to ensure that the switched small-bandwidth PLL is still stable.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the locking detection circuit is respectively connected with the frequency divider and the phase frequency detector and is used for judging the locking condition through digital signals acquired by the trigger.
Generally, the output phase of the programmable frequency divider after loop locking will align with the reference clock, and according to the characteristic that the phase difference is small when the analog signal is locked, the embodiment of the present application adopts a lock detection circuit based on analog phase difference judgment, and judges the locking condition through digital signals mutually acquired by flip-flops. From the whole signal link, the two-frequency divider at the front end is used for eliminating poor duty ratio, the next delay module is used for eliminating the problem of delay mismatching caused by different bilateral distances on the layout, the delay modules on the mutually-adopted paths can control the threshold value of phase difference detection, and the threshold value can be digitally controlled to control errors brought by the immune process. The exclusive-nor (Xnor) determines the digital level outputted by the flip-flop, and when the digital level is high at the same time, it will give a high level, and it should be noted that due to the introduction of the frequency division by two, it may cause the rising edge at the reference time of the first flip to be aligned with the falling edge of the frequency division signal, so that when the rising edge is low at the same time, it will give a high level to be supplied to the following operation of the up/down counter.
The embodiment of the application comprises the following key technologies:
(1) a fast AFC technique: under the condition of fixing the VCO control voltage, counting the output clock of the 4-frequency-division VCO by using the reference clock, comparing the obtained frequency division ratio with a preset frequency division ratio, searching a binary tree according to the polarity and the absolute value of the error value, and finally outputting the optimal VCO capacitor array control word under the current working environment.
(2) A phase error compensation technique: after the frequency is changed, the phase error is accumulated rapidly, the PEC detects the phase difference, the real-time frequency dividing ratio is subjected to the operation of adding or subtracting the phase difference by judging the polarity of the phase difference, and the frequency dividing ratio of the next period is restored to the default value. Two phase error compensations, one first and the other, are completed through the process to replace the conventional stabilizing process of the PLL.
(3) The loop bandwidth switching technology comprises the following steps: the switching process is completed by CP current control word switching and LF capacitor resistor array control word switching. The CP and the LF are matched with the switching loop bandwidth to ensure that the switched small-bandwidth PLL is still stable.
(4) LF charge backflow treatment technology: a special CP is designed to synchronously charge and discharge the C2, and the current value is calculated through the capacitance value proportional relation and the current magnitude of the two CPs.
According to the embodiment of the application, when the PLL needs to perform wide-range frequency hopping operation, the PLL can reach a locking state within 2 us.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A phase-locked loop circuit, comprising:
a voltage controlled oscillator for generating a high frequency clock signal;
the frequency divider is connected with the voltage-controlled oscillator and is used for dividing the frequency of the high-frequency clock signal to obtain a low-frequency signal;
the phase frequency detector is connected with the frequency divider and used for comparing the low-frequency signal with the reference signal in a time domain to obtain a time domain fast-slow signal;
the charge pump circuit is connected with the phase frequency detector and is used for converting the time domain fast and slow signals into current amplitude signals;
the loop filter is connected with the charge pump circuit and is used for converting the current amplitude signal into a voltage signal so as to feedback control the voltage-controlled oscillator;
and the automatic frequency calibration circuit is connected with the voltage-controlled oscillator and used for determining a capacitor array control word of the voltage-controlled oscillator, wherein the capacitor array control word is used for adjusting the frequency of the high-frequency clock signal generated by the voltage-controlled oscillator.
2. The phase-locked loop circuit of claim 1, wherein the automatic frequency calibration circuit comprises:
a main state machine and a processing state sub-state machine;
the main state machine uses a reference clock, enters an initial state in the first period, and enters a cyclic process of a counting state and a processing state when a starting signal is detected.
3. The phase-locked loop circuit of claim 2, wherein in the count state, rising edges of the high-frequency clock signal output by the voltage-controlled oscillator are counted.
4. The pll circuit of claim 2, wherein in the processing state, the count value in the count state is subtracted from the frequency division ratio of the frequency divider to obtain an error value, and the vco capacitor array control word is adjusted according to the error value.
5. The phase-locked loop circuit of claim 4, wherein adjusting the capacitor array control word of the voltage-controlled oscillator according to the error value comprises:
judging whether the capacitor array control word selects a left sub-tree or a right sub-tree according to the polarity of the error value;
and judging whether the control word of the sub-tree or the control word of the father node is selected by the capacitor array control word according to the error value.
6. The phase-locked loop circuit of claim 1, further comprising:
and the phase error compensation module is used for compensating the phase difference between the reference signal and the clock signal output by the frequency divider.
7. The phase-locked loop circuit of claim 6, wherein the phase error compensation module is configured to:
after the automatic frequency calibration circuit determines a capacitor array control word of the voltage-controlled oscillator, performing first phase error compensation on the reference signal and a clock signal output by the frequency divider by changing the frequency division ratio of the frequency divider;
and when the frequency of the reference signal is the same as that of the clock signal output by the frequency divider, performing second phase error compensation on the reference signal and the clock signal output by the frequency divider by changing the frequency dividing ratio of the frequency divider, so that the frequency and the phase of the reference signal and the clock signal output by the frequency divider are synchronous.
8. The phase-locked loop circuit of any of claims 1 to 7, further comprising:
and the other charge pump circuit is connected with the loop filter and is used for synchronously charging and discharging one capacitor in the loop filter.
9. The phase-locked loop circuit according to any one of claims 1 to 7, wherein the switching of the loop bandwidth of the phase-locked loop circuit is performed by switching a current control word of the charge pump circuit and switching a capacitance resistance control word of the loop filter.
10. The phase-locked loop circuit of any of claims 1 to 7, further comprising:
and the locking detection circuit is respectively connected with the frequency divider and the phase frequency detector and is used for judging the locking condition through digital signals acquired by the trigger.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113644912A (en) * | 2021-07-27 | 2021-11-12 | 矽力杰半导体技术(杭州)有限公司 | Phase-locked loop circuit and control method thereof |
| CN114142854A (en) * | 2021-11-16 | 2022-03-04 | 北京大学 | Frequency compensation circuit, phase-locked loop compensation circuit, method, device, and storage medium |
| CN114513204A (en) * | 2021-12-28 | 2022-05-17 | 宁波奥拉半导体股份有限公司 | Multi-loop phase-locked loop circuit and circuit board assembly |
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| CN117097329A (en) * | 2023-10-09 | 2023-11-21 | 芯耀辉科技有限公司 | Digital signal processing method and system |
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