CN113014253A - Frequency synthesizer, frequency synthesizing method, electronic device and storage medium - Google Patents
Frequency synthesizer, frequency synthesizing method, electronic device and storage medium Download PDFInfo
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Abstract
The embodiment of the invention relates to the field of communication and discloses a frequency synthesizer, a frequency synthesizing method, electronic equipment and a storage medium. In the present invention, a frequency synthesizer includes: a reference crystal oscillator, an integer frequency synthesizer circuit and a fractional frequency synthesizer circuit; the reference crystal oscillator is used for providing a reference clock signal for the integer frequency synthesizer circuit; the integer frequency synthesizer circuit is used for providing a reference clock signal for the decimal frequency synthesizer circuit, and the decimal frequency synthesizer circuit obtains a phase discrimination frequency according to the reference clock signal; the decimal frequency synthesizer circuit is used for generating the frequency signal that the decimal spurious value is greater than the predetermined threshold value according to phase discrimination frequency, through regarding the output of integer frequency synthesizer as decimal frequency synthesizer's reference clock, has simplified circuit structure, has reduced the control degree of difficulty to guaranteed that decimal frequency synthesizer circuit phase discrimination frequency can change in a flexible way, and then can both realize good decimal spurious evasion when exporting different frequency signal, promote output signal's spectral quality.
Description
Technical Field
Embodiments of the present invention relate to the field of communications, and in particular, to a frequency synthesizer, a frequency synthesizing method, an electronic device, and a storage medium.
Background
With the development of communication technology, in the process of electronic communication, signals are synthesized and output by a phase-locked loop frequency synthesizer, and the frequency bandwidth of the output signals becomes larger and larger. When a decimal frequency synthesizer needs to output a radio frequency signal with a wide frequency band and full coverage, the situation that decimal spurs fall within the loop bandwidth of a phase-locked loop can inevitably occur under the traditional scheme, the problem of how to suppress decimal spurs is always a technical problem, the existing decimal spurs suppression method is mainly realized by using two or more decimal frequency synthesizer circuits, namely, one or more decimal frequency synthesizers are connected behind a reference clock signal to realize phase demodulation frequency adjustment input to the final decimal frequency synthesizer, thereby suppressing decimal spurs of the final decimal frequency synthesizer. Or a plurality of reference crystal oscillators are adopted to reference the decimal frequency synthesizer, different reference sources are switched through a switch, and the switching of the reference frequency input to the final decimal frequency synthesizer is realized, so that the phase demodulation frequency adjustment of the final decimal frequency synthesizer is realized to realize the decimal spurious suppression.
When signal synthesis is carried out, a relatively complex circuit structure is needed for adjusting the phase demodulation frequency, the control is complex when the phase demodulation frequency is switched, and new decimal spurs can be introduced.
Disclosure of Invention
An object of embodiments of the present invention is to provide a frequency synthesizer, a frequency synthesizing method, an electronic device, and a storage medium, which enable flexible switching of a phase discrimination frequency according to a frequency of an output signal, achieve good avoidance of fractional spurs, reduce circuit complexity and control difficulty, and improve a frequency spectrum quality of the output signal.
To solve the above technical problem, an embodiment of the present invention provides a frequency synthesizer, including: a reference crystal oscillator, an integer frequency synthesizer circuit and a fractional frequency synthesizer circuit; the reference crystal oscillator is connected with a reference clock input end of the integer frequency synthesizer circuit and is used for providing a reference clock signal for the integer frequency synthesizer circuit; the output end of the integer frequency synthesizer circuit is connected with the reference clock input end of the decimal frequency synthesizer circuit and is used for providing a reference clock signal for the decimal frequency synthesizer circuit and obtaining the phase discrimination frequency for the decimal frequency synthesizer circuit according to the reference clock signal; the decimal frequency synthesizer circuit is used for generating a frequency signal of which the decimal spurious value is greater than a preset threshold value according to the phase discrimination frequency.
The embodiment of the invention also provides a frequency synthesis method, which comprises the following steps: applied to a frequency synthesizer comprising: the circuit comprises a reference crystal oscillator, an integer frequency synthesizer circuit and a decimal frequency synthesizer circuit, wherein the reference crystal oscillator is connected with the reference clock input end of the integer frequency synthesizer circuit, and the output end of the integer frequency synthesizer circuit is connected with the reference clock input end of the decimal frequency synthesizer circuit; the frequency synthesis method comprises the following steps: acquiring an output signal of the integer frequency synthesizer circuit, and inputting the output signal into the decimal frequency synthesizer circuit as a reference clock signal of the decimal frequency synthesizer circuit; detecting whether a decimal stray value of a frequency signal generated by a decimal frequency synthesizer circuit is greater than a preset threshold value; if the frequency is not greater than the preset threshold, adjusting the output signal of the integer frequency synthesizer circuit, and detecting whether the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold again until the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold.
An embodiment of the present invention also provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the frequency synthesis method.
Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which when executed by a processor implements the frequency synthesis method described above.
Compared with the prior art, the embodiment of the invention adjusts the reference clock signal of the decimal frequency synthesizer circuit by using the output of the integer frequency synthesizer circuit as the reference clock of the decimal frequency synthesizer circuit and adjusting the output of the integer frequency synthesizer circuit, thereby ensuring that the phase discrimination frequency of the decimal frequency synthesizer circuit can be flexibly adjusted according to the frequency of the output signal, and further realizing that good decimal stray evasion can be carried out when signals of all frequencies are output; the output of the integer frequency synthesizer circuit is used as a reference clock of the decimal frequency synthesizer circuit, so that the problems of complex circuit structure and control mode caused by the need of a plurality of decimal frequency synthesizer circuits are avoided, the introduction of new decimal spurs is avoided, and the frequency spectrum quality of output signals is improved.
In addition, the integer frequency synthesizer circuit includes: the phase detector comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider and a second frequency divider; the first input end of the first phase discriminator is connected with the reference crystal oscillator, the second input end of the first phase discriminator is connected with the output end of the first frequency divider, the output end of the first phase discriminator is connected with the input end of the first loop filter, and the first phase discriminator is used for discriminating a first phase discrimination frequency determined according to a reference clock signal provided by the reference crystal oscillator and a feedback signal of the first voltage-controlled oscillator after frequency division, and transmitting a phase discrimination result to the first loop filter; the output end of the first loop filter is connected with the input end of the first voltage-controlled oscillator and used for generating a first control signal according to the phase discrimination result and transmitting the first control signal to the first voltage-controlled oscillator; the feedback output end of the first voltage-controlled oscillator is connected with the input end of the first frequency divider, and the signal output end of the first voltage-controlled oscillator is connected with the input end of the second frequency divider and used for adjusting the frequency of a signal to be output, outputting a frequency signal and transmitting a feedback signal to the first frequency divider; the first frequency divider is used for dividing the frequency of a feedback signal of the first voltage-controlled oscillator; the output end of the second frequency divider is connected with the reference clock input end of the decimal frequency synthesizer circuit and used for dividing the frequency of the output signal of the first voltage-controlled oscillator, and the frequency of the output signal can be adjusted according to the reference clock signal required by the decimal frequency synthesizer through frequency division and adjustment of the output signal of the decimal frequency synthesizer circuit, so that the decimal frequency synthesizer circuit can well avoid the decimal stray of the output signal according to the phase discrimination frequency corresponding to the reference clock signal.
In addition, the integer frequency synthesizer circuit includes: the frequency divider comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider, a second frequency divider and a third frequency divider; the input end of the third frequency divider is connected with the reference crystal oscillator, and the output end of the third frequency divider is connected with the first input end of the first phase detector and is used for dividing the frequency of a reference clock signal provided by the reference crystal oscillator; the second input end of the first phase discriminator is connected with the output end of the first frequency divider, the output end of the first phase discriminator is connected with the input end of the first loop filter, and the first phase discriminator is used for discriminating a first phase discrimination frequency determined according to the reference clock signal after frequency division and a feedback signal of the first voltage-controlled oscillator after frequency division, and transmitting a phase discrimination result to the first loop filter; the output end of the first loop filter is connected with the input end of the first voltage-controlled oscillator and used for generating a first control signal according to the phase discrimination result and transmitting the first control signal to the first voltage-controlled oscillator; the feedback output end of the first voltage-controlled oscillator is connected with the input end of the first frequency divider, and the signal output end of the first voltage-controlled oscillator is connected with the input end of the second frequency divider and used for adjusting the frequency of a signal to be output, outputting a frequency signal and transmitting a feedback signal to the first frequency divider; the first frequency divider is used for dividing the frequency of a feedback signal of the first voltage-controlled oscillator; the output end of the second frequency divider is connected with the reference clock input end of the decimal frequency synthesizer circuit and used for dividing the frequency of the output signal of the first voltage-controlled oscillator, and the output signal of the integer frequency synthesizer circuit can better accord with the reference clock signal required by the decimal frequency synthesizer circuit through the frequency division of the reference clock signal provided by the reference crystal oscillator, so that the decimal frequency synthesizer can obtain the reference clock which accords with the requirement, and the frequency spectrum quality of the finally output signal is ensured.
In addition, the fractional frequency synthesizer circuit includes: the second phase discriminator, the second loop filter, the second voltage-controlled oscillator and the fourth frequency divider; the first input end of the second phase detector is connected with the circuit output end of the integer frequency synthesizer circuit, the second input end of the second phase detector is connected with the output end of the fourth frequency divider, the output end of the second phase detector is connected with the input end of the second loop filter, and the second phase detector is used for carrying out phase discrimination on the phase discrimination frequency determined according to a reference clock signal provided by the integer frequency synthesizer circuit and a feedback signal of the second voltage-controlled oscillator after frequency division and transmitting a phase discrimination result to the second loop filter; the output end of the second loop filter is connected with the input end of a second voltage-controlled oscillator and used for generating a second control signal according to the phase discrimination result and transmitting the second control signal to the second voltage-controlled oscillator; the feedback output end of the second voltage-controlled oscillator is connected with the input end of the fourth frequency divider and is used for adjusting the frequency of a signal to be output, outputting a frequency signal and transmitting a feedback signal to the fourth frequency divider; the fourth frequency divider is used for dividing the frequency of the feedback signal of the second voltage-controlled oscillator, and the feedback control adjustment is carried out according to the phase discrimination result of the phase discriminator, so that the fractional stray of the output signal can be effectively avoided.
In addition, the fractional frequency synthesizer circuit includes: the second phase discriminator, the second loop filter, the second voltage-controlled oscillator, the fourth frequency divider, the fifth frequency divider and the sixth frequency divider; the input end of the fifth frequency divider is connected with the circuit output end of the integer frequency synthesizer circuit, and the output end of the fifth frequency divider is connected with the first input end of the second phase discriminator and is used for dividing the frequency of the reference clock signal provided by the integer frequency synthesizer circuit; the first input end of the second phase discriminator is connected with the output end of the fifth frequency divider, the second input end of the second phase discriminator is connected with the output end of the fourth frequency divider, the output end of the second phase discriminator is connected with the input end of the second loop filter, and the second phase discriminator is used for discriminating the phase discrimination frequency determined according to the reference clock signal provided by the integer frequency synthesizer circuit after frequency division and the feedback signal of the second voltage-controlled oscillator after frequency division, and transmitting the phase discrimination result to the second loop filter; the output end of the second loop filter is connected with the input end of a second voltage-controlled oscillator and used for generating a second control signal according to the phase discrimination result and transmitting the second control signal to the second voltage-controlled oscillator; the feedback output end of the second voltage-controlled oscillator is connected with the input end of the sixth frequency divider and is used for adjusting the frequency of a signal to be output, outputting a frequency signal and transmitting a feedback signal to the sixth frequency divider; the output end of the sixth frequency divider is connected with the input end of the fourth frequency divider and used for pre-dividing the feedback signal of the second voltage-controlled oscillator, outputting the pre-divided feedback signal of the second voltage-controlled oscillator to the fourth frequency divider for the fourth frequency divider to re-divide the pre-divided feedback signal of the second voltage-controlled oscillator, and pre-dividing the feedback signal to reduce the frequency dividing ratio and difficulty of the fourth frequency divider, thereby avoiding the problem of signal quality reduction caused by over-high frequency dividing ratio and ensuring the signal quality of the output signal.
Drawings
One or more embodiments are illustrated by the corresponding figures in the drawings, which are not meant to be limiting.
Fig. 1 is a schematic diagram of a frequency synthesizer according to the prior art;
fig. 2 is a schematic diagram of another frequency synthesizer according to the prior art;
fig. 3 is a schematic diagram of a frequency synthesizer according to a first embodiment of the present invention;
fig. 4 is a schematic diagram of a frequency synthesizer according to a second embodiment of the present invention;
fig. 5 is a flowchart of a frequency synthesis method according to a third embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to a fourth embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present invention, and the embodiments may be mutually incorporated and referred to without contradiction.
When the fractional spur avoidance is performed, the difference Δ f between the harmonic of the phase detection frequency closest to the output signal frequency and the output signal frequency is usually used as the quantization target of the fractional spur, and the fractional spur can be mostly suppressed at the position 20 to 30 times of the bandwidth BW of the loop filter of the fractional frequency synthesizer. In the structure shown in fig. 1, two outputs ref1 and ref2 are obtained by providing a same reference crystal oscillator for a first fractional frequency synthesizer and a second fractional frequency synthesizer, then the outputs of the two fractional frequency synthesizers are connected to a radio frequency switch, a reference clock signal input to a third fractional frequency synthesizer is selected according to the radio frequency switch, and a reference clock of the third fractional frequency synthesizer is adjusted, so that a phase discrimination frequency determined according to the reference clock is adjusted, and the phase discrimination frequency of the third fractional frequency synthesizer is adjustable.
In the structure shown in fig. 2, a reference crystal oscillator 1 and a reference crystal oscillator 2 generate different reference crystal oscillators through different power supplies by means of a frequency generator, then the reference crystal oscillators are input to a radio frequency switch, the reference crystal oscillators to be input to a frequency detector are selected through a crystal oscillator switching circuit, then phase discrimination frequencies are determined by a phase-locked loop circuit according to the reference crystal oscillators, synthesized signals of different frequencies are output according to the phase discrimination frequencies, and one of the reference crystal oscillators is selected as the reference crystal oscillator of the phase-locked loop circuit, so that switching of the phase discrimination frequencies of the phase-locked loop circuit is realized.
When the phase demodulation frequency of the third fractional frequency synthesizer is adjusted by combining a plurality of fractional frequency synthesizers and a radio frequency switch, the problems that more fractional frequency synthesizers are needed, the circuit structure and control are complex, and new fractional stray can be introduced exist; the radio frequency switch selects one of the reference crystal oscillators to provide a reference clock signal for the phase-locked loop circuit, and when the phase discrimination frequency is adjusted through the selected reference clock signal, the problems that a plurality of reference crystal oscillators are needed and a large circuit area is occupied exist.
A first embodiment of the present invention relates to a frequency synthesizer, and a schematic configuration diagram of the frequency synthesizer in this embodiment is shown in fig. 3, in which an output of an integer frequency synthesizer circuit is used as an input of a reference clock of a fractional frequency synthesizer circuit, and the output of the integer frequency synthesizer circuit is adjusted according to a frequency of an output signal of the fractional frequency synthesizer circuit, thereby flexibly adjusting a phase detection frequency of the fractional frequency synthesizer circuit.
The following describes the implementation details of the frequency synthesizer in the present embodiment, and the following is only provided for the convenience of understanding and is not necessary for implementing the present embodiment.
In the frequency synthesizer of the present embodiment, the reference crystal oscillator is connected to a reference clock input terminal of the integer frequency synthesizer circuit, and the reference crystal oscillator is used as an input of the integer frequency synthesizer circuit to provide a reference clock signal for the integer frequency synthesizer circuit, so that the integer frequency synthesizer can generate an output signal according to the reference crystal oscillator; the output end of the integer frequency synthesizer circuit is connected with the reference clock input end of the decimal frequency synthesizer circuit, the output of the integer frequency synthesizer circuit is used as a reference clock signal of the decimal frequency synthesizer circuit, so that the reference clock input of the decimal frequency synthesizer circuit can be flexibly changed according to the output of the integer frequency synthesizer circuit, the decimal frequency synthesizer circuit determines the phase discrimination frequency of the decimal frequency synthesizer circuit according to the reference clock signal provided by the integer frequency synthesizer circuit, and then generates a frequency signal with a decimal stray value larger than a preset threshold value according to the phase discrimination frequency. The output of the integer frequency synthesizer circuit is used as the reference clock input of the decimal frequency synthesizer circuit, so that the reference clock of the decimal frequency synthesizer circuit can be changed according to the output of the integer frequency synthesizer circuit, the phase discrimination frequency of the decimal frequency synthesizer circuit is flexibly switched, and good decimal spurious avoidance can be carried out when the decimal frequency synthesizer circuit outputs signals with different frequencies.
Further, the integer frequency synthesizer circuit includes: the phase detector comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider and a second frequency divider; the first input end of the first phase discriminator is connected with the reference crystal oscillator, the second input end of the first phase discriminator is connected with the output end of the first frequency divider, the output end of the first phase discriminator is connected with the input end of the first loop filter, and the first phase discriminator is used for discriminating a first phase discrimination frequency determined according to the reference crystal oscillator and a feedback signal of the first voltage-controlled oscillator after frequency division and transmitting a phase discrimination result to the first loop filter; the output end of the first loop filter is connected with the input end of the first voltage-controlled oscillator and used for generating a first control signal according to the phase discrimination result and transmitting the first control signal to the first voltage-controlled oscillator; the feedback output end of the first voltage-controlled oscillator is connected with the input end of the first frequency divider, and the signal output end of the first voltage-controlled oscillator is connected with the input end of the second frequency divider, and is used for adjusting the frequency of the output signal and transmitting the feedback signal to the first frequency divider; the first frequency divider is used for dividing the frequency of a feedback signal of the first voltage-controlled oscillator; the output end of the second frequency divider is connected with the reference clock input end of the decimal frequency synthesizer circuit and used for dividing the frequency of the output signal of the first voltage-controlled oscillator. Signals output by the integer frequency synthesizer circuit are divided by adjusting the frequency division coefficient of the second frequency divider which is adjusted in a programmable mode to obtain Fout1, and the output signals Fout1 after frequency division are transmitted to the reference clock signal input end of the fractional frequency synthesizer circuit, so that the fractional frequency synthesizer circuit can have good fractional spurious avoidance effects on output signals of various frequencies when synthesizing and outputting signals according to the phase discrimination frequency corresponding to the obtained reference clock signal.
Further, the integer frequency synthesizer circuit further comprises: a third frequency divider; the input end of the third frequency divider is connected with the reference crystal oscillator, the output end of the third frequency divider is connected with the second input end of the first phase detector and is used for dividing the frequency of the reference crystal oscillator obtained by the integer frequency synthesizer circuit, the frequency of the output signal of the integer frequency synthesizer circuit is more consistent with the requirement of the decimal frequency synthesizer circuit on the frequency of the reference clock signal through frequency division of the reference crystal oscillator, the decimal frequency synthesizer is used for obtaining the reference clock meeting the requirement, and therefore the quality of the finally output signal is guaranteed.
Further, the fractional frequency synthesizer circuit includes: the second phase discriminator, the second loop filter, the second voltage-controlled oscillator and the fourth frequency divider; the first input end of the second phase discriminator is connected with the circuit output end of the integer frequency synthesizer circuit, the second input end of the second phase discriminator is connected with the output end of the fourth frequency divider, the output end of the second phase discriminator is connected with the input end of the second loop filter, and the second phase discriminator is used for carrying out phase discrimination on the phase discrimination frequency determined according to the reference clock signal provided by the integer frequency synthesizer circuit and the feedback signal of the second voltage-controlled oscillator after frequency division and transmitting the phase discrimination result to the second loop filter; the output end of the second loop filter is connected with the input end of a second voltage-controlled oscillator and used for generating a second control signal according to the phase discrimination result and transmitting the second control signal to the second voltage-controlled oscillator; the feedback output end of the second voltage-controlled oscillator is connected with the input end of the fourth frequency divider and is used for adjusting the frequency of a signal to be output, outputting a frequency signal and transmitting a feedback signal to the fourth frequency divider; the fourth frequency divider is used for dividing the frequency of the feedback signal of the second voltage-controlled oscillator, and the output signal of the fourth frequency divider enters the second phase discriminator to be compared with the reference signal in a phase discrimination way; the second loop filter generates a control signal according to the feedback signal determined by the second phase discriminator and the phase discrimination result of the phase discrimination frequency to adjust the frequency of the output signal of the second voltage-controlled oscillator, so that fractional stray of the output signal can be effectively avoided when signals of various frequencies are output; fractional frequency synthesizer circuits are based on sigma-delta modulation techniques.
Further, the fractional frequency synthesizer circuit further comprises: a fifth frequency divider; the input end of the fifth frequency divider is connected with the circuit output end of the integer frequency synthesizer circuit, and the output end of the fifth frequency divider is connected with the first input end of the second phase discriminator and is used for dividing the frequency of the reference clock signal provided by the integer frequency synthesizer circuit; the first input end of the second phase discriminator is connected with the circuit output end of the integer frequency synthesizer circuit through the fifth frequency divider, and the acquired reference clock signal is divided by the fifth frequency divider, so that the determined phase discrimination frequency is ensured to meet the requirement of the decimal frequency synthesizer circuit, and the good avoidance of decimal spurious is realized.
In one example, when the frequency synthesizer synthesizes and outputs signals, firstly, configuration data of a first voltage-controlled oscillator of the integer frequency synthesizer circuit and a frequency division coefficient of a second frequency divider are adjusted through software to obtain Fout1 with different frequencies which can be output by the integer frequency synthesizer circuit, a reference clock signal alternative library of the fractional frequency synthesizer circuit is formed according to possible outputs of the integer frequency synthesizer circuit, then, a fractional spur avoidance requirement is determined according to a loop bandwidth of the fractional frequency synthesizer circuit, when the signals are synthesized and output, a phase discrimination frequency which can meet the fractional spur avoidance requirement when the fractional frequency synthesizer circuit outputs each frequency signal is calculated through a configuration algorithm, then, a reference clock signal required by the fractional frequency synthesizer circuit is determined according to the determined phase discrimination frequency, configuration data of the integer frequency synthesizer circuit is adjusted according to the determined reference clock signal, the integer frequency synthesizer circuit is made to output a frequency signal satisfying the requirement. Here, in order to achieve a better fractional spur cancellation effect, the avoidance principle may be set to Δ f < n · BW, so that the fractional spur falls outside n times of the loop bandwidth and is filtered by the loop filter, and the value range of n may be set to 30 to 120 in consideration of design and circuit cost.
For example, the frequency range of the output signal of the fractional frequency synthesizer circuit is between 3-9GHz, the loop bandwidth of the output signal is 50kHz, the basic phase discrimination frequency is 50MHz, n is selected to be equal to 100 according to the evasion principle of fractional spur, namely, the fractional spur falls at the loop bandwidth of 100 times, at this time, evasion measures need to be taken for setting the phase discrimination frequency harmonic and the output frequency difference delta f to be less than 5MHz, namely, the phase discrimination frequency needs to be reselected when the fractional spur delta f is less than 5MHz, all possible outputs of the integer frequency synthesizer circuit are obtained through software calculation, a reference clock signal alternative library is obtained, and the 50MHz output signal is selected as the basic output signal according to the basic phase discrimination frequency of the fractional frequency synthesizer circuit. When the decimal frequency synthesizer circuit carries out signal synthesis and output, the configuration data of a second frequency divider and a first voltage-controlled oscillator of the integer frequency synthesizer are set according to the basic output signal, and an output signal of 50MHz is output. At a certain moment, the decimal frequency synthesizer circuit outputs 4500.03MHz signals, the phase discrimination frequency acquired according to the reference clock signal is the basic phase discrimination frequency of 50MHz, the 90 th harmonic of the phase discrimination frequency is closest to the output frequency through software calculation, and Δ f at the moment is 30kHz and less than 50kHz, namely, the decimal spurious appears in the loop bandwidth of 50kHz, the avoidance requirement of the decimal spurious can not be met, at the moment, the frequency is greater than the current signal frequency by inquiring the data in the reference clock signal alternative library, the alternative signal closest to the current signal frequency is used as the signal to be output, the signal closest to 50MHz is 51.28205MHz by inquiring the data in the reference clock alternative library, the signal with the frequency of 51.28205MHz is used as the signal to be output, the configuration data of the second frequency divider and the first voltage-controlled oscillator are adjusted according to the frequency of the signal to be output, make integer frequency synthesizer circuit's output signal be 51.28205MHz, at this moment, decimal frequency synthesizer circuit's phase discrimination frequency change is 51.28205MHz, and at this moment, the 88 th harmonic of phase discrimination frequency is closest to output signal's frequency, calculates to obtain Δ f 12.7904MHz, is far more than 50kHz, can realize good decimal spurious evasion, consequently, maintains the configuration data of current second frequency divider and first voltage controlled oscillator unchangeable, supplies decimal frequency synthesizer circuit to carry out the synthesis and the output of frequency signal.
Therefore, the embodiment provides a frequency synthesizer, which can provide a proper reference clock signal for a fractional frequency synthesizer circuit by means of an integer frequency synthesizer circuit, so that the fractional frequency synthesizer circuit can obtain a corresponding phase discrimination frequency according to the output change of the integer frequency synthesizer circuit, and can realize good fractional spurious avoidance when the fractional frequency synthesizer outputs signals with different frequencies; the reference clock of the decimal frequency synthesizer circuit is provided through the integer frequency synthesizer circuit, a plurality of reference clock signal generating circuits are avoided being required to be arranged, the structure of the circuit is simplified, the circuit complexity and the control difficulty are reduced, the circuit area and the cost are saved, the problem that a new decimal is stray can be introduced when a plurality of decimal frequency synthesizer circuits are combined is avoided, the effect of stray evasion of decimal is guaranteed, and the quality of output signals is improved.
A second embodiment of the present invention relates to a frequency synthesizer, which is substantially the same as the first embodiment, and in this embodiment, a sixth frequency divider that prescales a feedback signal of a fractional frequency synthesizer is added to a feedback signal of the fractional frequency synthesizer in a fractional frequency synthesizer circuit, so that by prescaling the feedback signal, a frequency division requirement and difficulty for the fourth frequency divider are reduced, a phase discrimination result is prevented from being affected due to signal quality degradation caused by an excessively high frequency division ratio, and quality of an output signal is further ensured.
Fig. 4 shows a schematic structural diagram of this embodiment, except for the sixth frequency divider, other modules in this embodiment are similar to those in the first embodiment, and in order to avoid repetition, description is not repeated here, and only the sixth frequency divider is described.
In this embodiment, the fractional frequency synthesizer circuit further includes: a sixth frequency divider; the input end of the sixth frequency divider is connected with the feedback output end of the second voltage-controlled oscillator, the output end of the sixth frequency divider is connected with the input end of the fourth frequency divider, the sixth frequency divider is used for pre-dividing the feedback signal of the second voltage-controlled oscillator, and the feedback signal is pre-divided, so that the frequency dividing ratio of the fourth frequency divider is reduced, the problem of signal quality reduction caused by overhigh frequency dividing ratio is avoided, and the signal quality of the output signal is ensured.
In one example, a sixth frequency divider is added in the fractional frequency synthesizer circuit, since the phase detector compares the difference between a certain harmonic of the phase detection frequency and the frequency of the signal received by the fourth frequency divider, the fractional spur at this time is Δ f/p, where p is the frequency division coefficient of the sixth frequency divider, for example, the fractional frequency synthesizer needs to output a 3-9GHz signal, the basic phase detection frequency of the fractional frequency synthesizer is 50MHz, the loop bandwidth is 50kHz, the frequency division coefficient of the sixth frequency detector is 2, at a certain time, the frequency of the output signal is 4500.03MHz, the 90 th harmonic of the phase detection frequency and the frequency of the signal fed back to the fourth frequency divider are the closest, at this time, the feedback signal to be output to the phase detector should be the signal whose output frequency is divided by the sixth frequency divider and the fourth frequency divider, since the frequency division coefficient of the sixth frequency divider is 2, the feedback signal is divided, therefore, the frequency division coefficient of the fourth frequency divider is set to 45.0003, at the moment, the difference value delta f between the 90 th harmonic of the phase discrimination frequency and the output frequency of the sixth frequency divider is 30kHZ, the corresponding fractional stray is delta f/p, namely 15kHz, the current fractional stray evasion effect is detected according to the fractional stray evasion requirement, the parameter of the fractional frequency synthesizer circuit is adjusted according to the detection result, the integer frequency synthesizer circuit outputs proper frequency, the modification of the phase discrimination frequency of the fractional frequency synthesizer circuit is realized, and the requirement is met until the fractional stray evasion effect.
From this, this embodiment provides a frequency synthesizer, through in the feedback signal transmission channel at decimal frequency synthesizer circuit, add a sixth frequency divider before the fourth frequency divider, become secondary frequency division with feedback signal's frequency division process, the frequency division ratio of fourth frequency divider has been reduced, avoided because the too big signal quality that leads to of frequency division ratio descends, the quality of the signal that the phase discriminator received has been guaranteed, and then the accuracy of phase discrimination result has been guaranteed, thereby avoid influencing the stray effect of avoidng of decimal because the phase discrimination result is inaccurate, guarantee output signal's quality.
A third embodiment of the present invention relates to a frequency synthesis method, and specifically, a flow chart is shown in fig. 5, and is applied to the frequency synthesizer of any one of the above embodiments, where the frequency synthesis method includes:
Specifically, before the frequency signals are synthesized and output, the output signal of the integer frequency synthesizer circuit is acquired, and the acquired output signal of the integer frequency synthesizer circuit is input to the fractional frequency synthesizer circuit as the reference clock signal of the fractional frequency synthesizer circuit.
Specifically, after an obtained output signal of the integer frequency synthesizer circuit is used as a reference clock signal of the fractional frequency synthesizer circuit, a phase detection frequency of the fractional frequency synthesizer circuit is determined according to the reference clock signal of the fractional frequency synthesizer circuit, a difference value between a harmonic closest to the output frequency and the output frequency in a phase detection frequency harmonic is calculated according to the determined phase detection frequency and the frequency of a frequency signal to be output, a fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is determined, whether the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than a preset threshold value or not is detected, if the fractional spurious value is greater than the preset threshold value, the step 104 is performed, and if the fractional spurious value is not greater than the preset threshold value, the step 103 is performed.
In practical application, the preset threshold of the fractional stray value can be set according to the actual situation of the fractional stray avoidance requirement, and the specific value of the preset threshold is not limited in the embodiment.
Specifically, when it is detected that signal synthesis and output are performed according to a phase detection frequency corresponding to a current reference clock signal and a fractional spur value is not greater than a preset threshold, it is determined that the phase detection frequency corresponding to the current reference clock signal cannot achieve good fractional spur avoidance in a process of performing signal synthesis and output of the current frequency, and the reference clock signal needs to be adjusted, that is, the output signal of the integer frequency synthesizer circuit is adjusted, and then the step 102 is returned again, and it is detected again whether the fractional spur value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold until the fractional spur value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold.
In one example, when synthesizing and outputting frequency signals, a reference clock signal alternative library 1 is generated according to all alternative frequencies of the acquired output signals of the integer frequency synthesizer circuit, then according to the basic phase discrimination frequency of the decimal frequency synthesizer circuit, the basic output signals of the integer frequency synthesizer circuit are selected from the reference clock signal alternative library 1, then according to the frequency range of the output signals of the decimal frequency synthesizer circuit, through software calculation, the phase discrimination frequency required when the decimal frequency synthesizer circuit outputs different frequency signals is traversed, the output signal frequency range which can be suitable for the current phase discrimination frequency is detected by taking the current phase discrimination frequency as the basis, when the current phase discrimination frequency is detected not to meet the requirement of decimal spurious evasion, the target frequency which is closest to the current output signal frequency is selected from the reference clock alternative library 1, and adjusting configuration data of the integer frequency synthesizer circuit according to the target frequency, so that the integer frequency synthesizer circuit outputs an output signal of the target frequency, and then detecting an output signal range which can be used according to the phase discrimination frequency corresponding to the new reference clock signal until all output signals of the decimal frequency synthesizer circuit are traversed. And generating a reference clock signal alternative library 2 according to the reference clock signal selected in the traversal calculation process, directly selecting a target frequency with the frequency closest to the current phase discrimination frequency from the reference clock signal alternative library 2 when the output of the integer frequency synthesizer circuit is adjusted, and adjusting the configuration data of the integer frequency synthesizer circuit according to the selected target frequency so that the integer frequency synthesizer circuit can output an output signal of the target frequency.
In practical applications, the target frequency may be a frequency value closest to the current signal frequency, among frequencies greater than the current signal frequency or less than the current signal frequency, and the embodiment is not limited to a specific selection rule.
For example, the fractional frequency synthesizer needs to output 3-9GHz signals, the basic phase discrimination frequency of the fractional frequency synthesizer is 50MHz, the loop bandwidth is 50kHz, and the frequencies of the output signals of the integer frequency synthesizer circuit, including the frequencies of the output signals of the integer frequency synthesizer circuit, include: the method comprises the following steps of generating a reference clock alternative library 1 according to a plurality of possible output signals of an integer frequency synthesizer circuit by 50MHz, 55.55555MHz, 54.05405MHz, 52.63157MHz, 51.28205MHz, 48.78048MHz, 47.61904MHz, 46.51162MHz, 45.45454MHz, 55.88235MHz, 54.28571MHz, 52.77777MHz, 51.35135MHz, 48.71794MHz, 47.5MHz, 46.34146MHz, 45.23809MHz and the like, and determining the required phase discrimination frequency when 3-9GHz signal output is performed through software traversal calculation, wherein the required phase discrimination frequency comprises the following steps: 50MHz, 51.28205MHz, 51.35135MHz, 52.63157MHz and 52.77777MHz, according to the reference clock signals corresponding to the 5 phase detection frequencies, a reference clock alternative library 2 is generated, at a certain moment, the decimal frequency synthesizer circuit outputs 4500.03MHz signals, the adopted phase detection frequency is 50MHz, the 90 th harmonic of the phase detection frequency is closest to the frequency of the output signal, the difference value delta f between the two is 30kHz, namely, the decimal stray value is 30kHz at the moment, the requirement of decimal stray evasion is not met, at the moment, and selecting 51.28205MHz reference clock which is closest to the current phase detection frequency from the signals with the frequency higher than the current phase detection frequency from the reference clock alternative library 2 as the signals to be output, and adjusts the configuration data of the integer frequency synthesizer circuit according to the selected signal to output a signal with a frequency of 51.28205MHz, then, returning to step 102, it is checked again whether the fractional spur value of the frequency signal generated by the fractional frequency synthesizer circuit is larger than a preset threshold.
And 104, outputting a frequency signal.
Specifically, when the fractional spur value of the output frequency signal of the fractional frequency synthesizer circuit is detected to be greater than the preset threshold value, the phase discrimination frequency corresponding to the current reference clock can be directly judged to be capable of realizing good fractional spur avoidance in the process of synthesizing and outputting the signal of the current frequency, so that the frequency signal is directly output according to the current reference clock signal.
Therefore, the present embodiment provides a frequency synthesis method, in which the output of the integer frequency synthesizer circuit is used as the input of the reference clock signal of the fractional frequency synthesizer circuit, so that the reference clock of the fractional frequency synthesizer can be flexibly changed according to the output of the integer frequency synthesizer, thereby realizing flexible change of the phase discrimination frequency; the selection of a reference clock signal and the adjustment of an integer frequency synthesizer circuit are carried out through a pre-established reference clock alternative library, so that the phase discrimination frequency adjustment efficiency is improved; the adjustment of the output signal of the integer frequency synthesizer circuit is carried out through the relation between the calculation result of the fractional stray value and the preset threshold value, so that the phase discrimination frequency of the fractional frequency synthesizer circuit can be changed according to different frequency output signals, good fractional stray avoidance can be carried out when different frequency signals are output, and the quality of the output signals is guaranteed.
The steps of the above methods are divided for clarity, and the implementation may be combined into one step or split some steps, and the steps are divided into multiple steps, so long as the same logical relationship is included, which are all within the protection scope of the present patent; it is within the scope of the patent to add insignificant modifications to the algorithms or processes or to introduce insignificant design changes to the core design without changing the algorithms or processes.
A fourth embodiment of the invention relates to an electronic device, as shown in fig. 6, comprising at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the frequency synthesis method.
Where the memory and processor are connected by a bus, the bus may comprise any number of interconnected buses and bridges, the buses connecting together one or more of the various circuits of the processor and the memory. The bus may also connect various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor is transmitted over a wireless medium via an antenna, which further receives the data and transmits the data to the processor.
The processor is responsible for managing the bus and general processing and may also provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. And the memory may be used to store data used by the processor in performing operations.
A fifth embodiment of the present invention relates to a computer-readable storage medium storing a computer program. The computer program realizes the above-described method embodiments when executed by a processor.
That is, as can be understood by those skilled in the art, all or part of the steps in the method for implementing the embodiments described above may be implemented by a program instructing related hardware, where the program is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a processor (processor) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (10)
1. A frequency synthesizer, comprising: a reference crystal oscillator, an integer frequency synthesizer circuit and a fractional frequency synthesizer circuit;
the reference crystal oscillator is connected with a reference clock input end of the integer frequency synthesizer circuit and used for providing a reference clock signal for the integer frequency synthesizer circuit;
the output end of the integer frequency synthesizer circuit is connected with the reference clock input end of the decimal frequency synthesizer circuit and is used for providing a reference clock signal for the decimal frequency synthesizer circuit so that the decimal frequency synthesizer circuit can obtain phase discrimination frequency according to the reference clock signal;
and the decimal frequency synthesizer circuit is used for generating a frequency signal with a decimal spurious value larger than a preset threshold value according to the phase discrimination frequency.
2. The frequency synthesizer of claim 1, wherein the integer frequency synthesizer circuit comprises: the phase detector comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider and a second frequency divider;
a first input end of the first phase discriminator is connected to the reference crystal oscillator, a second input end of the first phase discriminator is connected to an output end of the first frequency divider, an output end of the first phase discriminator is connected to an input end of the first loop filter, and the first phase discriminator is used for discriminating a first phase discrimination frequency determined according to a reference clock signal provided by the reference crystal oscillator and a feedback signal of the first voltage-controlled oscillator after frequency division, and transmitting a phase discrimination result to the first loop filter;
the output end of the first loop filter is connected with the input end of the first voltage-controlled oscillator and used for generating a first control signal according to the phase discrimination result and transmitting the first control signal to the first voltage-controlled oscillator;
the feedback output end of the first voltage-controlled oscillator is connected with the input end of the first frequency divider, and the signal output end of the first voltage-controlled oscillator is connected with the input end of the second frequency divider, and is used for adjusting the frequency of a signal to be output, outputting a frequency signal and transmitting a feedback signal to the first frequency divider;
the first frequency divider is used for dividing the frequency of the feedback signal of the first voltage-controlled oscillator;
the output end of the second frequency divider is connected with the reference clock input end of the decimal frequency synthesizer circuit and is used for dividing the frequency of the output signal of the first voltage-controlled oscillator.
3. The frequency synthesizer of claim 1, wherein the integer frequency synthesizer circuit comprises: the frequency divider comprises a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider, a second frequency divider and a third frequency divider;
the input end of the third frequency divider is connected with the reference crystal oscillator, and the output end of the third frequency divider is connected with the first input end of the first phase detector and is used for dividing the frequency of a reference clock signal provided by the reference crystal oscillator;
the second input end of the first phase discriminator is connected with the output end of the first frequency divider, and the output end of the first phase discriminator is connected with the input end of the first loop filter, and the first phase discriminator is used for discriminating a first phase discrimination frequency determined according to the frequency-divided reference clock signal and a feedback signal of the first voltage-controlled oscillator after frequency division, and transmitting a phase discrimination result to the first loop filter;
the output end of the first loop filter is connected with the input end of the first voltage-controlled oscillator and used for generating a first control signal according to the phase discrimination result and transmitting the first control signal to the first voltage-controlled oscillator;
the feedback output end of the first voltage-controlled oscillator is connected with the input end of the first frequency divider, and the signal output end of the first voltage-controlled oscillator is connected with the input end of the second frequency divider, and is used for adjusting the frequency of a signal to be output, outputting a frequency signal and transmitting a feedback signal to the first frequency divider;
the first frequency divider is used for dividing the frequency of the feedback signal of the first voltage-controlled oscillator;
the output end of the second frequency divider is connected with the reference clock input end of the decimal frequency synthesizer circuit and is used for dividing the frequency of the output signal of the first voltage-controlled oscillator.
4. The frequency synthesizer of claim 1, wherein the fractional frequency synthesizer circuit comprises: the second phase discriminator, the second loop filter, the second voltage-controlled oscillator and the fourth frequency divider;
a first input end of the second phase detector is connected to a circuit output end of the integer frequency synthesizer circuit, a second input end of the second phase detector is connected to an output end of the fourth frequency divider, an output end of the second phase detector is connected to an input end of the second loop filter, and the second phase detector is used for performing phase detection on a phase detection frequency determined according to a reference clock signal provided by the integer frequency synthesizer circuit and a feedback signal of the second voltage-controlled oscillator after frequency division, and transmitting a phase detection result to the second loop filter;
the output end of the second loop filter is connected with the input end of the second voltage-controlled oscillator and used for generating a second control signal according to the phase discrimination result and transmitting the second control signal to the second voltage-controlled oscillator;
the feedback output end of the second voltage-controlled oscillator is connected with the input end of the fourth frequency divider and is used for adjusting the frequency of a signal to be output, outputting a frequency signal and transmitting a feedback signal to the fourth frequency divider;
the fourth frequency divider is used for dividing the frequency of the feedback signal of the second voltage-controlled oscillator.
5. The frequency synthesizer of claim 1, wherein the fractional frequency synthesizer circuit comprises: the second phase discriminator, the second loop filter, the second voltage-controlled oscillator, the fourth frequency divider and the fifth frequency divider;
the input end of the fifth frequency divider is connected with the circuit output end of the integer frequency synthesizer circuit, and the output end of the fifth frequency divider is connected with the first input end of the second phase discriminator and is used for dividing the frequency of the reference clock signal provided by the integer frequency synthesizer circuit;
a second input end of the second phase detector is connected with an output end of the fourth frequency divider, an output end of the second phase detector is connected with an input end of the second loop filter, and the second phase detector is used for performing phase detection on a phase detection frequency determined according to a reference clock signal provided by the integer frequency synthesizer circuit after frequency division and a feedback signal of the second voltage-controlled oscillator after frequency division, and transmitting a phase detection result to the second loop filter;
the output end of the second loop filter is connected with the input end of the second voltage-controlled oscillator and used for generating a second control signal according to the phase discrimination result and transmitting the second control signal to the second voltage-controlled oscillator;
the feedback output end of the second voltage-controlled oscillator is connected with the input end of the fourth frequency divider and is used for adjusting the frequency of a signal to be output, outputting a frequency signal and transmitting a feedback signal to the fourth frequency divider;
the fourth frequency divider is used for dividing the frequency of the feedback signal of the second voltage-controlled oscillator.
6. The frequency synthesizer of claim 1, wherein the fractional frequency synthesizer circuit comprises: the second phase discriminator, the second loop filter, the second voltage-controlled oscillator, the fourth frequency divider, the fifth frequency divider and the sixth frequency divider;
the input end of the fifth frequency divider is connected with the circuit output end of the integer frequency synthesizer circuit, and the output end of the fifth frequency divider is connected with the first input end of the second phase discriminator and is used for dividing the frequency of the reference clock signal provided by the integer frequency synthesizer circuit;
a first input end of the second phase detector is connected with an output end of the fifth frequency divider, a second input end of the second phase detector is connected with an output end of the fourth frequency divider, an output end of the second phase detector is connected with an input end of the second loop filter, and the second phase detector is used for carrying out phase discrimination on a phase discrimination frequency determined according to a reference clock signal provided by the frequency-divided integer frequency synthesizer circuit and a feedback signal of the second voltage-controlled oscillator after frequency division and transmitting a phase discrimination result to the second loop filter;
the output end of the second loop filter is connected with the input end of the second voltage-controlled oscillator and used for generating a second control signal according to the phase discrimination result and transmitting the second control signal to the second voltage-controlled oscillator;
the feedback output end of the second voltage-controlled oscillator is connected with the input end of the sixth frequency divider and is used for adjusting the frequency of a signal to be output, outputting a frequency signal and transmitting a feedback signal to the sixth frequency divider;
the output end of the sixth frequency divider is connected to the input end of the fourth frequency divider, and is configured to pre-divide the frequency of the feedback signal of the second voltage controlled oscillator, and output the pre-divided feedback signal of the second voltage controlled oscillator to the fourth frequency divider, so that the fourth frequency divider performs frequency re-division on the pre-divided feedback signal of the second voltage controlled oscillator.
7. A method for frequency synthesis, applied to a frequency synthesizer, the frequency synthesizer comprising: the frequency synthesizer comprises a reference crystal oscillator, an integer frequency synthesizer circuit and a decimal frequency synthesizer circuit, wherein the reference crystal oscillator is connected with a reference clock input end of the integer frequency synthesizer circuit, and an output end of the integer frequency synthesizer circuit is connected with a reference clock input end of the decimal frequency synthesizer circuit; the frequency synthesis method comprises the following steps:
acquiring an output signal of the integer frequency synthesizer circuit, and inputting the output signal into the fractional frequency synthesizer circuit as a reference clock signal of the fractional frequency synthesizer circuit;
detecting whether a fractional spurious value of a frequency signal generated by the fractional frequency synthesizer circuit is greater than a preset threshold value;
if the frequency is not greater than the preset threshold, adjusting the output signal of the integer frequency synthesizer circuit, and detecting whether the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold again until the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold.
8. The method of frequency synthesis of claim 7, wherein said adjusting the output signal of the integer frequency synthesizer circuit comprises:
acquiring all alternative frequencies of the output signal of the integer frequency synthesis circuit;
determining a target frequency closest to the current output signal frequency according to the alternative frequency;
and adjusting configuration data of the integer frequency synthesizer circuit according to the target frequency, so that the integer frequency synthesizer circuit outputs an output signal of the target frequency.
9. An electronic device, comprising:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the frequency synthesis method of claim 7 or 8.
10. A computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the frequency synthesizing method of claim 7 or 8.
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| PCT/CN2020/122943 WO2021120836A1 (en) | 2019-12-20 | 2020-10-22 | Frequency synthesizer, frequency synthesis method, electronic device and storage medium |
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| CN104320137B (en) * | 2014-10-22 | 2015-10-21 | 华中科技大学 | A kind of phase-locked loop frequency synthesizer |
| CN105049039B (en) * | 2015-07-08 | 2017-12-01 | 中国电子科技集团公司第四十一研究所 | A kind of fractional frequency division circuit for spurious reduction |
| CN206595986U (en) * | 2017-01-11 | 2017-10-27 | 扬州通信设备有限公司 | A kind of frequency synthesizer module |
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