KR101865323B1 - Frequency synthesizing method for identification friend or foe - Google Patents

Frequency synthesizing method for identification friend or foe Download PDF

Info

Publication number
KR101865323B1
KR101865323B1 KR1020180040485A KR20180040485A KR101865323B1 KR 101865323 B1 KR101865323 B1 KR 101865323B1 KR 1020180040485 A KR1020180040485 A KR 1020180040485A KR 20180040485 A KR20180040485 A KR 20180040485A KR 101865323 B1 KR101865323 B1 KR 101865323B1
Authority
KR
South Korea
Prior art keywords
frequency signal
frequency
fixed
signal
fixed frequency
Prior art date
Application number
KR1020180040485A
Other languages
Korean (ko)
Inventor
김태영
최성욱
박종혁
Original Assignee
한화시스템 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 한화시스템 주식회사 filed Critical 한화시스템 주식회사
Priority to KR1020180040485A priority Critical patent/KR101865323B1/en
Application granted granted Critical
Publication of KR101865323B1 publication Critical patent/KR101865323B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer and a frequency synthesis method for a peer identifier, and more particularly, to a frequency synthesizer and a frequency synthesis method for a peer identifier for oscillating a local oscillation signal used for radio communication of a peer identifier.
A frequency synthesizer for a peer identifier according to an embodiment of the present invention includes a first voltage controlled oscillator for outputting a variable frequency signal from a reference frequency signal; A fixed frequency signal generator for generating a plurality of fixed frequency signals from the reference frequency signal; A feedback unit for generating a comparison frequency signal by sequentially mixing the plurality of fixed frequency signals with the variable frequency signal; And a first phase locked loop unit for dividing the comparison frequency signal at a predetermined ratio and comparing the divided comparison frequency signal with the reference frequency signal to fix the phase of the variable frequency signal.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a frequency synthesizing method,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer and a frequency synthesis method for a peer identifier, and more particularly, to a frequency synthesizer and a frequency synthesis method for a peer identifier for oscillating a local oscillation signal used for radio communication of a peer identifier.

Identification Friend or Foe (IFF) is a device mainly used for military purposes. It is mainly used to identify peers of a target, especially to identify a friend. For example, assuming that the target is approaching the surveillance area, if the target is aliased or not, then the next step can be dealt with only if the identification of the pie is prioritized.

To this end, the peer identifier (IFF) sends a request signal for identifying the peer that is approaching the target, that is, the target of interest. Then, the target of interest returns a response signal in response to the request signal of the peer identifier. From this, the peer identifier IFF identifies the peer for the target of interest by receiving and analyzing the response signal returned from the target of interest.

As described above, the radio communication is performed for identifying the peer. The frequency used for radio communication for identifying the peer must have a low phase noise, and the necessity of receiving less influence from temperature and noise interference is better than that of other communication systems Higher.

KR 10-0727307 B1

The present invention provides a frequency synthesizer and a frequency synthesis method of a peer identifier capable of minimizing phase noise generated in a process of fixing a phase of a local oscillation signal.

A frequency synthesizer for a peer identifier according to an embodiment of the present invention includes a first voltage controlled oscillator for outputting a variable frequency signal from a reference frequency signal; A fixed frequency signal generator for generating a plurality of fixed frequency signals from the reference frequency signal; A feedback unit for generating a comparison frequency signal by sequentially mixing the plurality of fixed frequency signals with the variable frequency signal; And a first phase locked loop unit for dividing the comparison frequency signal at a predetermined ratio and comparing the divided comparison frequency signal with the reference frequency signal to fix the phase of the variable frequency signal.

The feedback unit may generate the comparison frequency signal by stepwise down-converting the frequency of the variable frequency signal.

The fixed frequency signal generator includes: a second voltage controlled oscillator for outputting an initial fixed frequency signal from the reference frequency signal; A second phase locked loop unit for dividing the initial fixed frequency signal by a predetermined ratio and comparing the divided initial fixed frequency signal with the reference frequency signal to fix the phase of the initial fixed frequency signal; A first filter unit for extracting a first fixed frequency signal from the initial fixed frequency signal; And a second filter unit for extracting a second fixed frequency signal having a frequency component different from the first fixed frequency signal from the initial fixed frequency signal.

The first fixed frequency signal may have a frequency component that is an integral multiple of the frequency of the second fixed frequency signal.

The first fixed frequency signal may include a harmonic frequency signal of the initial fixed frequency signal, and the second fixed frequency signal may include a source frequency signal of the initial fixed frequency signal.

Wherein the feedback unit comprises: a first mixer for mixing the first fixed frequency signal with the variable frequency signal; And a second mixer for mixing the second fixed frequency signal with a variable frequency signal in which the first fixed frequency signal is mixed.

Also, a method of synthesizing a frequency of a peer identifier according to an embodiment of the present invention includes: a step of outputting a variable frequency signal from a reference frequency signal; Generating a plurality of fixed frequency signals from the reference frequency signal; Generating a comparison frequency signal by sequentially mixing the plurality of fixed frequency signals with the variable frequency signal; And a step of dividing the comparison frequency signal at a predetermined ratio and comparing the divided comparison frequency signal with the reference frequency signal to fix the phase of the variable frequency signal.

Generating the plurality of fixed frequency signals includes generating an initial fixed frequency signal from the reference frequency signal; Extracting a first fixed frequency signal from the initial fixed frequency signal; And extracting a second fixed frequency signal having a frequency component different from the first fixed frequency signal from the initial fixed frequency signal.

The step of extracting the first fixed frequency signal may include the steps of selectively passing only the frequency component of the harmonic frequency signal in the initial fixed frequency signal and extracting the second fixed frequency signal, It is possible to selectively pass only the frequency component of the signal.

The process of extracting the first fixed frequency signal and extracting the second fixed frequency signal may be simultaneously performed.

Wherein the step of generating the comparison frequency signal includes: a step of first down-converting the frequency of the variable frequency signal by a frequency of the first fixed frequency signal; And a step of secondarily down-converting the frequency of the first down-converted variable frequency signal by a frequency of the second fixed frequency signal.

In the process of fixing the phase of the variable frequency signal, the frequency of the comparison frequency signal may be divided by a ratio smaller than a value obtained by dividing the frequency of the variable frequency signal by the frequency of the reference frequency signal.

According to the frequency synthesizer and the frequency synthesizing method of the present invention, a plurality of fixed frequency signals are mixed with a variable frequency signal to generate a comparison frequency signal, and the generated comparison frequency signal is divided to generate a variable frequency signal The frequency division ratio can be reduced.

In addition, in the fixed frequency signal, the frequency of the variable frequency signal is primarily down-converted using a harmonic frequency signal that is classified as noise and is to be removed, and the frequency of the variable frequency signal is converted to a second- Not only the noise included in the fixed frequency signal can be reduced, but also the frequency division ratio of the phase fixing process of the fixed frequency signal can be reduced. Thus, the phase noise characteristic can be improved, have.

Therefore, the frequency synthesizer and the frequency synthesis method of the PIAN identifier according to the embodiment of the present invention have a structure favorable to the phase noise characteristic and the miniaturization, and thus have a structure suitable for the equipment of the induction weapon Seeker, UAV or radar .

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a frequency synthesizer through a general phase locked loop control.
2 is a view schematically showing a variable frequency signal generating circuit in a frequency synthesizing apparatus of a peer discriminator according to an embodiment of the present invention;
3 is a view schematically showing a fixed frequency signal generating circuit in a frequency synthesizing apparatus of a peer discriminator according to an embodiment of the present invention.
4 is a diagram schematically illustrating a frequency synthesis method of a peer identifier according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, Is provided to fully inform the user. Wherein like reference numerals refer to like elements throughout.

1 is a diagram illustrating a frequency synthesizer through a conventional phase locked loop control.

Referring to FIG. 1, a frequency synthesizer using a general phase locked loop control uses a frequency signal output from a voltage-controlled oscillator 30 directly as a comparison frequency signal, and a phase locked loop divides a comparison frequency signal at a predetermined ratio The phase of the output frequency signal output from the voltage-controlled oscillator 30 is fixed.

That is, the frequency synthesizer through the general phase locked loop control oscillates a reference frequency signal of a low frequency from the reference frequency signal source 10. The frequency divider 40 divides the output frequency signal output from the voltage-controlled oscillator 30 by the division ratio of N. The phase detector 20 compares the reference frequency signal with the output frequency signal divided by the dividing ratio of N By outputting a control signal to the voltage-controlled oscillator, the phase of the output frequency signal out is fixed, and an output frequency signal having a frequency N times the frequency of the reference frequency signal is oscillated.

However, in the case of the frequency synthesizer using the phase locked loop control as described above, phase noise calculated by 20 log N is obtained. In the case of outputting the local oscillation signal, phase noise increases as the frequency division ratio increases, . This problem is more serious than in the case of a peer identifier for performing peer identification by wireless communication. Hereinafter, according to an embodiment of the present invention, phase noise generated in fixing the phase of a local oscillation signal can be minimized The frequency synthesizer and the frequency synthesizing method of the peer identifier will be described.

FIG. 2 is a view schematically showing a variable frequency signal generating circuit in a frequency synthesizing apparatus of a peer identifier according to an embodiment of the present invention. FIG. 3 is a block diagram of a frequency synthesizing apparatus according to an embodiment of the present invention, Fig.

2 and 3, the frequency synthesizer of the present invention includes a first voltage controlled oscillator 130 for outputting a variable frequency signal from a reference frequency signal; A fixed frequency signal generator for generating a plurality of fixed frequency signals from the reference frequency signal; A feedback unit (200) for generating a comparison frequency signal by sequentially mixing the plurality of fixed frequency signals with the variable frequency signal; And a first PLL unit 110 dividing the comparison frequency signal at a predetermined ratio and comparing the divided comparison frequency signal with the reference frequency signal to fix the phase of the variable frequency signal.

The frequency synthesizer of the present invention includes a variable frequency signal generating circuit for generating a variable frequency signal from a reference frequency signal and a fixed frequency signal generating circuit for generating a plurality of fixed frequency signals from the reference frequency signal . 2, the variable frequency generation circuit according to the embodiment of the present invention includes a first phase locked loop unit 110, a first loop filter 120, a first voltage controlled oscillator 130, (200).

The reference frequency signal source 10 oscillates a reference frequency signal and may be composed of a temperature compensated crystal oscillator (TCXO) or an oven controlled crystal oscillator (OCXO).

The first phase locked loop 110 (PLL) divides the comparison frequency signal at a predetermined ratio and compares the divided comparison frequency signal with the reference frequency signal to fix the phase of the variable frequency signal. Here, the comparison frequency signal refers to a signal obtained by sequentially mixing a plurality of fixed frequency signals generated from a fixed frequency signal generation circuit with a variable frequency signal, which will be described later in connection with the feedback section 200.

The first phase locked loop 110 includes a first reference counter 112 (1 / R), a first phase detector 114 (PFD) and a first frequency divider 116 N).

The first frequency divider 116 receives the compared frequency signal mixed by the feedback unit 200 and divides the compared frequency signal by a predetermined ratio, that is, the dividing ratio of N, and provides the compared frequency signal to the first phase detector 114. Here, the frequency division ratio of the first divider 116 can be varied according to the output frequency signal.

The first phase detector 114 compares the frequency-divided comparison frequency signal from the first frequency divider 116 with a reference frequency signal. Here, the reference frequency signal may be a signal divided by a first reference counter 112 (1 / R), where the first phase detector 114 receives a signal divided by the R counter and a first divider 116, And compares the compared frequency signals. Here, the first phase detector 114 may be of various types according to the circuit type, but a type that operates at the rising edge of the reference signal source 10 and the feedback signal may be used. This is because the phase difference detection range is as wide as -2 to +2, and when the phase difference is zero, the output pulse of the first phase detector 114 is not output, so that the charge pump becomes a high impedance output and is likely to be stabilized.

Also, the first phase detector 114 compares the frequency-divided comparison signal from the first frequency divider 116 with the reference frequency signal, and generates a pulse signal corresponding to the phase difference. For example, if the reference frequency signal is larger or smaller than the reference frequency signal divided from the first frequency divider 116, a pulse corresponding to the difference is generated. The pulses output from the first phase detector 114 are input to the first loop filter 120.

Here, a first charge pump (CP) may be further provided between the first phase detector 114 and the first loop filter 120. The first charge pump performs the function of outputting positive and negative voltages according to the sign of the pulse signal of the first phase detector 114. The first charge pump pushes and pulls a specific amount of charge so that the amount of charge output varies according to the pulse width. Thus, the charge amount of the difference between the two signals is pulled and pulled, ), And (+) voltage.

The first loop filter 120 has a low pass filter (LPF) characteristic. The first loop filter 120 low-pass filters the voltage output from the first charge pump to output only the DC component to the first voltage controlled oscillator 130). That is, the first charge pump and the first loop filter 120 compare the reference frequency signal with the reference frequency signal divided from the first frequency divider 116 by the first phase detector 114, When a signal is generated, the signal is integrated by a frequency difference of the signal, changed to a specific level voltage proportional thereto, and a spurious component is removed. When the first phase detector 114 outputs an undesired spurious component, the first loop filter 120 removes spurious components through the low-pass filter structure to filter unnecessary signals. Here, the first loop filter 120 is divided into an active or passive filter, and the filter end is usually composed of a second or third filter. Due to this difference in configuration, the loop bandwidth and the lock time are determined.

The first voltage controlled oscillator 130 operates as a frequency source that generates a variable frequency signal that is an output frequency signal from the reference frequency signal. That is, the first voltage controlled oscillator 130 outputs a variable frequency signal in accordance with the regulated voltage applied from the first loop filter 120. In other words, it functions as a local oscillator that adjusts the frequency of the signal output to the regulated voltage of the first voltage-controlled oscillator 130 and converts the frequency to RF or IF. The variable frequency signal output from the first voltage controlled oscillator 130 is distributed by the first distributor 140 and is oscillated by the output frequency signal or transmitted to the feedback unit 200.

The feedback unit 200 generates a comparison frequency signal by sequentially mixing a plurality of fixed frequency signals with the variable frequency signal. Here, the plurality of fixed frequency signals are generated from a fixed frequency signal generating unit, that is, a fixed frequency signal generating circuit to be described later, and the feedback unit 200 sequentially mixes a plurality of fixed frequency signals generated from the fixed frequency signal generating circuit And generates a comparison frequency signal to be transmitted to the first phase locked loop unit 110.

Here, the feedback unit 200 down-converts the frequency of the variable frequency signal output from the first voltage controlled oscillator 130 stepwise to generate a comparison frequency signal. That is, when the plurality of fixed frequency signals include the first fixed frequency signal FS1 and the second fixed frequency signal FS2, the feedback unit 200 outputs the first fixed frequency signal FS1 to the variable frequency signal And downconverts the frequency of the variable frequency signal by the frequency of the first fixed frequency signal FS1 and outputs the second fixed frequency signal FS2 to the variable frequency signal in which the first fixed frequency signal FS1 is mixed And secondarily downconverts the frequency of the first down-converted variable frequency signal by the frequency of the second fixed frequency signal FS2. To this end, the feedback unit 200 includes a first mixer 210 (MX: Mixer) for mixing and downconverting the first fixed frequency signal FS1 to the variable frequency signal, and a first fixed frequency signal FS1 And a second mixer 230 for mixing the second fixed frequency signal FS2 with the variable frequency signal.

When the frequency of the variable frequency signal fed back to the first phase locked loop unit 110 is lowered and the frequency of the variable frequency signal fed back to the first phase locked loop unit 110 is lower than the original frequency of the first frequency divider 116, The frequency component fed back in proportion to the reference frequency signal. Here, a typical performance index that defines the signal quality of the frequency synthesizer is phase noise. As described above, the phase noise is calculated as a value of 20 logN. Therefore, in order to lower the frequency of the variable frequency signal output from the first voltage controlled oscillator 130, the frequency synthesizer according to the embodiment of the present invention includes a first fixed frequency signal FS1 and a second fixed frequency signal FS2, . The reason why the fixed frequency signal is sequentially mixed with the first fixed frequency signal FS1 and the second fixed frequency signal FS2 will be described later.

The fixed frequency generation circuit may include a second phase locked loop unit 310, a second loop filter 320, a second voltage controlled oscillator 330, a first filter and a second filter, as shown in FIG. 3 have.

The second PLL 310 (PLL: Phase Lock Loop) divides the initial fixed-frequency signal by a predetermined ratio and compares the divided initial fixed-frequency signal with the reference-frequency signal to fix the phase of the initial fixed-frequency signal . Herein, the initial fixed frequency signal means a signal output directly from the second voltage controlled oscillator 330.

The second phase locked loop unit 310 includes a second reference counter 212 (1 / R), a second phase detector 314 (PFD) and a second frequency divider 316 (1 / N) . ≪ / RTI >

The second frequency divider 316 receives the initial fixed frequency signal output from the second voltage controlled oscillator 330 and divides the initial fixed frequency signal by a predetermined ratio, that is, the division ratio of N, and provides it to the first phase detector 114 do. Here, the frequency division ratio of the second frequency divider 316 is fixed and a signal having a fixed frequency is output. The frequency division ratio of the first frequency divider 116 and the frequency division ratio of the second frequency divider 316 are different from each other Can be different.

The second phase detector 314 compares the initial fixed frequency signal from the second frequency divider 316 with a reference frequency signal. Here, the reference frequency signal may be a signal divided by a second reference counter 312 (1 / R), where the second phase detector 314 receives a signal divided by the R counter and a second frequency divider 316, And compares the divided initial fixed frequency signals. Also, the second phase detector 314 compares the initial fixed frequency signal divided from the second divider 316 with the reference frequency signal, and generates a pulse signal corresponding to the phase difference.

A second charge pump (not shown) (CP) may be further included between the second phase detector 314 and the second loop filter 320. The second loop filter 320 (LC: The low-pass filter (LPF) has a characteristic of a low pass filter (LPF), low-pass filters the voltage output from the second charge pump, and applies only the DC component as an adjustment voltage to the second voltage controlled oscillator 330.

The second voltage controlled oscillator 330 outputs an initial fixed frequency signal from the reference frequency signal. The initial fixed frequency signal output from the second voltage controlled oscillator 330 is distributed by the second -1 divider 340 and transmitted to the second divider 350 and the second phase locked loop unit 310 .

The second-2 distributor 350 distributes the initial fixed-frequency signal output from the second voltage-controlled oscillator 330 to the first filter unit 360 and the second filter unit 370. The first filter unit 360 extracts the first fixed frequency signal FS1 from the initial fixed frequency signal and transmits the extracted first fixed frequency signal FS1 to the first mixer 210. The second filter unit 370 extracts the initial fixed frequency signal FS1 from the initial fixed frequency signal, 2 fixed frequency signal FS2 and transmits it to the second mixer 230. [ At this time, the first fixed frequency signal FS1 and the second fixed frequency signal FS2 may have different frequency components, and the first fixed frequency signal FS1 may be a harmonic frequency signal of the initial fixed frequency signal. And the second fixed frequency signal FS2 may comprise a fundamental frequency signal of the initial fixed frequency signal. Here, the harmonic frequency signal has a frequency component that is an integral multiple of the frequency of the fundamental frequency signal.

In the frequency synthesizer according to the embodiment of the present invention, the harmonic frequency signal is primarily mixed with the variable frequency signal output from the first voltage controlled oscillator 130 and down-converted to lower the frequency of the variable frequency signal first , The source frequency signal is secondarily mixed with the variable frequency signal mixed with the harmonic frequency signal, and then down-converted to lower the frequency of the variable frequency signal that has been primarily lowered.

Here, in order to lower the variable frequency signal, a fixed frequency signal obtained by adding the first fixed frequency signal FS1 and the second fixed frequency signal FS2 to the variable frequency signal may be mixed and down-converted. However, In order to lower the variable frequency signal, the first fixed frequency signal FS1 (harmonic frequency signal) is firstly mixed with the variable frequency signal to down-convert the frequency, and the first fixed frequency signal FS1 And the second fixed frequency signal FS2 (source frequency signal) is secondarily mixed with the mixed variable frequency signal to down-convert the frequency. In order to mix a fixed frequency signal with a variable frequency signal, it is necessary that the fixed frequency signal has a constant output. However, when a fixed frequency signal obtained by adding the first fixed frequency signal FS1 and the second fixed frequency signal FS2 is mixed This is because the output characteristic of the signal is rapidly deteriorated.

For example, when a harmonic frequency signal having a frequency component twice that of the source frequency signal is used as the first fixed frequency signal FS1 and a source frequency signal is used as the second fixed frequency signal FS2, The frequency synthesizing apparatus according to the embodiment of the present invention downconverts the variable frequency signal by a factor of two times the source frequency of the fixed frequency signal, further downconverts the frequency of the variable frequency signal by the source frequency, Can be down-converted by 3 times the original frequency.

However, when the variable frequency signal is down-converted to a harmonic frequency signal having a frequency component three times the frequency of the source frequency signal, in order to mix the harmonic frequency signal having the frequency component three times the source frequency signal with the variable frequency signal It is essential to amplify the harmonic frequency signal and to increase the output by repeating the filter. In this case, not only the structure is complicated but also the white noise is increased and the phase noise characteristic is remarkably lowered.

Therefore, in the frequency synthesizing apparatus according to the embodiment of the present invention, the first fixed frequency signal FS1 (harmonic frequency signal) is primarily mixed with the variable frequency signal to lower the variable frequency signal, It is possible not only to minimize the frequency division ratio by secondarily mixing the second fixed frequency signal FS2 (source frequency signal) with the variable frequency signal mixed with the one fixed frequency signal FS1 and down converting the frequency, It is possible to omit a separate structure for increasing the output of the variable gain amplifier, thereby maintaining excellent phase noise characteristics.

Hereinafter, a frequency synthesizing method of a peer identifier according to an embodiment of the present invention will be described. In the description of the frequency synthesizing method of the peer identifier according to the embodiment of the present invention, the description of the frequency synthesizer of the peer identifier according to the embodiment of the present invention will not be repeated.

4 is a diagram schematically showing a frequency synthesizing method of a peer identifier according to an embodiment of the present invention.

Referring to FIG. 4, a method for synthesizing a frequency of a peer identifier according to an embodiment of the present invention includes the steps of: (S100) outputting a variable frequency signal from a reference frequency signal; A step (S200) of generating a plurality of fixed frequency signals from the reference frequency signal; Generating a comparison frequency by sequentially mixing the plurality of fixed frequency signals with the variable frequency signal (S300); And a step (S400) of dividing the comparison frequency by a predetermined ratio, and comparing the divided comparison frequency signal with the reference frequency signal to fix the phase of the variable frequency signal.

The step S100 of outputting the variable frequency signal is performed by outputting the variable frequency signal from the first voltage controlled oscillator 130 using the reference frequency signal. Here, the first voltage-controlled oscillator 130 operates as a frequency source that generates a variable frequency signal that is an output frequency signal from the reference frequency signal. That is, the first voltage controlled oscillator 130 outputs a variable frequency signal in accordance with the regulated voltage applied from the first loop filter 120. In other words, it functions as a local oscillator that adjusts the frequency of the signal output to the regulated voltage of the first voltage-controlled oscillator 130 and converts the frequency to RF or IF. The variable frequency signal output from the first voltage controlled oscillator 130 is distributed by the first distributor 140 and is oscillated by the output frequency signal or transmitted to the feedback unit 200.

The step S200 of outputting a plurality of fixed frequency signals is performed by dividing the initial fixed frequency signals output from the second voltage controlled oscillator 330 into a plurality of initial frequency signals using the reference frequency signal.

Here, the generating of the plurality of fixed frequency signals includes generating an initial fixed frequency signal from the reference frequency signal, extracting a first fixed frequency signal FS1 from the initial fixed frequency signal, And extracting a second fixed frequency signal FS2 having a frequency component different from the first fixed frequency signal FS1 from the initial fixed frequency signal S120.

The process of outputting the initial fixed frequency signal is performed by outputting the fixed frequency signal from the second voltage controlled oscillator 330 using the reference frequency signal used in the process of outputting the variable frequency signal. Here, the second voltage-controlled oscillator 330 outputs an initial fixed frequency signal from the reference frequency signal.

The phase locked loop (PLL) 310 of the fixed frequency generation circuit is connected to the second voltage controlled oscillator 330, and the phase locked loop (PLL) And the frequency of the initial fixed frequency signal is compared with the reference frequency signal to fix the phase of the initial fixed frequency signal. Herein, the initial fixed frequency signal means a signal output directly from the second voltage controlled oscillator 330.

The second phase locked loop unit 310 includes a second reference counter 312 (1 / R), a second phase detector 314 (PFD) and a second frequency divider 316 (1 / N, and the second frequency divider 316 receives the initial fixed frequency signal output from the second voltage controlled oscillator 330 and divides the initial fixed frequency signal by a predetermined ratio, that is, 1 < / RTI >

At this time, the second phase detector 314 compares the initial fixed frequency signal divided from the second frequency divider 316 with the reference frequency signal. Here, the reference frequency signal may be a signal divided by a second reference counter 312 (1 / R), where the second phase detector 314 receives a signal divided by the R counter and a second frequency divider 316, And compares the divided initial fixed frequency signals. Also, the second phase detector 314 compares the initial fixed frequency signal divided from the second divider 316 with the reference frequency signal, and generates a pulse signal corresponding to the phase difference.

A second charge pump (CP) may be further included between the second phase detector 314 and the second loop filter 320. The second loop filter 320 (LC: Loop Filter) Pass filter (LPF), low-pass filtering the voltage output from the second charge pump, and applying only the DC component as the adjustment voltage of the second voltage-controlled oscillator 330. [

The second voltage controlled oscillator 330 outputs an initial fixed frequency signal from the reference frequency signal. The initial fixed frequency signal output from the second voltage controlled oscillator 330 is distributed by the second -1 divider 340 and transmitted to the second divider 350 and the second phase locked loop unit 310 .

The first fixed frequency signal FS1 is extracted by filtering the initial fixed frequency signal distributed by the second divider 350 by the first filter unit 360 and extracting the first fixed frequency signal FS1 do. In the process of extracting the second fixed frequency signal FS2, the initial fixed frequency signal distributed by the second-divider 350 is filtered by the second filter unit 370 to generate the second fixed frequency signal FS2, . Here, in the process of extracting the first fixed frequency and extracting the second fixed frequency signal FS2, the initial fixed frequency signal is distributed by the second-2 distributor 350, and the first filter 360 and the second filter 360, Can be performed simultaneously by the second filter unit 370.

Here, the process of extracting the first fixed frequency signal FS1 is performed by selectively passing only the frequency component of the harmonic frequency signal in the initial fixed frequency signal by the first filter unit 360, The process of extracting the signal FS2 may be performed by selectively passing only the frequency component of the fundamental frequency signal from the initial fixed frequency signal by the second filter unit 370. [

That is, the second-2 distributor 350 distributes the initial fixed-frequency signal output from the second voltage-controlled oscillator 330 to the first filter unit 360 and the second filter unit 370. The first filter unit 360 extracts the first fixed frequency signal FS1 from the initial fixed frequency signal and transmits the extracted first fixed frequency signal FS1 to the first mixer 210. The second filter unit 370 extracts the initial fixed frequency signal FS1 from the initial fixed frequency signal, 2 fixed frequency signal FS2 and transmits it to the second mixer 230. [ At this time, the first fixed frequency signal FS1 and the second fixed frequency signal FS2 may have different frequency components, and the first fixed frequency signal FS1 may be a harmonic frequency signal of the initial fixed frequency signal. And the second fixed frequency signal FS2 may comprise a fundamental frequency signal of the initial fixed frequency signal. Here, the harmonic frequency signal has a frequency component that is an integral multiple of the frequency of the fundamental frequency signal.

In the step of generating a comparison frequency signal (S300), a plurality of fixed frequency signals are sequentially mixed with the variable frequency signal to generate a comparison frequency. Here, the process of generating the comparison frequency is performed by the feedback unit 200, and the frequency of the variable frequency signal is obtained by mixing the variable frequency signal with the first fixed frequency signal FS1, (S310) for performing down-conversion of the first down-converted variable frequency signal (FS1) and the second fixed frequency signal (FS2) by mixing the variable frequency signal mixed with the first fixed frequency signal (FS1) And converting the frequency of the second fixed frequency signal FS2 to a second frequency lower than the frequency of the second fixed frequency signal FS2 S320.

The first mixer 210 mixes the variable frequency signal with the first fixed frequency signal FS1 to convert the frequency of the variable frequency signal to the first fixed frequency signal FS1 by a first mixer 210, The frequency of the frequency signal is firstly downconverted by the frequency of the first fixed frequency signal FS1 and the frequency of the downconverted variable frequency signal is converted to the frequency of the second fixed frequency signal FS2, The downmixing process is performed by mixing the second fixed frequency signal FS2 with the variable frequency signal in which the first fixed frequency signal FS1 is mixed by the second mixer 230 so that the frequency of the first down- To the second fixed frequency signal FS2.

Here, in the frequency synthesizing method according to the embodiment of the present invention, in order to lower the variable frequency signal, the first fixed frequency signal FS1 (harmonic frequency signal) is primarily mixed with the variable frequency signal to down convert the frequency, The second fixed frequency signal FS2 (source frequency signal) is secondarily mixed with the variable frequency signal in which the one fixed frequency signal FS1 is mixed and the frequency is down-converted. In order to mix a fixed frequency signal with a variable frequency signal, it is necessary that the fixed frequency signal has a constant output. However, when a fixed frequency signal obtained by adding the first fixed frequency signal FS1 and the second fixed frequency signal FS2 is mixed Signal in the case of the frequency synthesizer according to the embodiment of the present invention.

In the step S400 of fixing the phase of the variable frequency signal, the comparison frequency signal is divided by a predetermined ratio, and the divided comparison frequency signal is compared with the reference frequency signal to fix the phase of the variable frequency signal.

The first phase locked loop unit 110 includes a first reference counter 112 (1 / R), a first phase detector 114 ( PFD: Phase Frequency Detector) and a first divider 116 (1 / N). The configuration in which the phase of the variable frequency signal is fixed by each configuration of the first phase locked loop unit 110 is the same as that described above with respect to the frequency synthesizing apparatus according to the embodiment of the present invention, Is omitted.

In the step of fixing the phase of the variable frequency signal (S400), the frequency of the comparison frequency signal is divided by a ratio smaller than a value obtained by dividing the frequency of the variable frequency signal by the frequency of the reference frequency signal. That is, in a frequency synthesizer using a general phase locked loop control, the frequency divider divides the output frequency signal output from the voltage control oscillation section by the division ratio of N, and the phase detector divides the output frequency signal divided by N division ratio and the reference frequency signal The phase of the output frequency signal is fixed and the output frequency signal having the frequency N times the frequency of the reference frequency signal is oscillated by transmitting the control signal to the voltage controlled oscillator.

However, in the frequency synthesizing method according to the embodiment of the present invention, the frequency of the variable frequency signal is first down-converted by the frequency of the first fixed frequency signal FS1, and the frequency of the down- The frequency of the comparison frequency signal can be divided by a ratio smaller than a value obtained by dividing the frequency of the variable frequency signal by the frequency of the reference frequency signal by generating a comparison frequency by down converting the frequency of the second fixed frequency signal FS2 have. In this case, it is possible to remarkably reduce the phase noise calculated by the value of 20 logN with respect to the division ratio N. [

As described above, according to the frequency synthesizer and the frequency synthesizing method of the present invention, a plurality of fixed frequency signals are mixed with a variable frequency signal to generate a comparison frequency signal, and the generated comparison frequency signal is divided The frequency division ratio can be reduced by fixing the phase of the variable frequency signal.

In addition, in the fixed frequency signal, the frequency of the variable frequency signal is primarily down-converted using a harmonic frequency signal that is classified as noise and is to be removed, and the frequency of the variable frequency signal is converted to a second- Not only the noise included in the fixed frequency signal can be reduced, but also the frequency division ratio of the phase fixing process of the fixed frequency signal can be reduced. Thus, the phase noise characteristic can be improved, have.

Therefore, the frequency synthesizer and the frequency synthesis method of the PIAN identifier according to the embodiment of the present invention have a structure favorable to the phase noise characteristic and the miniaturization, and thus have a structure suitable for the equipment of the induction weapon Seeker, UAV or radar .

While the preferred embodiments of the present invention have been described and illustrated above using specific terms, such terms are used only for the purpose of clarifying the invention, and the embodiments of the present invention and the described terminology are intended to be illustrative, It will be obvious that various changes and modifications can be made without departing from the spirit and scope of the invention. Such modified embodiments should not be individually understood from the spirit and scope of the present invention, but should be regarded as being within the scope of the claims of the present invention.

10: reference frequency signal source 110: first phase locked loop unit
112: first counter 114: first phase detector
116: first frequency divider 120: first loop filter
130: first voltage controlled oscillator 140: first distributor
200: feedback section 210: first mixer
230: second mixer 210: second phase locked loop unit
212: second counter 214: second phase detector
216: second frequency divider 220: second loop filter
230: first voltage-controlled oscillator 240: second-1 distributor
250: second-2 distributor 260: first filter unit
270:

Claims (6)

Outputting a variable frequency signal from the reference frequency signal;
Generating a plurality of fixed frequency signals from the reference frequency signal;
Generating a comparison frequency signal by sequentially mixing the plurality of fixed frequency signals with the variable frequency signal; And
Dividing the comparison frequency signal by a predetermined ratio and comparing the divided comparison frequency signal with the reference frequency signal to fix the phase of the variable frequency signal;
Wherein the generating the plurality of fixed frequency signals comprises:
Outputting an initial fixed frequency signal from the reference frequency signal;
Extracting a first fixed frequency signal from the initial fixed frequency signal; And
And extracting a second fixed frequency signal having a frequency component different from the first fixed frequency signal from the initial fixed frequency signal,
In the process of fixing the phase of the variable frequency signal,
Wherein the frequency of the comparison frequency signal is less than a value obtained by dividing the frequency of the variable frequency signal by the frequency of the reference frequency signal.
delete The method according to claim 1,
Wherein the step of extracting the first fixed frequency signal comprises:
Selectively passing only the frequency component of the harmonic frequency signal in the initial fixed frequency signal,
Wherein the step of extracting the second fixed frequency signal comprises:
And selectively passes only a frequency component of a source frequency signal in the initial fixed frequency signal.
The method according to claim 1,
Wherein the step of extracting the first fixed frequency signal and the step of extracting the second fixed frequency signal are simultaneously performed.
delete delete
KR1020180040485A 2018-04-06 2018-04-06 Frequency synthesizing method for identification friend or foe KR101865323B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020180040485A KR101865323B1 (en) 2018-04-06 2018-04-06 Frequency synthesizing method for identification friend or foe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020180040485A KR101865323B1 (en) 2018-04-06 2018-04-06 Frequency synthesizing method for identification friend or foe

Publications (1)

Publication Number Publication Date
KR101865323B1 true KR101865323B1 (en) 2018-06-07

Family

ID=62621844

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020180040485A KR101865323B1 (en) 2018-04-06 2018-04-06 Frequency synthesizing method for identification friend or foe

Country Status (1)

Country Link
KR (1) KR101865323B1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455911A (en) * 1987-08-27 1989-03-02 Toshiba Corp Frequency synthesizer
KR100727307B1 (en) 2006-03-14 2007-06-12 엘지전자 주식회사 Phase locked loop
US20090268845A1 (en) * 2004-11-18 2009-10-29 Broadcom Corporation Radio transmitter incorporating digital modulator and circuitry to accommodate baseband processor with analog interface

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455911A (en) * 1987-08-27 1989-03-02 Toshiba Corp Frequency synthesizer
US20090268845A1 (en) * 2004-11-18 2009-10-29 Broadcom Corporation Radio transmitter incorporating digital modulator and circuitry to accommodate baseband processor with analog interface
KR100727307B1 (en) 2006-03-14 2007-06-12 엘지전자 주식회사 Phase locked loop

Similar Documents

Publication Publication Date Title
US7250823B2 (en) Direct digital synthesis (DDS) phase locked loop (PLL) frequency synthesizer and associated methods
US5034703A (en) Frequency synthesizer
EP2873152B1 (en) Ultra low phase noise signal source
US8242818B2 (en) Phase-locked loop frequency synthesizer
CN103490777B (en) low spurious frequency synthesizer
DE60307963T2 (en) Linearization technique for phase locked loops using a differential charge pump circuit
CN106067815B (en) Frequency synthesizer based on DDS and fractional frequency division phase-locked loop
US7120413B2 (en) Television tuner and method of processing a received RF signal
EP1775843A1 (en) Local oscillator with injection pulling suppression and spurious products filtering
JP2012120178A (en) Frequency synthesizer and frequency synthesizing method
EP1748559A1 (en) Automatic frequency control loop circuit
US8736326B1 (en) Frequency synthesizer and frequency synthesis method thereof
CN1874142B (en) Electric circuit for generating reference signal
WO2005117252A2 (en) Digital noise coupling reduction and variable intermediate frequency generation in mixed signal circuits
US20050093584A1 (en) Fast-hopping frequency synthesizer
US6753711B2 (en) Digital summing phase-lock loop circuit with sideband control and method therefor
US20070287401A1 (en) Frequency offset correction in receivers having non-ideal synthesizer channel spacing
CN113726334A (en) S-band low-phase-noise low-spurious fine-stepping frequency source component and using method
US7945218B1 (en) Method and system for tuning quality factor in high-Q, high-frequency filters
KR101865323B1 (en) Frequency synthesizing method for identification friend or foe
CN117081588A (en) Broadband low-phase-noise agile frequency synthesizer and signal synthesis method thereof
KR101865324B1 (en) Frequency synthesizing apparatus for identification friend or foe
KR101007210B1 (en) High frequency synthesizer for airbone with compact size
US4095190A (en) Tuning system
US6198354B1 (en) System for limiting if variation in phase locked loops

Legal Events

Date Code Title Description
E701 Decision to grant or registration of patent right
GRNT Written decision to grant