CN113013157A - PMOS (P-channel metal oxide semiconductor) ESD (electronic static discharge) device with embedded silicon controlled rectifier and implementation method thereof - Google Patents
PMOS (P-channel metal oxide semiconductor) ESD (electronic static discharge) device with embedded silicon controlled rectifier and implementation method thereof Download PDFInfo
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- CN113013157A CN113013157A CN202110209117.0A CN202110209117A CN113013157A CN 113013157 A CN113013157 A CN 113013157A CN 202110209117 A CN202110209117 A CN 202110209117A CN 113013157 A CN113013157 A CN 113013157A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 25
- 239000010703 silicon Substances 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 229910044991 metal oxide Inorganic materials 0.000 title description 3
- 150000004706 metal oxides Chemical class 0.000 title description 3
- 230000003068 static effect Effects 0.000 title description 2
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 20
- 238000002955 isolation Methods 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 claims description 11
- 239000002019 doping agent Substances 0.000 description 19
- 230000000694 effects Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 101100365087 Arabidopsis thaliana SCRA gene Proteins 0.000 description 1
- 101150105073 SCR1 gene Proteins 0.000 description 1
- 101100134054 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NTG1 gene Proteins 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
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Abstract
The invention discloses a PMOS type ESD device with an embedded silicon controlled rectifier and an implementation method thereof, wherein the ESD device comprises: a semiconductor substrate; an N well generated in the substrate; high-concentration P-type doping (22), high-concentration N-type doping (30) and high-concentration P-type doping (24) are arranged at the upper part of the N well, and P-type ESD doping is arranged below the N well; a P-type gate is arranged above the N well between the high-concentration P-type doping (20) and the high-concentration P-type doping (22); respectively generating metal silicides above the high-concentration N-type doping (32) and the high-concentration P-type doping (20) and leading out electrodes to be connected to form an anode; metal silicides are respectively generated above the high-concentration N-type doping (30) and the high-concentration P-type doping (24), leading-out electrodes are connected to be used as cathodes, and an RC time delay circuit is arranged between the anode and the cathode to adjust the grid voltage of the P-type grid.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a PMOS (P-channel metal oxide semiconductor) ESD (electro-static discharge) device embedded with a silicon controlled rectifier and used for anti-static protection design and an implementation method thereof.
Background
In the field of integrated circuit anti-static protection design, an anti-static protection design window generally depends on working voltage and gate oxide thickness of an internal protected circuit, taking a 55LP advanced process platform of a certain company as an example, the working voltage of a core device (1.2V MOSFET) is 1.2V, and the gate oxide thickness is 25A, so the anti-static protection design window of the core device (1.2V MOSFET) of the 55LP advanced process platform of the certain company is generally between 1.32V and 5V. However, the hysteresis effect characteristic curve of the core device (1.2V NMOS) of the 55LP apc platform of this company is shown in fig. 1, which indicates that the trigger voltage (Vt1, the lower inflection point of the right curve) of the core device is 6.7V, which exceeds the esd protection design window of the core device, and if the core device (1.2V NMOS) is directly used for the esd protection design, the reliability problem of the gate oxide layer of the core device (1.2V MOSFET) is easily caused.
In 2015, some literature in the industry first proposed a PMOS ESD device with embedded scr as shown in fig. 2, which is intended to solve the ESD protection design problem of the advanced platform core device, and according to the device structure of fig. 2, a corresponding equivalent circuit diagram as shown in fig. 3 can be obtained.
According to the equivalent circuit diagram of the existing PMOS ESD device with embedded scr, it can be found that the drain 22/28 of the PMOS (22/40/20/60) device itself constitutes the base of the parasitic NPN triode (60/28/30) inside the embedded scr, and the trigger mechanism is to trigger the hysteresis effect of the embedded scr by using the leakage current generated by the breakdown (breakdown) of the drain of the PMOS device, so the trigger voltage (Vt1) of the hysteresis effect of the existing PMOS ESD device with embedded scr is determined by the drain breakdown voltage of the PMOS device. The actually measured hysteresis effect curve of the SCR embedded device reported in this document in a certain process platform is shown as the curve corresponding to the deployed SCR1 (right triangle) in fig. 4a, and in order to see clear data, the dashed box at the lower left corner of fig. 4a is enlarged to see fig. 4b, which shows that the trigger voltage (Vt1) of the existing PMOS embedded rectifier device is about 5.5V, and the middle inflection point of the lower curve at the lower position of the lower curve at the left side of the existing PMOS embedded rectifier device is indeed able to greatly reduce the trigger voltage (Vt1) of the hysteresis effect compared with the conventional SCR embedded rectifier, but still exceeds the anti-static protection design window of the core device of the general advanced CMOS process platform, so it is necessary to further reduce the trigger voltage of the hysteresis effect.
Disclosure of Invention
In order to overcome the defects of the prior art, the present invention provides a PMOS ESD device with an embedded scr and a method for implementing the same, so as to implement a PMOS ESD device capable of reducing the trigger voltage of the embedded scr more easily.
To achieve the above and other objects, the present invention provides a PMOS ESD device with embedded scr, comprising:
a semiconductor substrate (80);
an N-well (60) created in the semiconductor substrate (80);
high-concentration N-type doping (32), high-concentration P-type doping (20), high-concentration P-type doping (22), high-concentration N-type doping (30) and high-concentration P-type doping (24) are sequentially arranged at the upper part of the N well (60), and a layer of P-type ESD doping (28) is arranged under the high-concentration P-type doping (22), the high-concentration N-type doping (30), the high-concentration P-type doping (24) and the interval part between the high-concentration P-type doping and the high-concentration P-type doping;
a part of the N well (60) is arranged between the high-concentration P-type doping (20) and the high-concentration P-type doping (22), and a P-type gate (40) is arranged above the part of the N well;
respectively generating metal silicide (50) above the high-concentration N-type doping (32) and above the high-concentration P-type doping (20), leading out electrodes to be connected and forming an anode of the PMOS-type ESD device; and respectively generating metal silicide (50) above the high-concentration N-type doping (30) and the high-concentration P-type doping (24), leading out electrodes to be connected as cathodes of the PMOS-type ESD devices, and arranging an RC time delay circuit between the anode and the cathode to adjust the grid voltage of the P-type grid (40).
Preferably, a resistor is connected between the anode and the P-type grid (40), and a capacitor is connected between the P-type grid (40) and the cathode.
Preferably, the resistance ranges from 100 Ω to 1M Ω.
Preferably, the value range of the capacitor is 100 fF-10 pF.
Preferably, the time constant of the RC delay circuit is set to 1nS to 100 nS.
Preferably, the high-concentration N-type doping (32) and the high-concentration P-type doping (20) are arranged at the upper left part of the N well (60), and the high-concentration P-type doping (22), the high-concentration N-type doping (30) and the high-concentration P-type doping (24) are arranged at the upper right part of the N well (60).
Preferably, the high-concentration N-type doping (32) and the high-concentration P-type doping (20) are isolated by a shallow trench isolation layer (10), the left side of the high-concentration N-type doping (32) is the shallow trench isolation layer (10), and the right sides of the high-concentration N-type doping (24) and the P-type ESD doping (28) are the shallow trench isolation layer (10).
In order to achieve the purpose, the invention also provides a method for realizing the PMOS type ESD device with the embedded silicon controlled rectifier, the method disconnects a P type grid (40) which is directly connected with an anode in the existing PMOS type ESD device with the embedded silicon controlled rectifier, and an RC time delay circuit is arranged between the anode and the cathode to adjust the grid voltage of the P type grid (40).
Preferably, the method comprises the steps of:
step S1, providing a semiconductor substrate;
step S2, generating an N-well (60) in the P-type substrate (80), sequentially generating high-concentration N-type doping (32), high-concentration P-type doping (20), high-concentration P-type doping (22), high-concentration N-type doping (30) and high-concentration P-type doping (24) on the upper part of the N-well (60), and generating a layer of P-type ESD doping (28) under the high-concentration P-type doping (22), the high-concentration N-type doping (30), the high-concentration P-type doping (24) and the interval part between the high-concentration P-type doping (22), the high-concentration N-type doping (30), the high-concentration P-type;
step S3, forming a P-type gate (40) above a part of the N-well (60) between the high-concentration P-type doping (20) and the high-concentration P-type doping (22);
step S4, respectively generating metal silicide (50) above the high-concentration N-type doping (32) and the high-concentration P-type doping (20), leading out electrodes to be connected and forming an anode of the PMOS-type ESD device; and respectively generating metal silicide (50) above the high-concentration N-type doping (30) and the high-concentration P-type doping (24), leading out electrodes to be connected as cathodes of the PMOS-type ESD devices, and arranging an RC time delay circuit between the anode and the cathode to adjust the grid voltage of the P-type grid (40).
Preferably, a resistor is connected between the anode and the P-type grid (40), and a capacitor is connected between the P-type grid (40) and the cathode.
Compared with the prior art, the PMOS type ESD device with the embedded silicon controlled rectifier and the implementation method thereof have the advantages that the connection between the P type grid 40 and the anode in the PMOS type ESD device with the embedded silicon controlled rectifier is disconnected, the grid voltage of the PMOS type ESD device is adjusted and controlled by the RC delay circuit, when ESD pulse is applied to the anode of the PMOS type ESD device, the PMOS type ESD device is in a conducting state due to the adjustment of the RC delay circuit on the grid voltage, the PMOS embedded silicon controlled rectifier of the PMOS type ESD device is triggered by the aid of the PMOS after the PMOS is conducted, compared with the existing PMOS device with the embedded silicon controlled rectifier, the trigger voltage of the embedded silicon controlled rectifier is easier to reduce.
Drawings
FIG. 1 is a 1.2V GGNMOS hysteresis effect characteristic curve of a company 55LP process platform;
FIG. 2 is a diagram of a prior art PMOS ESD device with an embedded SCR;
FIG. 3 is an equivalent circuit diagram of a PMOS ESD device with an embedded SCR;
FIG. 4a is a graph showing hysteresis effect characteristics of a conventional PMOS device with an embedded SCR;
FIG. 4b is an enlarged detail view of the hysteresis effect characteristic curve of the PMOS device with the embedded SCR;
FIG. 5 is a diagram of the device structure of a PMOS ESD device with embedded SCR according to the present invention;
FIG. 6 is an equivalent circuit diagram of a PMOS ESD device with embedded SCR according to the present invention;
FIG. 7 is a flowchart illustrating steps of a method for implementing a PMOS ESD device with an embedded SCR according to the present invention;
fig. 8 is a schematic view of an application scenario of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
FIG. 5 is a diagram of a device structure of a PMOS ESD device with embedded SCR according to the present invention. As shown in fig. 5, a PMOS ESD device with embedded scr according to the present invention includes: a plurality of Shallow Trench Isolation (STI) layers 10, high concentration N-type dopants (N +)32, high concentration P-type dopants (P +)20, high concentration P-type dopants (P +)22, high concentration N-type dopants (N +)30, high concentration P-type dopants (P +)24, P-type ESD dopants (P-ESD IMP)28, N-wells (N-Well)60, P-type gates (P-Gate)40, and a plurality of metal silicides (Silicide)50 connecting the doped regions and the electrodes.
The whole ESD device is arranged on a P-type substrate (P-Sub)80, an N-Well (N-Well)60 is generated in the P-type substrate (P-Sub)80, high-concentration N-type doping (N +)32 and high-concentration P-type doping (P +)20 are arranged at the upper left part of the N-Well (N-Well)60, high-concentration P-type doping (P +)22, high-concentration N-type doping (N +)30 and high-concentration P-type doping (P +)24 are arranged at the upper right part of the N-Well (N-Well)60, a layer of P-type ESD IMP 28 is arranged right below the high-concentration P-type doping (P +)22, the high-concentration N-type doping (N +)30, the high-concentration P-type doping (P +)24 and a spacing part in the middle of the high-concentration P-type doping (P +)20, the N-Well (N-Well)60 and the P-type ESD IMP 28 form an equivalent triode structure, the N-Well (N-Well)60, the P-type ESD doping (P-ESD IMP)28 and the high-concentration N-type doping (N +)30 form an equivalent NPN triode structure;
the high-concentration N-type doping (N +)32 and the high-concentration P-type doping (P +)20 are isolated by a Shallow Trench Isolation (STI) 10, a part of an N-Well (N-Well)60 is arranged between the right side of the high-concentration P-type doping (P +)20 and the high-concentration P-type doping (P +)22, a P-Gate (P-Gate)40 is arranged above the N-Well, and the left side of the high-concentration N-type doping (N +)32 is the Shallow Trench Isolation (STI 10); a part of an N Well (N-Well)60 is formed among the high-concentration P-type doping (P +)22, the high-concentration N-type doping (N +)30 and the high-concentration P-type doping (P +)24, namely, the bottom of the high-concentration P-type doping (P +)22, the bottom of the high-concentration N-type doping (N +)30, the bottom of the high-concentration P-type doping (P +)24 and the space part between the two are directly under a layer of P-type ESD doping (P-IMP) 28, and the right sides of the high-concentration N-type doping (N +)24 and the P-type ESD doping (P-ESD IMP)28 are Shallow Trench Isolation (STI, Shallow Trench Isolation) 10; the interval between the high-concentration P-type doping (P +)22 and the high-concentration N-type doping (N +)30 is S, the interval between the high-concentration N-type doping (N +)30 and the high-concentration P-type doping (P +)24 is S, the width of the high-concentration P-type doping (P +)22 and the high-concentration P-type doping (P +)24 is a, and the width of the high-concentration N-type doping (N +)30 is B.
2 metal silicide 50 leading-out electrodes are generated above the high-concentration N-type doping (N +)32 and above the high-concentration P-type doping (P +)20 and connected with each other to form an Anode of the PMOS device; forming a metal silicide 50 on the high concentration N-type doping (N +)30 and the high concentration P-type doping (P +)24 to lead out an electrode to be connected as a Cathode Cathode of the PMOS device of the invention; a resistor R is connected between the Anode and the P-Gate (P-Gate)40, the value range of the resistor R is 100 omega-1M omega, a capacitor C is connected between the P-Gate (P-Gate)40 and the Cathode, the value range of the capacitor C is 100 fF-10 pF, and the time constant of the RC delay circuit can be set to be 1 nS-100 nS;
the equivalent circuit diagram of the invention is shown in fig. 6, the invention connects the P-type gate 40 with the Anode in the existing PMOS type ESD device (22/40/20/60), the high concentration N-type dopant (N +)32 with the high concentration P-type dopant (P +)20 to form the Anode anide of the PMOS type ESD device of the invention, the node a is a network in which a resistor R and a capacitor C are connected to the P-type gate 40, the gate voltage of the PMOS type ESD device is adjusted and controlled by using an RC delay circuit, when an ESD pulse is applied to the Anode of the PMOS type ESD device of the embedded silicon controlled rectifier, the PMOS type ESD device is in a conducting state due to the adjustment of the gate voltage by the RC delay circuit, the PMOS after conducting assists to trigger the silicon controlled rectifier embedded in the PMOS type ESD device, compared with the existing PMOS type ESD device of the embedded silicon controlled rectifier, the silicon controlled rectifier embedded in the PMOS type ESD device is assisted to trigger by the breakdown of the PMOS device, the novel PMOS ESD device with the embedded silicon controlled rectifier is easier to reduce the trigger voltage (Vt1) of the embedded silicon controlled rectifier, so the PMOS ESD device with the embedded silicon controlled rectifier is more suitable for the anti-static protection design of the core device of the advanced CMOS process platform.
Fig. 7 is a flowchart illustrating steps of a method for implementing a PMOS ESD device with an embedded scr according to the present invention. As shown in fig. 7, the method for implementing a PMOS ESD device with an embedded scr according to the present invention includes the following steps:
in step S1, a semiconductor substrate is provided, and in one embodiment of the present invention, a P-type substrate (P-Sub)80 is provided, and an N-Well (N-Well)60 is formed in the P-type substrate (P-Sub) 80.
Step S2, forming an N-Well (N-Well)60 in the P-type substrate (P-Sub)80, sequentially forming a high concentration N-type dopant (N +)32 and a high concentration P-type dopant (P +)20 at the upper left portion of the N-Well (N-Well)60, forming a high concentration P-type dopant (P +)22, a high concentration N-type dopant (N +)30, and a high concentration P-type dopant (P +)24 at the upper right portion of the N-Well (N-Well)60, forming a layer of P-type ESD dopant (P-ESD IMP)28 directly under the high concentration P-type dopant (P +)22, the high concentration N-type dopant (N +)30, the high concentration P-type dopant (P +)24, and the intervening portion thereof, wherein the high concentration P-type dopant (P +)20, the N-Well (N-Well)60, and the P-type ESD dopant (P-ESD IMP)28 form a PNP equivalent triode structure, the N-Well (N-Well)60, the P-ESD doping (P-ESD IMP)28 and the high concentration N-type doping (N +)30 form an equivalent NPN triode structure.
Step S3, isolating the high-concentration N-type doping (N +)32 and the high-concentration P-type doping (P +)20 with a Shallow Trench Isolation (STI) 10, where the right side of the high-concentration P-type doping (P +)20 and the high-concentration P-type doping (P +)22 are part of an N-Well (N-Well)60, a P-type Gate (P-Gate)40 is disposed above the N-Well, and the left side of the high-concentration N-type doping (N +)32 is the Shallow Trench Isolation (STI) 10; the high concentration P-type doping (P +)22, the high concentration N-type doping (N +)30, and the high concentration P-type doping (P +)24 are part of an N-Well (N-Well)60, and the Shallow Trench Isolation (STI) 10 is disposed on the right side of the high concentration N-type doping (N +)24 and the P-type ESD doping (P-ESD IMP) 28. The interval between the high-concentration P-type doping (P +)22 and the high-concentration N-type doping (N +)30 is S, the interval between the high-concentration N-type doping (N +)30 and the high-concentration P-type doping (P +)24 is S, the width of the high-concentration P-type doping (P +)22 and the high-concentration P-type doping (P +)24 is a, and the width of the high-concentration N-type doping (N +)30 is B.
Step S4, forming 2 metal silicides 50 above the high concentration N-type doping (N +)32 and above the high concentration P-type doping (P +)20, and connecting the leading electrodes to form an Anode of the PMOS ESD device of the present invention; generating a metal silicide 50 above the high-concentration N-type doping (N +)30 and the high-concentration P-type doping (P +)24, and leading out an electrode to be connected to be used as a Cathode of the PMOS ESD device; a resistor R is connected between the Anode and the P-Gate (P-Gate)40, the value range of the resistor R is 100 omega-1M omega, a capacitor C is connected between the P-Gate (P-Gate)40 and the Cathode, the value range of the capacitor C is 100 fF-10 pF, and the time constant of the RC delay circuit can be set to be 1 nS-100 nS;
when in application, in order to protect an IO port, the Cathode of the PMOS type ESD device of the embedded silicon controlled rectifier is connected with an external IO (input/output end) and is internally connected with an internal circuit, the PMOS type ESD device is grounded Vss through a certain ESD protection device, and the anode of the PMOS type ESD device is connected with a power supply voltage Vdd; in order to protect the power supply, some other ESD protection device may be connected after the PMOS ESD device embedded with the scr to obtain the required characteristics, as shown in fig. 8.
In summary, the PMOS ESD device with embedded scr and the implementation method thereof according to the present invention disconnect the P-type gate 40 from the anode in the existing PMOS device with embedded scr, and the grid voltage of the PMOS type ESD device is adjusted and controlled by an RC time delay circuit, when an ESD pulse is applied to the anode of the PMOS type ESD device, the PMOS ESD device is in a conducting state due to the adjustment of the RC delay circuit to the grid voltage, the PMOS after being conducted assists in triggering the silicon controlled rectifier embedded in the PMOS ESD device, compared with the existing PMOS device with the embedded silicon controlled rectifier, which utilizes the breakdown of the PMOS device to assist in triggering the silicon controlled rectifier embedded in the PMOS device, the trigger voltage (Vt1) of the embedded silicon controlled rectifier is easier to reduce, therefore, the invention is more suitable for the anti-static protection design of the core device of the advanced CMOS process platform.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (10)
1. A PMOS type ESD device with embedded scr, comprising:
a semiconductor substrate (80);
an N-well (60) created in the semiconductor substrate (80);
high-concentration N-type doping (32), high-concentration P-type doping (20), high-concentration P-type doping (22), high-concentration N-type doping (30) and high-concentration P-type doping (24) are sequentially arranged at the upper part of the N well (60), and a layer of P-type ESD doping (28) is arranged under the high-concentration P-type doping (22), the high-concentration N-type doping (30), the high-concentration P-type doping (24) and the interval part between the high-concentration P-type doping and the high-concentration P-type doping;
a part of the N well (60) is arranged between the high-concentration P-type doping (20) and the high-concentration P-type doping (22), and a P-type gate (40) is arranged above the part of the N well;
respectively generating metal silicide (50) above the high-concentration N-type doping (32) and above the high-concentration P-type doping (20), leading out electrodes to be connected and forming an anode of the PMOS-type ESD device; and respectively generating metal silicide (50) above the high-concentration N-type doping (30) and the high-concentration P-type doping (24), leading out electrodes to be connected as cathodes of the PMOS-type ESD devices, and arranging an RC time delay circuit between the anode and the cathode to adjust the grid voltage of the P-type grid (40).
2. The ESD device of claim 1, wherein: a resistor is connected between the anode and the P-type grid (40), and a capacitor is connected between the P-type grid (40) and the cathode.
3. The ESD device of claim 2, wherein: the resistance ranges from 100 omega to 1M omega.
4. The ESD device of claim 2, wherein: the value range of the capacitor is 100 fF-10 pF.
5. The ESD device of claim 2, wherein: the time constant of the RC delay circuit is set to be 1 nS-100 nS.
6. The ESD device of claim 2, wherein: the high-concentration N-type doping (32) and the high-concentration P-type doping (20) are arranged at the left upper part of the N well (60), and the high-concentration P-type doping (22), the high-concentration N-type doping (30) and the high-concentration P-type doping (24) are arranged at the right upper part of the N well (60).
7. The ESD device of claim 6, wherein: the high-concentration N-type doping (32) and the high-concentration P-type doping (20) are isolated by a shallow channel isolation layer (10), the left side of the high-concentration N-type doping (32) is the shallow channel isolation layer (10), and the right sides of the high-concentration N-type doping (24) and the P-type ESD doping (28) are the shallow channel isolation layer (10).
8. A method for realizing a PMOS type ESD device with an embedded silicon controlled rectifier is characterized in that: the method comprises the steps of disconnecting a P-type grid (40) directly connected with an anode in a PMOS-type ESD device embedded with a silicon controlled rectifier, and arranging an RC time delay circuit between the anode and a cathode to adjust the grid voltage of the P-type grid (40).
9. The method of claim 8, wherein the method comprises the following steps:
step S1, providing a semiconductor substrate (80);
step S2, generating an N-well (60) in the semiconductor substrate (80), sequentially generating a high-concentration N-type doping (32), a high-concentration P-type doping (20), a high-concentration P-type doping (22), a high-concentration N-type doping (30) and a high-concentration P-type doping (24) on the upper part of the N-well (60), and generating a layer of P-type ESD doping (28) under the high-concentration P-type doping (22), the high-concentration N-type doping (30), the high-concentration P-type doping (24) and the interval part between the high-concentration P-type doping (22), the high-concentration N-type doping (30), the high;
step S3, forming a part of the N well (60) between the high-concentration P-type doping (20) and the high-concentration P-type doping (22), and forming a P-type gate (40) above the part of the N well;
step S4, respectively generating metal silicide (50) above the high-concentration N-type doping (32) and the high-concentration P-type doping (20), leading out electrodes to be connected and forming an anode of the PMOS-type ESD device; and respectively generating metal silicide (50) above the high-concentration N-type doping (30) and the high-concentration P-type doping (24), leading out electrodes to be connected as cathodes of the PMOS-type ESD devices, and arranging an RC time delay circuit between the anode and the cathode to adjust the grid voltage of the P-type grid (40).
10. The method of claim 9, wherein a resistor is connected between said anode and said P-type gate (40), and a capacitor is connected between said P-type gate (40) and said cathode.
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