CN110518010A - A kind of PMOS device and its implementation of embedded thyristor - Google Patents
A kind of PMOS device and its implementation of embedded thyristor Download PDFInfo
- Publication number
- CN110518010A CN110518010A CN201910808797.0A CN201910808797A CN110518010A CN 110518010 A CN110518010 A CN 110518010A CN 201910808797 A CN201910808797 A CN 201910808797A CN 110518010 A CN110518010 A CN 110518010A
- Authority
- CN
- China
- Prior art keywords
- type
- high concentration
- doping
- type doping
- pmos device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000000605 extraction Methods 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 230000000694 effects Effects 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 238000012423 maintenance Methods 0.000 abstract description 7
- 230000001737 promoting effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thyristors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses the PMOS devices and its implementation of a kind of embedded thyristor, low concentration N-type is replaced with by the high concentration n-type doping that the PMOS device of existing embedded thyristor is connected cathode, and (30) are lightly doped, and (30) upper surface is lightly doped in the low concentration N-type and forms metal silicide, cathode of the extraction electrode as the PMOS device, the p-type ESD below high concentration p-type doping (20) and high concentration p-type doping (26) is removed simultaneously to adulterate, the present invention can promote its maintenance voltage higher than its operating voltage while promoting PMOS device secondary breakdown current.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields, are used for ESD (Electro-Static more particularly to one kind
Discharge, Electro-static Driven Comb) embedded thyristor PMOS device and its implementation.
Background technique
In integrated circuit antistatic protection design field, antistatic protection design protection window is generally dependent on operating voltage
With the gate oxide thickness of internal protected circuit.It is with the 28nm high-K/Metal Gate technique platform of industry routine
Example, the gate oxide thickness of I/O device is about 40A, operating voltage 1.8V, then the 28nm high-K/Metal Gate
The antistatic protection design window of technique platform is usually between 2.2V~8V.
PMOS device results in the second breakdown of its echo effect because the mobility ratio of its internal carrier hole is lower
Electric current It2 is relatively low, industry in order to promote the secondary breakdown current of PMOS in 28nm High-K/Metal Gate technique platform,
A kind of PMOS device of embedded thyristor was proposed in 2015, as shown in Figure 1, being inserted into the drain electrode of PMOS device high
Concentration N-dopant (N+) 30, and p-type ESD doping (P-ESD IMP) 10~12 is all added below source-drain electrode, it then will be highly concentrated
The connection of n-type doping (N+) 30 cathode is spent, then forms a parasitic PNPN (high concentration p-type doping inside the PMOS device at this time
(P+) 20/N trap (N-Well) 60/P type ESD adulterates (P-ESD IMP) 10/ high concentration n-type doping (N+) 30 or high concentration p-type
Adulterate (P+) 26/N trap (N-Well) 60/P type ESD and adulterate (P-ESD IMP) 10/ high concentration n-type doping (N+) 30) silicon control rectification
The secondary breakdown current of device, the PMOS of the embedded thyristor greatly promotes, as shown in table 1 below:
Table 1
Table 1 is the PMOS of existing embedded thyristor and traditional under 28nm High-K/Metal Gate technique
The echo effect parameter comparison sheet of GGNMOS and GDPMOS, it can be found that existing embedded thyristor PMOS can will be traditional
The secondary breakdown current of PMOS greatly promotes, and has been even more than the secondary breakdown current of traditional GGNMOS, but its maintenance voltage
But there was only 1.7V or so, be less than operating voltage 1.8V, be easy the trigger latch effect in external disturbance, it can be seen that in existing
The PMOS of embedding thyristor is not particularly suited for antistatic protection design, so needing to existing embedded thyristor
PMOS device is further improved, and promotes its maintenance voltage Vh, makes that it is suitable for antistatic protection designs.
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of embedded thyristors
PMOS device and its implementation, to promote its maintenance voltage while promoting PMOS device secondary breakdown current higher than its work
Make voltage, makes that it is suitable for antistatic protection designs.
In view of the above and other objects, the present invention proposes a kind of PMOS device of embedded thyristor, the PMOS device
Part includes:
Semiconductor substrate (80)；
The N trap (60) being created in the semiconductor substrate (80)；
High concentration n-type doping (32), high concentration p-type doping (20) are placed in the left side of the N trap (60), and high concentration p-type is mixed
(30) are lightly doped in miscellaneous (22), low concentration N-type, high concentration p-type doping (24) is placed in the centre of the N trap (60), and high concentration N-type is mixed
Miscellaneous (34), high concentration p-type doping (26) are placed in the right of the N trap (60), the bottom of the high concentration p-type doping (22), low
One layer of p-type is arranged in the lower section that (30) bottom, high concentration p-type doping (24) bottom and its intermediate spacing section is lightly doped in concentration N-type
ESD adulterates (10)；
The first p-type grid are arranged in top between the high concentration p-type doping (20) and high concentration p-type doping (22)
(40), the second p-type grid (42) are arranged in the top between the high concentration n-type doping (24) and high concentration p-type doping (26)；
The top of the high concentration n-type doping (32), high concentration p-type doping (20) top generate metal silicide and with
The first p-type grid (40) are connected to form the anode of the PMOS device, and the low concentration N-type, which is lightly doped above (30), generates gold
Belong to cathode of the silicide extraction electrode as the PMOS device, the top of the high concentration n-type doping (34), high concentration p-type
The top of doping (26) generates metal silicide and is connected to form the anode of the PMOS device with the second p-type grid (42).
Preferably, the high concentration p-type doping (20), N trap (60) and p-type ESD doping (10) constitute equivalent tri- pole PNP
Pipe structure.
Preferably, the N trap (60), p-type ESD doping (10) and low concentration N-type are lightly doped (30) and constitute tri- pole equivalent N PN
Pipe structure.
Preferably, the high concentration p-type doping (26), N trap (60) and p-type ESD doping (10) constitute equivalent tri- pole PNP
Pipe structure.
Preferably, it is isolated between the high concentration n-type doping (32), high concentration p-type doping (20) with shallow trench isolation layer,
It is a part of the N trap (60) between the right side and high concentration p-type doping (22) of the high concentration p-type doping (20).
It preferably, is the one of the N trap (60) between the high concentration n-type doping (24) and high concentration p-type doping (26)
Part is isolated between the high concentration p-type doping (26) and high concentration n-type doping (34) with shallow trench isolation layer.
Preferably, the echo effect characteristic of the PMOS device is adulterated (22) by the high concentration p-type and is mixed with high concentration p-type
The width B of (30), high concentration p-type doping (22) and low concentration N-type is lightly doped in the width A of miscellaneous (24), the low concentration N-type
It is lightly doped the interval between (30) and interval between (30) and high concentration p-type doping (24) is lightly doped in the low concentration N-type
S, the low concentration N-type be lightly doped (30) doping concentration determine, wherein A be 0.1~1um, B be 0.1~2um, S be 0~
2um, doping concentration dosage range are 1E12~1E15/cm2。
In order to achieve the above objectives, the present invention also provides a kind of implementation method of the PMOS device of embedded thyristor, institutes
Method is stated gently to mix the high concentration n-type doping replacement low concentration N-type of the PMOS device connection cathode of existing embedded thyristor
Miscellaneous (30), and (30) upper surface is lightly doped in the low concentration N-type and forms metal silicide, extraction electrode is as the PMOS device
The cathode of part, and the p-type ESD removed below high concentration p-type doping (20) and high concentration p-type doping (26) is adulterated.
Preferably, described method includes following steps:
Step S1 is provided semi-conductive substrate (80), and a N trap (60) is generated in the semiconductor substrate (80)；
High concentration n-type doping (32), high concentration p-type doping (20) are placed in the left side of the N trap (60) by step S2, high
(30) are lightly doped in concentration of P type doping (22), low concentration N-type, high concentration p-type doping (24) is placed in the centre of the N trap (60), high
Concentration N-dopant (34), high concentration p-type doping (26) are placed in the right of the N trap (60), and the high concentration p-type adulterates (22)
Bottom, low concentration N-type be lightly doped (30) bottom, high concentration p-type doping (24) bottom and its intermediate spacing section below set
One layer of p-type ESD doping (10) is set, the top between Yu Suoshu high concentration p-type doping (20) and high concentration p-type doping (22) is set
The first p-type grid (40) are set, the second p-type grid are arranged in the top between the high concentration n-type doping (24) and high concentration p-type doping (26)
(42)；
The top of step S3, Yu Suoshu high concentration n-type doping (32), the top of high concentration p-type doping (20) generate metal
(30) are lightly doped in silicide and the anode that the PMOS device is connected to form with the first p-type grid (40), the low concentration N-type
Cathode of the top generation metal silicide extraction electrode as the PMOS device, the top of the high concentration n-type doping (34),
The top of high concentration p-type doping (26) generates metal silicide and is connected to form the PMOS device with the second p-type grid (42)
The anode of part.
Preferably, the echo effect characteristic of the PMOS device is adulterated (22) by the high concentration p-type and is mixed with high concentration p-type
The width B of (30), high concentration p-type doping (22) and low concentration N-type is lightly doped in the width A of miscellaneous (24), the low concentration N-type
It is lightly doped the interval between (30) and interval between (30) and high concentration p-type doping (24) is lightly doped in the low concentration N-type
S, the low concentration N-type be lightly doped (30) doping concentration determine, wherein A be 0.1~1um, B be 0.1~2um, S be 0~
2um, doping concentration dosage range are 1E12~1E15/cm2。
Compared with prior art, the PMOS device and its implementation of a kind of embedded thyristor of the present invention pass through existing
Embedded thyristor PMOS device in connect the high concentration n-type doping of cathode and replace with the N-type being lightly doped and be lightly doped
(NLDD), and remove jointed anode high concentration p-type doping lower section P-ESD IMP doping, can promoted PMOS device it is secondary
Maintenance voltage is promoted while breakdown current and is higher than its operating voltage, makes that it is suitable for antistatic protection designs.
Detailed description of the invention
Fig. 1 is the schematic diagram of the PMOS device of the embedded thyristor of the prior art；
Fig. 2 is a kind of device junction composition of the preferred embodiment of the PMOS device of embedded thyristor of the present invention；
The step of Fig. 3 is a kind of preferred embodiment of implementation method of the PMOS device of embedded thyristor of the present invention is flowed
Cheng Tu；
Fig. 4 is application scenarios schematic diagram of the invention.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 2 is a kind of device junction composition of the preferred embodiment of the PMOS device of embedded thyristor of the present invention.Such as Fig. 2
It is shown, a kind of PMOS device of embedded thyristor of the present invention, comprising: multiple shallow trench isolation layer (STI, Shallow
Trench Isolation) 70, high concentration n-type doping (N+) 32, high concentration p-type doping (P+) 20, high concentration p-type doping (P+)
22, (NLDD) 30, high concentration p-type doping (P+) 24, p-type ESD doping 10, high concentration (P-ESD IMP) are lightly doped in low concentration N-type
P-type adulterates (P+) 26, high concentration n-type doping (N+) 34, N trap (N-Well) 60, the 80, first p-type grid of P type substrate (P-Sub) (P-
Gate) the metal silicide (Silicide) 50 of the 40, second p-type grid (P-Gate) 42 and multiple connecting doped areas and electrode.
Entire ESD device is placed in P type substrate (P-Sub) 80, and a N trap (N- is generated in P type substrate (P-Sub) 80
Well) 60, high concentration n-type doping (N+) 32, high concentration p-type doping (P+) 20 are placed in the upper left quarter of N trap (N-Well) 60, highly concentrated
It spends p-type doping (P+) 20, N trap (N-Well) 60 and p-type ESD doping (P-ESD IMP) 10 and constitutes equivalent PNP triode knot
Structure, (NLDD) 30 is lightly doped in high concentration p-type doping (P+) 22, low concentration N-type, high concentration p-type doping (P+) 24 is placed in N trap (N-
Well (NLDD) is lightly doped in) 60 middle and upper part, N trap (N-Well) 60, p-type ESD doping (P-ESD IMP) 10 and low concentration N-type
30 constitute equivalent N PN audion, and high concentration n-type doping (N+) 34, high concentration p-type doping (P+) 26 are placed in N trap (N-
Well) 60 upper right quarter, high concentration p-type adulterate (P+) 26, N trap (N-Well) 60 and p-type ESD and adulterate (P-ESD IMP) 10
Constitute equivalent PNP triode structure；
Shallow trench isolation layer (STI, Shallow are used between high concentration n-type doping (N+) 32, high concentration p-type doping (P+) 20
Trench Isolation) 70 isolation, it is N trap that high concentration p-type, which is adulterated between the right side of (P+) 20 and high concentration p-type doping (P+) 22,
(N-Well) 60 a part places the first p-type grid (P-Gate) 40 above the N trap of the part；High concentration p-type adulterates (P+)
22, a part that it is N trap (N-Well) 60 between (NLDD) 30, high concentration p-type doping (P+) 24 that low concentration N-type, which is lightly doped, it is highly concentrated
The underface that degree p-type doping 22 bottom (P+) to high concentration of P type adulterates 24 bottom (P+) is that one layer of p-type ESD adulterates (P-ESD
IMP) 10, i.e. 30 bottom (NLDD), high concentration p-type doping (P is lightly doped in high concentration p-type doping 22 bottom (P+), low concentration N-type
+) lower section of 24 bottoms and in-between compartment is that one layer of p-type ESD adulterates (P-ESD IMP) 10；High concentration n-type doping (N
+) it is a part of N trap (N-Well) 60 between 24 and high concentration p-type doping (P+) 26, the second p-type is placed above the N trap of the part
Grid (P-Gate) 42, high concentration p-type adulterate between (P+) 26 and high concentration n-type doping (N+) 34 with shallow trench isolation layer (STI,
Shallow Trench Isolation) 70 isolation；High concentration p-type doping (P+) 22, low concentration N-type are lightly doped between (NLDD) 30
Between be divided into S, low concentration N-type is divided into S between being lightly doped between (NLDD) 30, high concentration p-type doping (P+) 24, and high concentration p-type adulterates (P
+) 22 and high concentration p-type doping (P+) 24 width be A, low concentration N-type be lightly doped (NLDD) 30 width be B；
2 metal silications are generated in the top that the top of high concentration n-type doping (N+) 32, high concentration p-type adulterate (P+) 20
Object 50 and be connected to form with the first p-type grid (P-Gate) 40 present invention PMOS device anode A node, it is light in low concentration N-type
The top for adulterating (NLDD) 30 generates cathode Cathode of 50 extraction electrode of metal silicide as the PMOS device of the present invention,
The top that the top of high concentration n-type doping (N+) 34, high concentration p-type adulterate (P+) 26 generate 2 metal silicides 50 and with
Second p-type grid (P-Gate) 42 are connected to form the anode A node of the PMOS device of the present invention.
The PMOS device of embedded thyristor proposed by the invention for ESD is actually by the existing of such as Fig. 1
Embedded thyristor PMOS device in connect the high concentration n-type doping of cathode and replace with the N-type of low concentration and be lightly doped
(NLDD) 30, the N-type of the low concentration is lightly doped inside PMOS device of (NLDD) 30 as novel embedded thyristor and posts
Raw NPN ((NLDD) 30/P type ESD doping (P-ESD IMP) 10/N trap (N-Well) 60 is lightly doped in low concentration N-type) triode
Emitter, the efficiency of launching electronics reduces because of the reduction of n-type doping concentration itself, and it reduce the novel PMOS devices
Endoparasitic NPN ((NLDD) 30/P type ESD doping (P-ESD IMP) 10/N trap (N-Well) 60 is lightly doped in low concentration N-type)
Current gain (the β of triodeNPN)；The high concentration p-type of jointed anode is adulterated (P+) 20 to still further aspect and high concentration p-type is mixed
P-type ESD doping (P-ESD IMP) the 11-12 removal of 26 lower section miscellaneous (P+), can reduce high concentration p-type to a certain extent and mix
Miscellaneous (P+) 20 and high concentration p-type adulterate the efficiency that (P+) 26 emits hole to N trap (N-Well) 60, this is reduced to a certain extent
(high concentration p-type doping (P+) 20 or 26/N trap (N-Well) 60/P type ESD mixes the endoparasitic PNP of PMOS device of the present invention
Miscellaneous (P-ESD IMP) 10) triode current gain (βPNP), the two combines, can be by the embedded silicon control rectification of the present invention
The maintenance voltage of the PMOS device echo effect of device is promoted to 2.2V or more, so embedded thyristor proposed by the invention
PMOS device be more suitable for 28nm High-K/Metal Gate technique platform antistatic protection design.
In the present invention, size A, B, S and NLDD doping of the PMOS device of the embedded thyristor for being used for ESD are dense
Degree determines its echo effect performance characteristic together, and wherein A is 0.1~1um, and B is 0.1~2um, and S is 0~2um, doping concentration
Dosage range is 1E12~1E15/cm2。
The step of Fig. 3 is a kind of preferred embodiment of implementation method of the PMOS device of embedded thyristor of the present invention is flowed
Cheng Tu.As shown in figure 3, a kind of implementation method of the PMOS device of embedded thyristor of the present invention, includes the following steps:
Step S1, provides semi-conductive substrate, in the specific embodiment of the invention, provides a P type substrate (P-Sub) 80,
And a N trap (N-Well) 60 is generated in the P type substrate (P-Sub) 80.
Step S2 utilizes high concentration p-type doping (P+) 20, N trap (N-Well) 60 and p-type ESD doping (P-ESD IMP)
10 form equivalent PNP triode structure in the upper left quarter of N trap (N-Well) 60, utilize N trap (N-Well) 60, p-type ESD doping
(P-ESD IMP) 10 and low concentration N-type are lightly doped (NLDD) 30 and constitute tri- pole equivalent N PN in the middle and upper part of N trap (N-Well) 60
Pipe structure, using high concentration p-type doping (P+) 26, N trap (N-Well) 60 and p-type ESD doping (P-ESD IMP) 10 in N trap
(N-Well) 60 upper right quarter constitutes equivalent PNP triode structure, specifically, by high concentration n-type doping (N+) 32, high concentration P
Type doping (P+) 20 is placed in the upper left quarter of N trap (N-Well) 60, and high concentration p-type adulterates (P+) 20, N trap (N-Well) 60 and P
Type ESD adulterates (P-ESD IMP) 10 and constitutes equivalent PNP triode structure, and high concentration p-type doping (P+) 22, low concentration N-type are gently mixed
Miscellaneous (NLDD) 30, high concentration p-type doping (P+) 24 are placed in the middle and upper part of N trap (N-Well) 60, N trap (N-Well) 60, p-type ESD
Doping (P-ESD IMP) 10 and low concentration N-type are lightly doped (NLDD) 30 and constitute equivalent N PN audion, high concentration n-type doping
(N+) 34, high concentration p-type doping (P+) 26 is placed in the upper right quarter of N trap (N-Well) 60, and high concentration p-type adulterates (P+) 26, N trap
(N-Well) 60 and p-type ESD adulterates (P-ESD IMP) 10 and constitutes equivalent PNP triode structure.
Wherein, high concentration n-type doping (N+) 32, high concentration p-type doping (P+) 20 between with shallow trench isolation layer (STI,
Shallow Trench Isolation) 70 isolation, high concentration p-type adulterates the right side of (P+) 20 and high concentration p-type adulterates (P+)
Between 22 it is a part of N trap (N-Well) 60, and places the first p-type grid (P-Gate) 40 above the N trap of the part；High concentration P
It is the one of N trap (N-Well) 60 that type doping (P+) 22, low concentration N-type, which are lightly doped between (NLDD) 30, high concentration p-type doping (P+) 24,
Part, the underface that high concentration p-type doping 22 bottom (P+) to high concentration of P type adulterates 24 bottom (P+) is one layer of p-type ESD doping
30 bottom (NLDD), high concentration p-type is lightly doped in (P-ESD IMP) 10, i.e. high concentration p-type doping 22 bottom (P+), low concentration N-type
The lower section for adulterating 24 bottom (P+) and in-between compartment is that one layer of p-type ESD adulterates (P-ESD IMP) 10；High concentration N-type
It adulterates and is a part of N trap (N-Well) 60 between (N+) 24 and high concentration p-type doping (P+) 26, and put above the N trap of the part
The second p-type grid (P-Gate) 42 are set, use shallow trench isolation between high concentration p-type doping (P+) 26 and high concentration n-type doping (N+) 34
Layer (STI, Shallow Trench Isolation) 70 is isolated；High concentration p-type doping (P+) 22, low concentration N-type are lightly doped
(NLDD) between 30 between be divided into S, low concentration N-type is divided into S, high concentration between being lightly doped between (NLDD) 30, high concentration p-type doping (P+) 24
It is A that p-type, which adulterates (P+) 22 and the width of high concentration p-type doping (P+) 24, and the width that (NLDD) 30 is lightly doped in low concentration N-type is
B。
Step S3 generates 2 gold in the top that the top of high concentration n-type doping (N+) 32, high concentration p-type adulterate (P+) 20
Belong to silicide 50 and be connected to form the anode A node of the PMOS device of the present invention with the first p-type grid (P-Gate) 40, in low concentration
The top that (NLDD) 30 is lightly doped in N-type generates cathode of 50 extraction electrode of metal silicide as the PMOS device of the present invention
Cathode generates 2 metal silications in the top that the top of high concentration n-type doping (N+) 34, high concentration p-type adulterate (P+) 26
Object 50 and be connected to form with the second p-type grid (P-Gate) 42 present invention PMOS device anode A node.
In application, for protection I/O port, by Cathode pairs of cathode of the PMOS device of the embedded thyristor of the present invention
External IO (input/output terminal) is grounded Vss to inscribed internal circuit, and by certain ESD protective device, and anode connects power supply electricity
Press Vdd, anode A node；For protection power source, others can also be connected after the PMOS device for embedding thyristor
Certain ESD protective device is to obtain the characteristics of needs, as shown in Figure 4.
In conclusion the PMOS device and its implementation of a kind of embedded thyristor of the present invention are embedded by existing
The high concentration n-type doping that cathode is connected in the PMOS device of thyristor replaces with the N-type being lightly doped and is lightly doped (NLDD), and
The P-ESD doping for removing the high concentration p-type doping lower section of jointed anode, can promote the same of PMOS device secondary breakdown current
Shi Tisheng maintenance voltage is higher than its operating voltage, and the PMOS device of the embedded thyristor of the present invention is more suitable for 28nm
The antistatic protection of High-K/Metal Gate technique platform integrated circuit designs.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (10)
1. a kind of PMOS device of embedded thyristor, which is characterized in that the PMOS device includes:
Semiconductor substrate (80)；
The N trap (60) being created in the semiconductor substrate (80)；
High concentration n-type doping (32), high concentration p-type doping (20) are placed in the left side of the N trap (60), the doping of high concentration p-type
(22), (30) are lightly doped in low concentration N-type, high concentration p-type doping (24) is placed in the centre of the N trap (60), high concentration n-type doping
(34), high concentration p-type doping (26) is placed in the right of the N trap (60), the bottom of the high concentration p-type doping (22), low dense
(30) bottom is lightly doped in degree N-type, the one layer of p-type ESD in high concentration p-type doping (24) bottom and its setting of intermediate spacing section lower section mixes
Miscellaneous (10)；
The first p-type grid (40), institute is arranged in top between the high concentration p-type doping (20) and high concentration p-type doping (22)
The second p-type grid (42) are arranged in the top stated between high concentration n-type doping (24) and high concentration p-type doping (26)；
The top of the high concentration n-type doping (32), high concentration p-type doping (20) top generate metal silicide and with it is described
First p-type grid (40) are connected to form the anode of the PMOS device, and the low concentration N-type, which is lightly doped above (30), generates metallic silicon
Cathode of the compound extraction electrode as the PMOS device, the top of the high concentration n-type doping (34), the doping of high concentration p-type
(26) top generates metal silicide and is connected to form the anode of the PMOS device with the second p-type grid (42).
2. a kind of PMOS device of embedded thyristor as described in claim 1, which is characterized in that it is characterized by: institute
It states high concentration p-type doping (20), N trap (60) and p-type ESD doping (10) and constitutes equivalent PNP triode structure.
3. a kind of PMOS device of embedded thyristor as described in claim 1, which is characterized in that it is characterized by: institute
It states N trap (60), p-type ESD doping (10) and low concentration N-type and (30) composition equivalent N PN audion is lightly doped.
4. a kind of PMOS device of embedded thyristor as claimed in claim 2, which is characterized in that it is characterized by: institute
It states high concentration p-type doping (26), N trap (60) and p-type ESD doping (10) and constitutes equivalent PNP triode structure.
5. a kind of PMOS device of embedded thyristor as described in claim 1, which is characterized in that it is characterized by: institute
It states and is isolated between high concentration n-type doping (32), high concentration p-type doping (20) with shallow trench isolation layer, the high concentration p-type doping
It (20) is a part of the N trap (60) between right side and high concentration p-type doping (22).
6. a kind of PMOS device of embedded thyristor as described in claim 1, which is characterized in that it is characterized by: institute
State high concentration n-type doping (24) and high concentration p-type doping (26) between be the N trap (60) a part, the high concentration p-type
It adulterates and is isolated between (26) and high concentration n-type doping (34) with shallow trench isolation layer.
7. a kind of PMOS device of embedded thyristor as described in claim 1, it is characterised in that: the PMOS device
It is light that echo effect characteristic is adulterated the width A of (22) and high concentration p-type doping (24), the low concentration N-type by the high concentration p-type
Interval between (30) and described is lightly doped in width B, high concentration p-type doping (22) and the low concentration N-type for adulterating (30)
Low concentration N-type be lightly doped (30) and high concentration p-type doping (24) between interval S, the low concentration N-type mixing for (30) is lightly doped
Miscellaneous concentration determines, wherein A is 0.1~1um, and B is 0.1~2um, and S is 0~2um, doping concentration dosage range be 1E12~
1E15/cm2。
8. a kind of implementation method of the PMOS device of embedded thyristor, it is characterised in that: by existing embedded thyristor
The high concentration n-type doping of PMOS device connection cathode replace with low concentration N-type and be lightly doped (30), and in the low concentration N-type
(30) upper surface is lightly doped and forms metal silicide, cathode of the extraction electrode as the PMOS device, and removes high concentration p-type
The p-type ESD below (20) and high concentration p-type doping (26) is adulterated to adulterate.
9. a kind of implementation method of the PMOS device of embedded thyristor as claimed in claim 8, which is characterized in that described
Method includes the following steps:
Step S1 is provided semi-conductive substrate (80), and a N trap (60) is generated in the semiconductor substrate (80)；
High concentration n-type doping (32), high concentration p-type doping (20) are placed in the left side of the N trap (60), high concentration P by step S2
(30) are lightly doped in type doping (22), low concentration N-type, high concentration p-type doping (24) is placed in the centre of the N trap (60), high concentration N
Type doping (34), high concentration p-type doping (26) are placed in the right of the N trap (60), the bottom of the high concentration p-type doping (22)
The lower section setting one of (30) bottom, high concentration p-type doping (24) bottom and its intermediate spacing section is lightly doped in portion, low concentration N-type
Layer p-type ESD doping (10), Yu Suoshu high concentration p-type adulterate the top between (20) and high concentration p-type doping (22) and are arranged the
The second p-type grid are arranged in one p-type grid (40), the top between the high concentration n-type doping (24) and high concentration p-type doping (26)
(42)；
The top of step S3, Yu Suoshu high concentration n-type doping (32), the top of high concentration p-type doping (20) generate metal silication
Object and the anode that the PMOS device is connected to form with the first p-type grid (40), the low concentration N-type are lightly doped above (30)
Generate cathode of the metal silicide extraction electrode as the PMOS device, it is the top of the high concentration n-type doping (34), highly concentrated
The top of degree p-type doping (26) generates metal silicide and is connected to form the PMOS device with the second p-type grid (42)
Anode.
10. a kind of implementation method of the PMOS device of embedded thyristor as claimed in claim 9, it is characterised in that: institute
The echo effect characteristic for stating PMOS device is adulterated width A, the institute of (22) and high concentration p-type doping (24) by the high concentration p-type
State low concentration N-type be lightly doped the width B of (30), the high concentration p-type doping (22) and low concentration N-type be lightly doped between (30)
(30) and high concentration p-type is lightly doped in interval and the low concentration N-type, and to adulterate interval S between (24), the low concentration N-type light
The doping concentration for adulterating (30) determines that wherein A is 0.1~1um, and B is 0.1~2um, and S is 0~2um, doping concentration dosage range
For 1E12~1E15/cm2。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910808797.0A CN110518010B (en) | 2019-08-29 | 2019-08-29 | PMOS device with embedded silicon controlled rectifier and implementation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910808797.0A CN110518010B (en) | 2019-08-29 | 2019-08-29 | PMOS device with embedded silicon controlled rectifier and implementation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110518010A true CN110518010A (en) | 2019-11-29 |
| CN110518010B CN110518010B (en) | 2021-07-16 |
Family
ID=68627917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910808797.0A Active CN110518010B (en) | 2019-08-29 | 2019-08-29 | PMOS device with embedded silicon controlled rectifier and implementation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110518010B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113013157A (en) * | 2021-02-24 | 2021-06-22 | 上海华力微电子有限公司 | PMOS (P-channel metal oxide semiconductor) ESD (electronic static discharge) device with embedded silicon controlled rectifier and implementation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012063378A1 (en) * | 2010-11-08 | 2012-05-18 | パナソニック株式会社 | Semiconductor integrated circuit |
| CN107516657A (en) * | 2017-07-31 | 2017-12-26 | 上海华力微电子有限公司 | A kind of new E SD protection structures and its implementation |
| CN108091650A (en) * | 2017-12-28 | 2018-05-29 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
| CN108389891A (en) * | 2018-01-19 | 2018-08-10 | 湖南师范大学 | A kind of double grid grid-control silicon controlled rectifier (SCR) Electro-static Driven Comb device and preparation method thereof |
-
2019
- 2019-08-29 CN CN201910808797.0A patent/CN110518010B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012063378A1 (en) * | 2010-11-08 | 2012-05-18 | パナソニック株式会社 | Semiconductor integrated circuit |
| CN107516657A (en) * | 2017-07-31 | 2017-12-26 | 上海华力微电子有限公司 | A kind of new E SD protection structures and its implementation |
| CN108091650A (en) * | 2017-12-28 | 2018-05-29 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
| CN108389891A (en) * | 2018-01-19 | 2018-08-10 | 湖南师范大学 | A kind of double grid grid-control silicon controlled rectifier (SCR) Electro-static Driven Comb device and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113013157A (en) * | 2021-02-24 | 2021-06-22 | 上海华力微电子有限公司 | PMOS (P-channel metal oxide semiconductor) ESD (electronic static discharge) device with embedded silicon controlled rectifier and implementation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110518010B (en) | 2021-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100452433C (en) | Semiconductor device and high voltage p-type metal oxide semiconductor (HVPMOS) device | |
| US7372109B2 (en) | Diode and applications thereof | |
| CN108183101B (en) | Without echo effect thyristor type esd protection structure and its implementation | |
| US10930641B2 (en) | Series connected ESD protection circuit | |
| CN108091650B (en) | Without echo effect thyristor type esd protection structure and its implementation | |
| CN110690270B (en) | PMOS device with embedded silicon controlled rectifier and implementation method thereof | |
| CN107248514A (en) | A kind of new E SD protection structures and its implementation | |
| US8476672B2 (en) | Electrostatic discharge protection device and method for fabricating the same | |
| US8598625B2 (en) | ESD protection device with tunable design windows | |
| CN107195630B (en) | A kind of new E SD protection structure and its implementation | |
| TWI665805B (en) | Electrostatic discharge protection apparatus and applications thereof | |
| CN110518012B (en) | Grid-constrained silicon controlled rectifier ESD device and implementation method thereof | |
| CN110504254B (en) | Grid-constrained silicon controlled rectifier ESD device and implementation method thereof | |
| CN110504253B (en) | Grid-constrained silicon controlled rectifier ESD device and manufacturing method thereof | |
| CN110518010A (en) | A kind of PMOS device and its implementation of embedded thyristor | |
| CN108766964B (en) | LDMOS electrostatic protection device | |
| CN109300895B (en) | ESD protection device of LDMOS-SCR structure | |
| CN111799257B (en) | Protection ring for improving negative current latch-up prevention capability of high-voltage integrated circuit and implementation method | |
| US7411251B1 (en) | Self protecting NLDMOS, DMOS and extended voltage NMOS devices | |
| US11222886B2 (en) | ESD protection device with low trigger voltage | |
| CN116207090A (en) | Electrostatic discharge protection structure | |
| CN111799256A (en) | Protection ring for improving negative current latching prevention capability of high-voltage integrated circuit and implementation method | |
| CN112071834A (en) | Gate-constrained silicon controlled rectifier and implementation method thereof | |
| CN112071835A (en) | Gate-constrained silicon controlled rectifier and implementation method thereof | |
| CN110518011B (en) | Grid-constrained silicon controlled rectifier ESD device and implementation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |