CN113010353B - Nuclear address updating method, mapping method, data transmission method, device and chip - Google Patents
Nuclear address updating method, mapping method, data transmission method, device and chip Download PDFInfo
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Abstract
The present disclosure provides a method for updating a core address, the method comprising: updating the original address of at least part of cores into an updated address according to a preset size; the arrangement mode of the update addresses of the cores is the same as the arrangement mode of the original addresses of the cores, the preset size is the size of an array formed by the update addresses of the cores, and at least part of the cores have no update addresses. And the maintenance cost of the multi-core chip is saved. The disclosure also provides a mapping method, a data transmission method, a core address updating device, a mapping device, a chip and a computer readable medium.
Description
Technical Field
The disclosure relates to the technical field of artificial intelligent chips, and in particular relates to a core address updating method, a mapping method, a data transmission method, a core address updating device, a mapping device, a chip and a computer readable medium.
Background
A chip (e.g., an artificial intelligence chip) may be comprised of one or more processors, with multiple complete compute engines (cores) typically integrated into one processor, and with cores within one processor or among multiple processors cooperating.
When a failed core occurs in the chip, the failed core cannot execute the algorithm, but the probability of route damage is low. Therefore, these failed cores, although not capable of algorithmic mapping, still have routing functionality. Currently, when the above-mentioned fault occurs, because the fault core cannot execute the algorithm, it may be necessary to remap the entire chip so that the algorithm is mapped onto the core capable of executing the algorithm, or directly replace the entire chip with a normal chip, and the entire chip is disabled, which is costly.
Disclosure of Invention
The present disclosure provides a core address updating method, a mapping method, a data transmission method, a core address updating device, a mapping device, a chip, and a computer readable medium.
In a first aspect, the present disclosure provides a method for updating a core address, the method comprising:
updating the original address of at least part of cores into an updated address according to a preset size; the arrangement mode of the update addresses of the cores is the same as the arrangement mode of the original addresses of the cores, the preset size is the size of an array formed by the update addresses of the cores, and at least part of the cores have no update addresses.
In some embodiments, the updating the original address of at least part of the cores to the updated address according to the preset size includes:
Determining a preset topological direction and a deletion amount thereof according to the preset size;
determining a deletion amount of cores as deletion cores in each row of cores arranged along a preset topological direction;
Updating the original address of the non-deleted core into an updated address, wherein the deleted core has no updated address.
In some embodiments, the determining that the deletion amount of cores is a deletion core in each row of cores arranged along the preset topology direction includes:
When any row of cores arranged along the preset topological direction has no fault core, determining the deletion quantity of cores positioned at the preset position in the row of cores as deletion cores.
In some embodiments, the deleted quantity core located at the predetermined position in the row of cores is the last deleted quantity core in the row of cores along the preset topology direction.
In some embodiments, the determining that the deletion amount of cores is a deletion core in each row of cores arranged along the preset topology direction includes:
when any row of cores arranged along the preset topological direction has a fault core, determining that a deletion amount of cores in the row of cores are deletion cores, and determining that all the fault cores in the row are deletion cores.
In some embodiments, when the number of failed cores in the row of cores is n less than the deletion amount, the determining that the deletion amount of cores in the row of cores is a deletion core includes:
And determining all the fault cores in the row of cores as deletion cores, and determining the last n non-fault cores in the row of cores along the preset topological direction as deletion cores.
In some embodiments, the determining the preset topology direction and the deletion amount thereof according to the preset size includes:
Determining the maximum fault core number of each topological direction; the maximum number of the fault cores is the maximum value of the number of the fault cores in all the row cores arranged along the corresponding topological direction;
determining the allowable deletion amount of each topological direction when different topological directions are taken as preset topological directions according to the preset size;
Determining part of topological directions as preset topological directions according to the maximum fault core number and the allowable deletion amount, and determining the allowable deletion amount of the corresponding topological directions as the deletion amount of the preset topological directions; the maximum fault nucleus number of any preset topological direction does not exceed the deletion amount.
In some embodiments, the preset arrangement mode is a two-dimensional matrix, and one topological direction is determined as a preset topological direction from row topological directions and column topological directions of the two-dimensional matrix.
In a second aspect, the present disclosure provides a mapping method for a chip whose core address is updated according to the foregoing core address updating method, the mapping method including:
and mapping a plurality of tasks to the cores with the updated addresses according to the arrangement condition of the updated addresses of the cores in the chip.
In some embodiments, before mapping the plurality of tasks to the core with the updated address according to the arrangement of the updated addresses of the cores in the chip, the method further comprises:
And compiling the problem to be processed according to the preset size to obtain the tasks.
In a third aspect, the present disclosure provides a data transmission method for a chip whose core address is updated according to the aforementioned core address updating method, the data transmission method including:
acquiring data, wherein the data comprises a destination core update address;
And transmitting the data to the target core at least according to the update address of the target core.
In some embodiments, the transmitting the data to the destination core based at least on the destination core update address includes:
And transmitting the data to the target core according to the corresponding relation between the original address and the updated address of at least part of the cores, the original address of at least part of the cores and the updated address of the target core.
In some embodiments, the transmitting the data to the destination core based at least on the destination core update address includes:
Determining a destination core original address corresponding to the destination core update address;
And transmitting the data to the target core according to the original address of each core.
In a fourth aspect, the present disclosure provides a device for updating a core address of a chip, where the chip includes a plurality of cores, original addresses of the plurality of cores are arranged according to a preset arrangement manner, and the device for updating a core address includes:
The updating module is used for updating the original address of at least part of the cores into an updated address according to the preset size; the arrangement mode of the update addresses of the cores is the same as the arrangement mode of the original addresses of the cores, the preset size is the size of an array formed by the update addresses of the cores, and at least part of the cores have no update addresses.
In a fifth aspect, the present disclosure provides a mapping apparatus for a chip whose core address is updated according to the aforementioned core address updating method, including:
And the mapping module is used for mapping a plurality of tasks to the cores with the updated addresses according to the arrangement condition of the updated addresses of the cores in the chip.
In a sixth aspect, the present disclosure provides a chip comprising a plurality of cores, the chip for implementing at least one of the following methods:
The method for updating the core address is as described above;
A mapping method as described above;
Such as the data transmission method described above.
In a seventh aspect, the present disclosure provides a computer readable medium having stored thereon a computer program, wherein the computer program when executed by a processing core performs at least one of the following methods:
The method for updating the core address is as described above;
A mapping method as described above;
Such as the data transmission method described above.
Before the chip leaves the factory, the original address of at least part of the cores is updated into the updated address according to the preset size, so that the size of an array formed by the updated addresses of the cores is consistent with the preset size, namely the arrangement layout of the updated addresses is matched with the compiling arrangement layout of the cores, and the cores corresponding to each updated address in the array formed by the updated addresses of the cores can execute an algorithm and data can still be transmitted according to the original address arrangement situation of the cores. Under the condition that no fault core exists, updating the original address of at least part of cores into updated addresses according to a preset size, and reserving at least part of cores without updated addresses as backup (backup), which is equivalent to providing a certain allowable fault amount and avoiding the need of recompilation when the fault core exists; under the condition that a fault core occurs, the original address of at least part of non-fault cores is updated to be an updated address according to the preset size, the whole chip is not required to be recompiled, the whole chip is not required to be directly replaced, the chip can still work normally, and the maintenance cost required when the fault core occurs in the multi-core chip is saved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure, without limitation to the disclosure. The above and other features and advantages will become more readily apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
FIG. 1 is a flowchart of a method for updating a core address according to an embodiment of the present disclosure;
FIG. 2 is a flowchart of another method for updating a core address according to an embodiment of the present disclosure;
FIG. 3 is a flowchart of yet another method for updating a core address according to an embodiment of the present disclosure;
FIG. 4 is a flowchart of another method for updating a core address according to an embodiment of the present disclosure;
FIG. 5 is a flowchart of yet another method for updating a core address according to an embodiment of the present disclosure;
FIG. 6 is a flow chart of a mapping method provided by an embodiment of the present disclosure;
FIG. 7 is a flow chart of yet another mapping method provided by an embodiment of the present disclosure;
fig. 8 is a flowchart of a data transmission method according to an embodiment of the present disclosure;
fig. 9 is a flowchart of another data transmission method according to an embodiment of the present disclosure;
Fig. 10 is a flowchart of yet another data transmission method according to an embodiment of the present disclosure;
FIG. 11 is a schematic diagram illustrating an arrangement of primary addresses of cores according to an embodiment of the present disclosure;
FIG. 12 is a schematic diagram illustrating an arrangement of original addresses of another core according to an embodiment of the present disclosure;
FIG. 13 is a diagram illustrating an arrangement of update addresses of cores according to an embodiment of the present disclosure;
FIG. 14 is a schematic diagram illustrating an arrangement of the original addresses of a core according to another embodiment of the present disclosure;
FIG. 15 is a schematic diagram illustrating an arrangement of original addresses of another core according to an embodiment of the present disclosure;
FIG. 16 is a schematic diagram illustrating an arrangement of the original addresses of a core according to another embodiment of the present disclosure;
FIG. 17 is a block diagram illustrating an address update apparatus according to an embodiment of the present disclosure;
Fig. 18 is a block diagram of a mapping apparatus according to an embodiment of the present disclosure.
Detailed Description
For a better understanding of the technical solutions of the present disclosure, exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings, in which various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a flowchart of a method for updating a core address according to an embodiment of the present disclosure.
Referring to fig. 1, an embodiment of the present disclosure provides a core address update method for updating a core address of a chip.
The chip comprises a plurality of cores, and original addresses of the cores are arranged according to a preset arrangement mode.
Each core in the chip has an address (or ID Identity document, identity) which can be abstracted as coordinates, the original address being the original address that has not been updated. The primary addresses of the cores in the chip are arranged according to a preset arrangement manner, for example, the primary addresses may be arranged according to a matrix form, and each primary address is taken as an element in the matrix, but the specific content of the matrix may be different, for example, the size of the matrix (the number of rows and columns of the matrix, i.e., the number of primary addresses in the two directions of the row direction and the column direction) may be different. The original address may transfer data between two cores adjacent in the row direction of the matrix or adjacent in the column direction of the matrix.
It should be noted that, the original addresses may be arranged in other arrangements such as a three-dimensional body, and each original address is a coordinate in the three-dimensional body, but the dimensions of the three-dimensional body (i.e., the number of original addresses in the three directions of the X-axis, the Y-axis, and the Z-axis) may be different.
Referring to fig. 11, taking a total of 16 cores on a chip as an example, each circle represents one core, the primary addresses of the 16 cores are arranged in a matrix form, and the primary addresses of the 16 cores are respectively: (1, 1), (2, 1), (3, 1) … … (4, 4). Data can be transferred between the core with the original address (1, 1) and the core with the original address (2, 1), and data can also be transferred between the core with the original address (1, 1) and the core with the original address (1, 2).
The method for updating the core address in the embodiment of the disclosure specifically comprises the following steps:
S101, updating the original address of at least part of cores into an updated address according to a preset size; the arrangement mode of the update addresses of the cores is the same as the arrangement mode of the original addresses of the cores, the preset size is the size of an array formed by the update addresses of the cores, and at least part of the cores have no update addresses.
The original address of the core and the update address of the core are arranged according to a preset arrangement mode, the array formed by the original address and the array formed by the update address have certain sizes, and the original address of at least part of the core can be updated into the update address according to the preset size, so that the size of the array formed by the update address is consistent with the preset size.
Wherein, the term "all arranged according to a preset arrangement mode" means that the original address of the core and the update address of the core form an array in the same mode, for example, all form an array consisting of rows and columns; but the size of the array of the original addresses of the cores is not the same as the size of the array of the updated addresses of the cores.
Where "size" refers to the number of core addresses that the array includes in each topological direction. The predetermined size is required to match the compiled arrangement layout of the predetermined core. Before the chip leaves the factory, compiling is carried out aiming at various types of to-be-processed problems and a given core compiling arrangement layout is obtained, so that tasks obtained by compiling the to-be-processed problems can be mapped to cores according to the core compiling arrangement layout, therefore, the chip has a preset core compiling arrangement layout, a plurality of core compiling arrangement layouts obtained by compiling a certain type of to-be-processed problems can be obtained, a plurality of core compiling arrangement layouts obtained by compiling a plurality of types of to-be-processed problems can be obtained, but the core compiling arrangement layout is often smaller than an actual core original address arrangement layout, and the aim of re-compiling the to-be-processed problems when a subsequent failure core occurs is avoided as much as possible.
In addition, the preset size is related to the allowable failure rate of the core in the chip. After the original address of at least part of the cores is updated to the updated address according to the preset size, the cores actually executing the algorithm are all cores in the updated address array, and if the number of the cores capable of executing the algorithm is too small, the overall computing power of the chip is affected. For example, if the total number of cores is 100 and the allowable failure rate is 20%, when the addresses are arranged in a matrix form, the preset size may be 8X10 (representing 8 rows and 10 columns, or representing 10 rows and 8 columns), and the compiling arrangement layout of the cores is also the same.
An array of addresses of cores has only relative dimensions in the topological direction inside the array, and no absolute dimensions, e.g. when the addresses are arranged in a matrix, the dimensions in the row direction and the dimensions in the column direction are only relatively equivalent, and the dimensions of 3 rows and 4 columns are substantially equivalent to the dimensions of 4 rows and 3 columns. Therefore, the preset size is not an absolute size, and when the original address of the core is updated, the size of the array formed by the updated address is only required to be matched with the preset size in a certain direction.
Typically, the preset size is set smaller than the size of the array constituted by the original addresses of the cores, and therefore, in order to make the size of the array constituted by the updated addresses coincide with the preset size, the original addresses of part of the cores, that is, the part of the cores having no updated address, may not be updated.
Referring to fig. 12 and 13, taking the preset size of 3X4 as an example, if the array formed by the original addresses of the cores is 4 rows and 4 columns as shown in fig. 12, the original addresses of part of the cores can be updated to the updated addresses according to the preset size so that the array formed by the updated addresses is 3 rows and 4 columns as shown in fig. 13.
In fig. 12 and 13, a non-faulty core is indicated by a solid circle, and a faulty core is indicated by a hollow circle. In fig. 13, when two brackets for indicating addresses are provided above the non-faulty core, the upper address of the two addresses is the original address, and the lower address is the updated address (if the original address is the same as the updated address, only one bracket is used for indicating). It can be seen that the original address array shown in fig. 12 has a failed core, the update address array shown in fig. 13 has no failed core, which indicates that the failed core has no update address, and the original address of a part of non-failed cores is different from the update address.
It should be understood that fig. 13 only shows an array of updated addresses of all cores having updated addresses after updating the original addresses of at least some cores, and does not represent that the actual number of cores is reduced after updating the original addresses of at least some cores, i.e. the entity structure of all cores is still unchanged after updating the original addresses of at least some cores.
It should be noted that, the update address is not necessarily capable of transmitting data between two cores adjacent in the row direction (or column direction) of the matrix shown in fig. 13, because data still needs to be transmitted between two cores adjacent in the row direction (or column direction) of the matrix shown in fig. 12, and the update address is not necessarily capable of being adjacent in the row direction (or column direction) of the matrix shown in fig. 13, and there may be an original address between the original addresses of the two cores that is not updated to the update address.
Before the chip leaves the factory, the method for updating the core address updates the original address of at least part of the cores into the updated address according to the preset size, so that the size of an array formed by the updated address of the cores is consistent with the preset size, namely the arrangement layout of the updated address is matched with the compiling arrangement layout of the cores, and the fact that each core corresponding to each updated address in the array formed by the updated address of the core can execute an algorithm is ensured, and data can still be transmitted according to the original address arrangement condition of the cores.
Under the condition that no fault core exists, updating the original address of at least part of cores into updated addresses according to a preset size, and reserving at least part of cores without updated addresses as backup (backup), which is equivalent to providing a certain allowable fault amount and avoiding the need of recompilation when the fault core exists; under the condition that a fault core occurs, the original address of at least part of non-fault cores is updated to be an updated address according to the preset size, the whole chip is not required to be recompiled, the whole chip is not required to be directly replaced, the chip can still work normally, and the maintenance cost required when the fault core occurs in the multi-core chip is saved.
Fig. 2 is a flowchart of another method for updating a core address according to an embodiment of the present disclosure.
Referring to fig. 2, an embodiment of the present disclosure provides a core address update method, including:
s201, determining a preset topological direction and a deleting amount thereof according to a preset size.
The preset size is the size of an array formed by the update addresses of the cores.
Because the preset size is smaller than the size of the array formed by the original addresses of the cores, part of the original addresses of the cores need to be deleted, so that the original addresses of the rest cores can be updated to updated addresses to form the array conforming to the preset size. An appropriate topology direction can be selected from the topology directions according to a preset size and the deletion amount can be determined.
The preset topology direction is related to the arrangement manner, for example, when the addresses of the cores are arranged in a matrix form, the preset topology direction may be a row direction or a column direction (corresponding to an X-axis direction or a Y-axis direction, but the row direction is not particularly limited to the X-axis direction or the Y-axis direction), and when the addresses of the cores are arranged in a three-dimensional arrangement manner, the preset topology direction may be the X-axis direction or the Y-axis direction or the Z-axis direction.
S202, determining the deleting quantity of cores as deleting cores in each row of cores arranged along the preset topological direction.
After determining the preset topology direction and the deletion amount thereof, part of cores (original addresses) can be deleted according to the preset topology direction and the deletion amount thereof, and first, the deletion amount of cores in each row of cores arranged along the preset topology direction can be determined as cores to be deleted.
It should be noted that, when the addresses of the cores are arranged in the three-dimensional arrangement manner, the cores that are arranged along the preset topology direction and are to be a plurality of planes perpendicular to the preset topology direction, that is, the multi-layer cores, each of the above rows of cores may also include a layer of cores, and at this time, it is determined that the deleted number of cores is the deleted core in each layer of cores arranged along the preset topology direction.
S203, updating the original address of the non-deleted core to an updated address, wherein the deleted core has no updated address.
The arrangement mode of the update addresses of the cores is the same as the arrangement mode of the original addresses of the cores, and no update address is deleted from the cores.
After determining the deleted core, other cores in each row (layer) of cores arranged along the preset topological direction are non-deleted cores, updating the original address of the non-deleted cores only, and arranging the updated addresses of the cores according to the arrangement mode same as the original address.
After updating the original address of the non-deleted core, the updated address of the core may be the same as or different from the original address of the core.
Fig. 3 is a flowchart of yet another method for updating a core address according to an embodiment of the present disclosure.
Referring to fig. 3, an embodiment of the present disclosure provides a core address update method, including:
S301, determining a preset topological direction and a deleting amount thereof according to a preset size.
The preset size is the size of an array formed by the update addresses of the cores.
S302, when no fault core exists in any row of cores arranged along the preset topological direction, determining the deletion quantity of cores positioned at the preset position in the row of cores as deletion cores.
In the case where there is no failed core in any of the rows of cores arranged in the preset topological direction, cores located at the predetermined positions in each row of cores may be designated as deleted cores, and the number of cores designated as deleted cores is equal to the deletion amount.
S303, updating the original address of the non-deleted core to an updated address, wherein the deleted core has no updated address.
The arrangement mode of the update addresses of the cores is the same as the arrangement mode of the original addresses of the cores, and no update address is deleted from the cores.
In some embodiments, when there is no failed core in any row of cores arranged along the preset topology direction, determining the last deleted number of cores in the row of cores along the preset topology direction as deleted cores.
When any row of cores arranged along the preset topological direction has no fault core, determining the last deleted quantity of cores in the row of cores along the preset topological direction as deleted cores, and updating the original addresses of the non-deleted cores in the row of cores, wherein the updated addresses of all the non-deleted cores in the row of cores can be the same as the original addresses, namely the updated addresses are unchanged.
Referring to fig. 14, an array of original addresses of cores is shown in fig. 14, in which non-faulty cores are indicated by filled circles and faulty cores are indicated by open circles. Taking a preset topological direction as a row direction and a deletion amount in the row direction as 1 as an example, when no fault core exists in the first row core and the third row core in the column direction in each row of cores arranged in the row direction, the last core in the row direction (namely, the core with the original address of (4, 1) and the core with the original address of (4, 3) in the two rows of cores) can be determined as a deletion core, and six cores with the original addresses of (1, 1), (2, 1), (3, 1), (1, 3), (2, 3) in the two rows of cores are non-deletion cores, and the update addresses of the six non-deletion cores can be the same as the original addresses of (1, 1), (2, 1), (3), (2, 3) and (1, 3).
Fig. 4 is a flowchart of another method for updating a core address according to an embodiment of the present disclosure.
Referring to fig. 4, an embodiment of the present disclosure provides a core address update method, including:
s401, determining a preset topological direction and a deleting amount thereof according to a preset size.
The preset size is the size of an array formed by the update addresses of the cores.
S402, when a fault core exists in any row of cores arranged along a preset topological direction, determining that a deletion amount of cores in the row of cores are deletion cores, and determining that all the fault cores in the row are deletion cores.
If the arrangement layout of the updated address is matched with the compiling arrangement layout of the cores so as to ensure that each core in the updated address array can execute the algorithm, the original address of the failed core cannot be updated, and therefore, when any row of cores arranged along the preset topological direction has failed cores, all the failed cores in each row of cores can be determined to be deleted cores.
It should be noted that, the deletion amount of the preset topology direction may be the number of cores that are determined according to the preset size and are allowed to be deleted in any row of cores arranged along the preset topology direction, and if the number of failed cores in any row of cores arranged along the preset topology direction exceeds the deletion amount of the preset topology direction, the core address cannot be updated, and the chip may need to be invalidated.
S403, updating the original address of the non-deleted core to an updated address, wherein the deleted core has no updated address.
The arrangement mode of the update addresses of the cores is the same as the arrangement mode of the original addresses of the cores, and no update address is deleted from the cores.
In some embodiments, if there are failed cores in any row of cores arranged along the preset topology direction, when the number of failed cores in the row of cores is n smaller than the deletion amount, determining all failed cores in the row of cores as deleted cores, and determining the last n non-failed cores in the row of cores along the preset topology direction as deleted cores.
When any one of the cores arranged in the preset topological direction has a fault core and the number of the fault cores in the row is smaller than the deleting amount by n, all the fault cores in the row are determined to be deleting cores, and the last n non-fault cores in the row along the preset topological direction are determined to be deleting cores, wherein the cores except for the deleting cores in the row are all non-deleting cores. When the original address of the non-deleted core in the core row is updated, the updated address of the non-deleted core may be the same as the original address or may be different from the original address.
Referring to fig. 15, an array of original addresses of cores is shown in fig. 15, wherein a solid circle represents a non-faulty core and a hollow circle represents a faulty core. Taking the preset topological direction as the row direction and the deleting amount in the row direction as 2 as an example, only for the second row of cores in the row direction in each row of cores arranged in the row direction, when a faulty core exists in the row of cores, the faulty core is the second core in the row direction in the row of cores (namely, the core with the original address of (2, 2)), the number of faulty cores in the row of cores is 1 less than the deleting amount, the core with the original address of (2, 2) can be determined as the deleting core, and the last core in the row direction in the row of cores (namely, the core with the original address of (4, 2) can be determined as the deleting core. When updating the original address of the non-deleted core in the row core, the original address (1, 2) may be updated to the updated address (1, 2), and the original address (3, 2) may be updated to the updated address (2, 2).
Fig. 5 is a flowchart of another method for updating a core address according to an embodiment of the present disclosure.
Referring to fig. 5, an embodiment of the present disclosure provides a core address update method, including:
S501, determining the maximum fault nucleus number of each topological direction; the maximum number of failed cores is the maximum of the number of failed cores that are present in all the row cores that are aligned in the corresponding topological direction.
After the chip is initialized, the original address of the fault core in the chip can be obtained, and the maximum fault core number in each topological direction can be determined according to the original address of the fault core. The number of the fault cores included in each row of cores may be the same or different in all the row of cores arranged along a certain topological direction, and the maximum value of the number of the fault cores is the maximum fault core number of the topological direction.
Referring to fig. 16, an array of original addresses of cores is shown in fig. 16, wherein a solid circle represents a non-faulty core and a hollow circle represents a faulty core. It can be seen that, the four cores with original addresses (3, 1), (2, 2), (4, 3) and (3, 4) are all failure cores, and in four rows of cores arranged along the row direction, one failure core is in each row of cores, and the maximum failure core number in the row direction is 1; and among the four rows of cores arranged in the column direction, there is no failed core in the core of the first row in the row direction, one failed core in the core of the second row in the row direction and one failed core in the core of the fourth row, and two failed cores in the core of the third row in the row direction, the maximum number of failed cores in the column direction is 2.
S502, determining the allowable deletion amount of each topological direction when different topological directions are taken as preset topological directions according to the preset size.
The preset size is the size of an array formed by the update addresses of the cores. If the updated addresses of the cores are to be able to form an array conforming to the preset size, then the number of (original addresses of) cores to be deleted in each row of cores arranged in the corresponding topological direction, i.e. the allowed deletion amount, needs to be determined when the cores in the original address array are deleted in different topological directions.
Assuming that the original address of the core forms a matrix array of 4 rows and 4 columns and the preset size is 3X4, as described above, the size of 3 rows and 4 columns and the size of 4 rows and 3 columns are substantially equivalent in the address array, it is feasible to use the row direction as the preset topology direction or the column direction as the preset topology direction. When the row direction is the preset topology direction, the allowable deletion amount in the row direction is 1, and the allowable deletion amount in the column direction is 0. When the column direction is the preset topology direction, the allowable deletion amount in the row direction is 0, and the allowable deletion amount in the column direction is 1. Whether a core (original address) is deleted in each row of cores arranged in the row direction to obtain a 4-row 3-column update address array or a core (original address) is deleted in each row of cores arranged in the column-row direction to obtain a 3-row 4-column update address array, the update address array has a size of 3X4 in practice.
S503, determining a part of topological directions as preset topological directions according to the maximum fault core number and the allowable deletion amount, and determining the allowable deletion amount of the corresponding topological directions as the deletion amount of the preset topological directions; the maximum fault nucleus number of any preset topological direction does not exceed the deletion amount.
If the maximum fault core number in a certain topological direction exceeds the allowable deletion amount, after deleting (the original address of) all fault cores, the update address of the non-deleted core is insufficient to form an array conforming to the preset size. Thus, in order to enable the updated address of the core to form an array conforming to the preset size, it is also necessary to satisfy the condition: the maximum fault nucleus number of the preset topology direction does not exceed the allowable deletion amount.
The number of the topological directions of which the maximum fault core number is not more than the allowable deletion amount is possibly multiple, and any topological direction of which the maximum fault core number is not more than the allowable deletion amount is selected as a preset topological direction. After determining the preset topology direction, the allowable deletion amount of the preset topology direction can be determined as the deletion amount of the core, and the deletion amount of the preset topology direction is the number of cores to be deleted in each row of cores arranged along the preset topology direction.
Of course, when the number of topology directions in which the maximum number of failure cores does not exceed the allowable deletion amount is plural, one topology direction in which the allowable deletion amount is the smallest may be selected from the plural topology directions as a preset topology direction.
S504, determining the deleting quantity of cores as deleting cores in each row of cores arranged along the preset topological direction.
S505, the original address of the non-deleted core is updated to be an updated address, and the deleted core has no updated address.
In some embodiments, the preset arrangement may be a two-dimensional matrix, and then one topology direction is determined as a preset topology direction from a row topology direction and a column topology direction of the two-dimensional matrix.
If the original address and the updated address of the core are arranged in a two-dimensional matrix, the topology direction of the two-dimensional matrix comprises a row topology direction and a column topology direction, and one topology direction needs to be selected from the row topology direction and the column topology direction to serve as a preset topology direction.
Fig. 6 is a flowchart of a mapping method provided in an embodiment of the present disclosure.
Referring to fig. 6, an embodiment of the present disclosure provides a mapping method for a chip whose core address is updated according to the aforementioned core address updating method.
The mapping method of the embodiment of the disclosure specifically comprises the following steps:
s601, mapping a plurality of tasks to the cores with the updated addresses according to the arrangement situation of the updated addresses of the cores in the chip.
After the chip updates the address according to the above-described core address update method, a plurality of tasks may be mapped to cores each having an update address according to an array of update addresses of cores in the chip, respectively. The cores with the updated addresses can execute an algorithm, and after a plurality of tasks are mapped to the cores with the updated addresses, each core can process the tasks respectively and work cooperatively normally.
Fig. 7 is a flowchart of another mapping method provided in an embodiment of the present disclosure.
Referring to fig. 7, an embodiment of the present disclosure provides a mapping method for a chip with a core address updated according to the aforementioned core address updating method.
The mapping method of the embodiment of the disclosure specifically comprises the following steps:
s701, compiling the problem to be processed according to a preset size to obtain a plurality of tasks.
The size of the array formed by the update addresses of the cores is preset, and the array is matched with the compiling arrangement layout of the cores. When compiling the problem to be processed (or an algorithm capable of solving the problem to be processed), the problem to be processed can be compiled into a plurality of tasks according to a preset size, so that the tasks can be executed by cores in the update address array.
S702, mapping a plurality of tasks to the cores with the updated addresses according to the arrangement situation of the updated addresses of the cores in the chip.
The cores with the updated addresses can execute an algorithm, and after a plurality of tasks are mapped to the cores with the updated addresses, each core can process the tasks respectively and work cooperatively normally.
Fig. 8 is a flowchart of a data transmission method according to an embodiment of the present disclosure.
Referring to fig. 8, an embodiment of the present disclosure provides a data transmission method for a chip with a core address updated according to the aforementioned core address update method.
The data transmission method of the embodiment of the disclosure specifically comprises the following steps:
S801, acquiring data, wherein the data comprises a destination core update address.
After the original address of at least part of the cores in the chip is updated, the arrangement layout of the updated address of the cores is matched with the compiling layout of the preset cores, the cores with the updated address can execute an algorithm, and tasks are mapped to the cores with the updated address, so that when data are transmitted, the target cores are also the cores with the updated address, and the target core address carried by the data can be the target core updated address.
S802, at least according to the update address of the destination core, transmitting the data to the destination core.
At least part of the cores have the update address and the original address at the same time, at least part of the cores only have the original address but not the update address, all the cores have normal routing functions, and data can be transmitted to the target core at least according to the update address of the target core.
Fig. 9 is a flowchart of another data transmission method according to an embodiment of the present disclosure.
Referring to fig. 9, an embodiment of the present disclosure provides a data transmission method for a chip with a core address updated according to the aforementioned core address updating method.
The data transmission method of the embodiment of the disclosure specifically comprises the following steps:
S901, acquiring data, wherein the data comprises a destination core update address.
S902, transmitting data to a target core according to the corresponding relation between the original address and the update address of at least part of cores, the original address of at least part of cores and the update address of the target core.
After the original address of at least part of the cores in the chip is updated, each core can store the update address of the core adjacent to the core in each direction and having the update address, each core has the original address, and the core with the updated original address also has the update address, so that when data is transmitted, whether the data reaches the target core can be judged according to the update address, and the actual routing can be carried out according to the original address.
Specifically, the current core may determine whether the current core is a target core according to the update address of the current core, if not, the current core may select an update address closest to the update address of the target core in a certain topology direction from the update addresses of the cores adjacent to the current core in the topology directions stored by the current core, and transmit data to the core corresponding to the update address according to the original address of the current core, and the core corresponding to the update address continues to transmit data.
Referring to fig. 12 and 13, fig. 12 shows an array of the original addresses of the cores, and fig. 13 shows an array of the updated addresses of the cores. After updating the original address of at least part of the cores to the update address according to the preset size, four cores of the original addresses (4, 1), (2, 2), (4, 3) and (3, 4) shown in fig. 12 have no update address, and at this time, the core of the original address (2, 2) stores the update address of the core on the right side in the row direction as (2, 2) and the core of the original address (1, 2) stores the update address of the core on the right side in the row direction as (2, 2) because the core of the original address (2, 2) has no update address, the core having the update address on the right side of the core of the original address (1, 2) is the core of the original address (3, 2) and the core of the original address (3, 2) has the update address (2, 2).
Assuming that the core with the original address (2, 3) acquires data and the update address of the target core carried by the data is (3, 4), at this time, the core with the original address (2, 3) stores the update address of the left core with the row direction as (1, 3), the update address of the right core with the row direction as (3, 3) stores the update address of the upper core with the column direction as (2, 2), the update address of the upper core with the column direction as (2, 4) stores the update address of the upper core with the column direction as (2, 4), if the data is preferentially selected according to the row direction, the update address closest to the update address of the target core in the row direction is (3, 3), the core with the original address as (2, 3) can select the core with the update address as (3, 3), and the data is transmitted to the core with the update address as (3, 3) at first, and then the core with the update address as (3, 3) continues to transmit the data.
Fig. 10 is a flowchart of another data transmission method according to an embodiment of the present disclosure.
Referring to fig. 10, an embodiment of the present disclosure provides a data transmission method for a chip with a core address updated according to the aforementioned core address updating method.
The data transmission method of the embodiment of the disclosure specifically comprises the following steps:
s1001, acquiring data, wherein the data comprises a destination core update address.
S1002, determining a destination core original address corresponding to the destination core update address.
After the original address of at least part of cores in the chip is updated, the routing address translation table can be maintained in each core, and the routing address translation table can also be maintained in the central control core. The corresponding relationship between the original address and the updated address of the core may be stored in the routing address translation table, so that the core may directly query the local routing address translation table to determine the original address corresponding to a certain updated address, or may request to the central control core to determine the original address corresponding to a certain updated address, which is not specifically limited in the embodiment of the present disclosure.
In the routing address translation table, there may be a part of cores whose update addresses are the same as their original addresses, or a part of cores whose update addresses are different from their original addresses, and a part of cores having no update address, whose update addresses may be shown as null.
S1003, transmitting the data to the target core according to the original address of each core.
Whether the core has an update address or not, the core has a routing function, so after determining the original address of the target core corresponding to the update address of the target core, the core can transmit data to the original address of the target core according to the original address of each core.
Fig. 17 is a block diagram of a core address update apparatus according to an embodiment of the present disclosure.
Referring to fig. 17, an embodiment of the present disclosure provides a core address updating device 170, configured to update a core address of a chip, where the chip includes a plurality of cores, original addresses of the plurality of cores are arranged in a preset arrangement manner, and the core address updating device 170 includes:
An updating module 1701, configured to update an original address of at least a part of the cores to an updated address according to a preset size; the arrangement mode of the update addresses of the cores is the same as the arrangement mode of the original addresses of the cores, the preset size is the size of an array formed by the update addresses of the cores, and at least part of the cores have no update addresses.
Fig. 18 is a block diagram of a mapping apparatus according to an embodiment of the present disclosure.
Referring to fig. 18, an embodiment of the present disclosure provides a mapping apparatus 180 for updating a chip of a core address according to the aforementioned core address updating method, where the mapping apparatus 180 includes:
the mapping module 1801 is configured to map a plurality of tasks to a core with an update address according to an arrangement situation of update addresses of cores in a chip.
In addition, the embodiment of the disclosure also provides a chip for realizing at least one of the following methods:
The method for updating the core address is as described above;
A mapping method as described above;
Such as the data transmission method described above.
Furthermore, the disclosed embodiments also provide a computer readable medium having a computer program stored thereon, wherein the computer program, when executed by a processing core, implements at least one of the following methods:
The method for updating the core address is as described above;
A mapping method as described above;
Such as the data transmission method described above.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, R11M, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, it will be apparent to one skilled in the art that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments unless explicitly stated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (16)
1. The core address updating method is used for updating the core address of a chip, wherein the chip comprises a plurality of cores, and the original addresses of the cores are arranged according to a preset arrangement mode; the method comprises the following steps:
Updating the original address of at least part of cores into an updated address according to a preset size; the arrangement mode of the update addresses of the cores is the same as the arrangement mode of the original addresses of the cores, the preset size is the size of an array formed by the update addresses of the cores, and at least part of the cores have no update addresses;
the updating the original address of at least part of the cores into updated addresses according to the preset size comprises the following steps:
Determining a preset topological direction and a deletion amount thereof according to the preset size;
determining a deletion amount of cores as deletion cores in each row of cores arranged along a preset topological direction;
Updating the original address of the non-deleted core into an updated address, wherein the deleted core has no updated address.
2. The method for updating a core address according to claim 1, wherein the determining that the deleted number of cores is a deleted core in each row of cores arranged in the predetermined topology direction includes:
When any row of cores arranged along the preset topological direction has no fault core, determining the deletion quantity of cores positioned at the preset position in the row of cores as deletion cores.
3. The core address updating method according to claim 2, wherein the deleted number of cores located at the predetermined position in the row of cores is a last deleted number of cores in the row of cores along a predetermined topology direction.
4. The method for updating a core address according to claim 1, wherein the determining that the deleted number of cores is a deleted core in each row of cores arranged in the predetermined topology direction includes:
when any row of cores arranged along the preset topological direction has a fault core, determining that a deletion amount of cores in the row of cores are deletion cores, and determining that all the fault cores in the row are deletion cores.
5. The method for updating a core address according to claim 4, wherein when the number of failed cores in the row of cores is n smaller than the deletion amount, the determining that the deletion amount of cores in the row of cores is a deletion core includes:
And determining all the fault cores in the row of cores as deletion cores, and determining the last n non-fault cores in the row of cores along the preset topological direction as deletion cores.
6. The method for updating a core address according to claim 1, wherein said determining a preset topology direction and a deletion amount thereof according to the preset size comprises:
Determining the maximum fault core number of each topological direction; the maximum number of the fault cores is the maximum value of the number of the fault cores in all the row cores arranged along the corresponding topological direction;
determining the allowable deletion amount of each topological direction when different topological directions are taken as preset topological directions according to the preset size;
Determining part of topological directions as preset topological directions according to the maximum fault core number and the allowable deletion amount, and determining the allowable deletion amount of the corresponding topological directions as the deletion amount of the preset topological directions; the maximum fault nucleus number of any preset topological direction does not exceed the deletion amount.
7. The method of claim 6, wherein the predetermined arrangement is a two-dimensional matrix, and one topology direction is determined as a predetermined topology direction from row topology directions and column topology directions of the two-dimensional matrix.
8. A mapping method for a chip whose core address is updated according to the core address updating method of any one of claims 1 to 7, the mapping method comprising:
and mapping a plurality of tasks to the cores with the updated addresses according to the arrangement condition of the updated addresses of the cores in the chip.
9. The mapping method according to claim 8, wherein before the mapping of the plurality of tasks to the core having the update address according to the arrangement of update addresses of cores in the chip, the method further comprises:
And compiling the problem to be processed according to the preset size to obtain the tasks.
10. A data transmission method for a chip whose core address is updated according to the core address updating method of any one of claims 1 to 7, the data transmission method comprising:
acquiring data, wherein the data comprises a destination core update address;
And transmitting the data to the target core at least according to the update address of the target core.
11. The data transmission method according to claim 10, wherein the transmitting the data to the destination core based at least on the destination core update address includes:
And transmitting the data to the target core according to the corresponding relation between the original address and the updated address of at least part of the cores, the original address of at least part of the cores and the updated address of the target core.
12. The data transmission method according to claim 10, wherein the transmitting the data to the destination core based at least on the destination core update address includes:
Determining a destination core original address corresponding to the destination core update address;
And transmitting the data to the target core according to the original address of each core.
13. A core address updating device, configured to update a core address of a chip, where the chip includes a plurality of cores, and original addresses of the plurality of cores are arranged according to a preset arrangement manner, where the core address updating device includes:
The updating module is used for updating the original address of at least part of the cores into an updated address according to the preset size; the arrangement mode of the update addresses of the cores is the same as the arrangement mode of the original addresses of the cores, the preset size is the size of an array formed by the update addresses of the cores, and at least part of the cores have no update addresses;
The updating module is specifically configured to determine a preset topology direction and a deletion amount thereof according to the preset size; determining a deletion amount of cores as deletion cores in each row of cores arranged along a preset topological direction; updating the original address of the non-deleted core into an updated address, wherein the deleted core has no updated address.
14. A mapping apparatus for a chip whose core address is updated according to the core address updating method of any one of claims 1 to 7, comprising:
And the mapping module is used for mapping a plurality of tasks to the cores with the updated addresses according to the arrangement condition of the updated addresses of the cores in the chip.
15. A chip comprising a plurality of cores, the chip for implementing at least one of the following methods:
The core address update method of any of claims 1-7;
The mapping method of any of claims 8-9;
a data transmission method according to any of claims 10-12.
16. A computer readable medium having stored thereon a computer program, wherein the computer program when executed by a processing core implements at least one of the following methods:
The core address update method of any of claims 1-7;
The mapping method of any of claims 8-9;
a data transmission method according to any of claims 10-12.
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