CN113010353A - Nuclear address updating method, mapping method, data transmission method and device, and chip - Google Patents

Nuclear address updating method, mapping method, data transmission method and device, and chip Download PDF

Info

Publication number
CN113010353A
CN113010353A CN202110302080.6A CN202110302080A CN113010353A CN 113010353 A CN113010353 A CN 113010353A CN 202110302080 A CN202110302080 A CN 202110302080A CN 113010353 A CN113010353 A CN 113010353A
Authority
CN
China
Prior art keywords
core
cores
address
updating
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110302080.6A
Other languages
Chinese (zh)
Other versions
CN113010353B (en
Inventor
何伟
沈杨书
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Lynxi Technology Co Ltd
Original Assignee
Beijing Lynxi Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Lynxi Technology Co Ltd filed Critical Beijing Lynxi Technology Co Ltd
Priority to CN202110302080.6A priority Critical patent/CN113010353B/en
Publication of CN113010353A publication Critical patent/CN113010353A/en
Priority to PCT/CN2022/080104 priority patent/WO2022199390A1/en
Application granted granted Critical
Publication of CN113010353B publication Critical patent/CN113010353B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2035Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Hardware Redundancy (AREA)

Abstract

The present disclosure provides a core address updating method, which includes: updating original addresses of at least part of cores into updated addresses according to the preset size; the updating address arrangement mode of the core is the same as the original address arrangement mode of the core, the preset size is the size of an array formed by the updating addresses of the core, and at least part of the cores have no updating addresses. The maintenance cost of the multi-core chip is saved. The disclosure also provides a mapping method, a data transmission method, a kernel address updating device, a mapping device, a chip and a computer readable medium.

Description

Nuclear address updating method, mapping method, data transmission method and device, and chip
Technical Field
The present disclosure relates to the field of artificial intelligence chip technologies, and in particular, to a core address updating method, a mapping method, a data transmission method, a core address updating apparatus, a mapping apparatus, a chip, and a computer-readable medium.
Background
A chip (e.g., an artificial intelligence chip) may be composed of one or more processors, and one processor usually integrates multiple complete computing engines (cores), and cores within one processor or among multiple processors may cooperate.
When a fault core occurs in the chip, although the fault core cannot execute the algorithm, the probability of route damage is low. Therefore, these faulty cores still have a routing function although they cannot perform algorithm mapping. At present, when the above fault occurs, because the faulty core cannot execute the algorithm, the whole chip may need to be remapped so that the algorithm is mapped onto the core capable of executing the algorithm, or the normal chip is directly used to replace the whole chip, so that the whole chip is wasted, and the cost is high.
Disclosure of Invention
The disclosure provides a core address updating method, a mapping method, a data transmission method, a core address updating device, a mapping device, a chip and a computer readable medium.
In a first aspect, the present disclosure provides a core address updating method, including:
updating original addresses of at least part of cores into updated addresses according to the preset size; the updating address arrangement mode of the core is the same as the original address arrangement mode of the core, the preset size is the size of an array formed by the updating addresses of the core, and at least part of the cores have no updating addresses.
In some embodiments, the updating the original address of at least part of the cores to the updated address according to the preset size includes:
determining a preset topological direction and a deletion amount thereof according to the preset size;
determining a deleted core as a deleted core in each row of cores arranged along a preset topological direction;
and updating the original address of the non-deleted core into an updated address, wherein the deleted core has no updated address.
In some embodiments, the determining, in each row of cores arranged along the preset topological direction, a deleted number of cores as a deleted core includes:
when no fault core exists in any one row of cores arranged along the preset topological direction, determining the deleted cores in the row of cores at the preset positions as deleted cores.
In some embodiments, the deleted number of cores in the predetermined position in the row of cores is the last deleted number of cores in the row of cores along the preset topological direction.
In some embodiments, the determining, in each row of cores arranged along the preset topological direction, a deleted number of cores as a deleted core includes:
when a fault core exists in any one row of cores arranged along the preset topological direction, determining that the deleted cores in the row of cores are deleted cores, and determining all the fault cores in the row of cores to be deleted cores.
In some embodiments, when the number of faulty cores in the row of cores is less than the deletion amount by n, the determining that the deletion amount cores in the row of cores are deletion cores includes:
and determining all fault cores in the row of cores as deleted cores, and determining the last n non-fault cores in the row of cores along the preset topological direction as deleted cores.
In some embodiments, the determining a preset topological direction and a deletion amount thereof according to the preset size includes:
determining the maximum fault kernel number of each topological direction; the maximum fault core number is the maximum value of the number of fault cores in all the rows of cores arranged along the corresponding topological direction;
determining the allowed deletion amount of each topological direction when different topological directions are taken as the preset topological directions according to the preset size;
determining part of the topological directions as preset topological directions according to the maximum fault kernel number and the allowed deletion amount, and determining the allowed deletion amount of the corresponding topological directions as the deletion amount of the preset topological directions; the maximum fault core number in any preset topological direction does not exceed the deletion amount.
In some embodiments, the preset arrangement mode is a two-dimensional matrix, and one topological direction is determined as a preset topological direction from a row topological direction and a column topological direction of the two-dimensional matrix.
In a second aspect, the present disclosure provides a mapping method for updating a chip with a core address according to the foregoing core address updating method, where the mapping method includes:
and mapping a plurality of tasks to the cores with the updated addresses according to the arrangement condition of the updated addresses of the cores in the chip.
In some embodiments, before the mapping the plurality of tasks to the cores having the updated addresses according to the arrangement condition of the updated addresses of the cores in the chip, the method further includes:
and compiling the problem to be processed according to the preset size to obtain the plurality of tasks.
In a third aspect, the present disclosure provides a data transmission method for a chip whose core address is updated according to the foregoing core address updating method, including:
acquiring data, wherein the data comprises a target core updating address;
and updating the address according to at least the destination core, and transmitting the data to the destination core.
In some embodiments, the updating the address according to at least the destination core, and the transmitting the data to the destination core includes:
and transmitting the data to a target core according to the corresponding relation between the original address and the update address of at least part of cores, the original address of at least part of cores and the update address of the target core.
In some embodiments, the updating the address according to at least the destination core, and the transmitting the data to the destination core includes:
determining a destination core original address corresponding to the destination core update address;
and transmitting the data to a target core according to the original address of each core.
In a fourth aspect, the present disclosure provides a core address updating apparatus, configured to update a core address of a chip, where the chip includes a plurality of cores, and original addresses of the plurality of cores are arranged according to a preset arrangement manner, and the core address updating apparatus includes:
the updating module is used for updating the original addresses of at least part of cores into updated addresses according to the preset size; the updating address arrangement mode of the core is the same as the original address arrangement mode of the core, the preset size is the size of an array formed by the updating addresses of the core, and at least part of the cores have no updating addresses.
In a fifth aspect, the present disclosure provides a mapping apparatus, configured to update a chip with a core address according to the foregoing core address updating method, where the mapping apparatus includes:
and the mapping module is used for mapping the tasks to the cores with the updated addresses according to the arrangement condition of the updated addresses of the cores in the chip.
In a sixth aspect, the present disclosure provides a chip comprising a plurality of cores, the chip being configured to implement at least one of the following methods:
the core address update method as described above;
the mapping method as described above;
such as the aforementioned data transmission method.
In a seventh aspect, the present disclosure provides a computer readable medium having a computer program stored thereon, wherein the computer program, when executed by a processing core, implements at least one of the following methods:
the core address update method as described above;
the mapping method as described above;
such as the aforementioned data transmission method.
According to the core address updating method, the core address mapping method, the core address data transmission method, the core address updating device, the core mapping device, the core chip and the computer readable medium, before the chip leaves a factory, the original addresses of at least part of the cores are updated into the updated addresses according to the preset size, so that the size of an array formed by the updated addresses of the cores is consistent with the preset size, namely the arrangement layout of the updated addresses is matched with the compiling arrangement layout of the core, the core corresponding to each updated address in the array formed by the updated addresses of the cores can execute the algorithm, and data can still be transmitted according to the arrangement condition of the original addresses of the cores. Under the condition that no fault core exists, the original addresses of at least part of cores are updated to update addresses according to the preset size, and at least part of cores without update addresses can be reserved for backing up (backup), which is equivalent to providing a certain allowable fault amount and avoiding the need of recompilation when the fault core occurs; under the condition of a fault core, the original address of at least part of non-fault cores is updated to be the updated address according to the preset size, the whole chip is not required to be recompiled, the whole chip is not required to be directly replaced, the chip can still work normally, and the maintenance cost required when the fault core occurs in the multi-core chip is saved.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is a flowchart of a core address updating method according to an embodiment of the present disclosure;
fig. 2 is a flowchart of another core address updating method provided by the embodiment of the present disclosure;
fig. 3 is a flowchart of another core address updating method provided by the embodiment of the present disclosure;
FIG. 4 is a flowchart of another core address update method provided by an embodiment of the present disclosure;
fig. 5 is a flowchart of another core address updating method provided by the embodiment of the present disclosure;
fig. 6 is a flowchart of a mapping method provided by an embodiment of the present disclosure;
FIG. 7 is a flowchart of another mapping method provided by an embodiment of the present disclosure;
fig. 8 is a flowchart of a data transmission method provided by an embodiment of the present disclosure;
fig. 9 is a flowchart of another data transmission method provided by the embodiment of the present disclosure;
fig. 10 is a flowchart of another data transmission method provided by the embodiment of the present disclosure;
FIG. 11 is a diagram illustrating an arrangement of original addresses of cores according to an embodiment of the present disclosure;
FIG. 12 is a diagram illustrating an arrangement of original addresses of cores according to another embodiment of the present disclosure;
FIG. 13 is a diagram illustrating an arrangement of update addresses of cores according to an embodiment of the present disclosure;
FIG. 14 is a diagram illustrating an arrangement of original addresses of cores according to yet another embodiment of the present disclosure;
FIG. 15 is a diagram illustrating an arrangement of original addresses of cores according to another embodiment of the present disclosure;
FIG. 16 is a diagram illustrating an arrangement of original addresses of cores according to yet another embodiment of the present disclosure;
fig. 17 is a block diagram illustrating an address updating apparatus according to an embodiment of the present disclosure;
fig. 18 is a block diagram illustrating a mapping apparatus according to an embodiment of the disclosure.
Detailed Description
To facilitate a better understanding of the technical aspects of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, wherein various details of the embodiments of the present disclosure are included to facilitate an understanding, and they should be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a flowchart of a core address updating method according to an embodiment of the present disclosure.
Referring to fig. 1, an embodiment of the present disclosure provides a core address updating method, which is used for updating a core address of a chip.
The chip comprises a plurality of cores, and original addresses of the cores are arranged according to a preset arrangement mode.
Each core in the chip has an address (or ID), which can be abstracted into coordinates, and the original address is an original address that is not updated. The original addresses of the cores in the chip are arranged in a preset arrangement manner, for example, the original addresses may be arranged in a matrix form, and each original address is used as an element in the matrix, but specific contents of the matrix may be different, for example, the size of the matrix (the number of rows and columns of the matrix, that is, the number of original addresses in both the row direction and the column direction) may be different. The original addresses may transfer data between two cores that are adjacent in a row direction of the matrix or adjacent in a column direction of the matrix.
Note that the original addresses may be arranged in other arrangements such as a three-dimensional body, and each original address is a coordinate in the three-dimensional body, but the sizes of the three-dimensional bodies (the length, width, and height of the three-dimensional body, that is, the number of original addresses in the three directions of the X axis, the Y axis, and the Z axis) may be different.
Referring to fig. 11, taking 16 cores in total on a chip as an example, each circle represents one core, and the original addresses of the 16 cores are arranged in a matrix form, where the original addresses of the 16 cores are: (1, 1), (2, 1), (3, 1) … … (4, 4). Data can be transmitted between a core with an original address of (1, 1) and a core with an original address of (2, 1), and data can also be transmitted between a core with an original address of (1, 1) and a core with an original address of (1, 2).
The method for updating the core address in the embodiment of the present disclosure specifically includes:
s101, updating original addresses of at least part of cores into updated addresses according to a preset size; the updating address arrangement mode of the core is the same as the original address arrangement mode of the core, the preset size is the size of an array formed by the updating addresses of the core, and at least part of the cores have no updating addresses.
The original addresses of the cores and the updated addresses of the cores are arranged according to a preset arrangement mode, the array formed by the original addresses and the array formed by the updated addresses have a certain size, and at least part of the original addresses of the cores can be updated into the updated addresses according to the preset size, so that the size of the array formed by the updated addresses is consistent with the preset size.
The word "all arranged according to a preset arrangement mode" means that the original address of the core and the updated address of the core form an array in the same "mode", for example, the original address and the updated address both form an array composed of rows and columns; however, the size of the array of the original address of the core is different from the size of the array of the update address of the core.
Where "size" refers to the number of core addresses that the array includes in each topological direction. The predetermined size needs to match a predetermined compiling permutation layout of the cores. Before the chip leaves a factory, compiling is performed aiming at various types of problems to be processed, and a set core compiling arrangement layout is obtained, so that tasks obtained by compiling the problems to be processed can be mapped to each core according to the core compiling arrangement layout, the chip is provided with a preset core compiling arrangement layout, a plurality of core compiling arrangement layouts obtained by compiling a certain type of problems to be processed can be provided, a plurality of core compiling arrangement layouts obtained by compiling a plurality of types of problems to be processed can also be provided, but the core compiling arrangement layout is often smaller than an actual core original address arrangement layout, and the aim of avoiding the problem to be processed from being recompiled when a fault core occurs subsequently is achieved as far as possible.
In addition, the predetermined size has a certain relationship with the allowable failure rate of the core in the chip. After at least part of original addresses of the cores are updated to updated addresses according to the preset size, all the cores which actually execute the algorithm are the cores in the updated address array, and if the number of the cores which can execute the algorithm is too small, the overall calculation power of the chip is affected. For example, if the total number of cores is 100 and the allowable failure rate is 20%, when the addresses are arranged in a matrix form, the preset size may be 8 × 10 (representing 8 rows and 10 columns, or representing 10 rows and 8 columns), and the same is true for the compiled arrangement layout of the cores.
The array formed by the addresses of the cores has relative sizes in all topological directions only in the array, but has no absolute size, for example, when the addresses are arranged in a matrix form, the size in the row direction and the size in the column direction are only relative, and the size of 3 rows and 4 columns is substantially equivalent to the size of 4 rows and 3 columns. Therefore, the predetermined size is not an absolute size, and when the original address of the core is updated, it is only necessary to make the size of the array constituted by the updated address coincide with the predetermined size in a certain direction.
In general, a preset size is set to be smaller than the size of the array constituted by the original addresses of the cores, and therefore, in order to make the size of the array constituted by the update addresses coincide with the preset size, the original addresses of a part of the cores may not be updated, and the part of the cores also do not have the update addresses.
Referring to fig. 12 and 13, taking the preset size of 3X4 as an example, if the array of the original addresses of the cores is 4 rows and 4 columns as shown in fig. 12, the original addresses of some cores may be updated to the updated addresses according to the preset size so that the array of the updated addresses is 3 rows and 4 columns as shown in fig. 13.
In fig. 12 and 13, the non-failure core is indicated by a solid circle, and the failure core is indicated by an open circle. In fig. 13, when two brackets for indicating addresses are provided above the non-faulty core, the upper address of the two addresses is the original address, and the lower address is the updated address (if the original address is the same as the updated address, only one bracket is used for indicating the original address). It can be seen that the original address array shown in fig. 12 has a faulty core, and the updated address array shown in fig. 13 has no faulty core, which means that the faulty core has no updated address, and the original address of part of the non-faulty cores is different from the updated address.
It should be understood that fig. 13 only shows the array formed by the updated addresses of all the cores having the updated addresses after the original addresses of at least some of the cores are updated, and does not represent that the actual number of the cores is reduced after the original addresses of at least some of the cores are updated, that is, the physical structure of all the cores is still unchanged after the original addresses of at least some of the cores are updated.
It should be noted that the update address may not necessarily be able to transmit data between two cores adjacent to each other in the row direction (or the column direction) of the matrix shown in fig. 13, because data still needs to be transmitted between two cores adjacent to each other in the row direction (or the column direction) of the matrix shown in fig. 12, while the update address may not necessarily be adjacent to each other in the row direction (or the column direction) of the matrix shown in fig. 13, and there may be an original address that is not updated to the update address between the original addresses of the two cores.
By using the core address updating method of the embodiment of the disclosure, before the chip leaves factory, the original addresses of at least part of the cores are updated to the updated addresses according to the preset size, so that the size of the array formed by the updated addresses of the cores is consistent with the preset size, that is, the arrangement layout of the updated addresses is matched with the compiling arrangement layout of the cores, it is ensured that the core corresponding to each updated address in the array formed by the updated addresses of the cores can execute the algorithm, and the data can still be transmitted according to the arrangement condition of the original addresses of the cores.
Under the condition that no fault core exists, the original addresses of at least part of cores are updated to update addresses according to the preset size, and at least part of cores without update addresses can be reserved for backing up (backup), which is equivalent to providing a certain allowable fault amount and avoiding the need of recompilation when the fault core occurs; under the condition of a fault core, the original address of at least part of non-fault cores is updated to be the updated address according to the preset size, the whole chip is not required to be recompiled, the whole chip is not required to be directly replaced, the chip can still work normally, and the maintenance cost required when the fault core occurs in the multi-core chip is saved.
Fig. 2 is a flowchart of another core address updating method according to an embodiment of the present disclosure.
Referring to fig. 2, an embodiment of the present disclosure provides a core address updating method, where the core address updating method includes:
s201, determining a preset topological direction and a deletion amount according to a preset size.
The preset size is the size of an array formed by the update addresses of the cores.
Since the preset size is smaller than the size of the array formed by the original addresses of the cores, part of (the original addresses of) the cores need to be deleted, so that the original addresses of the rest of the cores can be updated to the updated addresses to form the array conforming to the preset size. An appropriate topological direction can be selected from the topological directions according to the preset size, and the deletion amount of the topological direction can be determined.
The preset topological direction is related to the arrangement, for example, when the addresses of the cores are arranged in a matrix form, the preset topological direction may be a row direction or a column direction (which is equivalent to an X-axis direction or a Y-axis direction, but the row direction is the X-axis direction or the Y-axis direction, which is not particularly limited), and when the addresses of the cores are arranged in a three-dimensional body arrangement, the preset topological direction may be the X-axis direction, the Y-axis direction, or the Z-axis direction.
S202, determining the deleted cores as deleted cores in each row of cores arranged along the preset topological direction.
After the preset topological direction and the deletion amount thereof are determined, part of (original addresses of) the cores may be deleted according to the preset topological direction and the deletion amount thereof, and first, the deletion amount of cores in each row of cores arranged along the preset topological direction may be determined as the cores to be deleted.
It should be noted that, when the addresses of the cores are arranged according to the arrangement manner of the three-dimensional body, the cores arranged in the preset topological direction should be multiple planar cores perpendicular to the preset topological direction, that is, multiple layers of cores, each layer of cores above may also include one layer of core, and at this time, a deleted number of cores should be determined as deleted cores in each layer of cores arranged in the preset topological direction.
S203, the original address of the non-deleted core is updated to be an updated address, and the deleted core has no updated address.
The updating address arrangement mode of the core is the same as the original address arrangement mode of the core, and no updating address exists in the deleting core.
After the cores are determined to be deleted, the other cores in each row (layer) of cores arranged along the preset topological direction are all non-deleted cores, only the original addresses of the non-deleted cores are updated, and the updated addresses of the cores are arranged according to the same arrangement mode as the original addresses.
After the original address of the non-deleted core is updated, the updated address of the core may be the same as or different from the original address of the core.
Fig. 3 is a flowchart of another core address updating method according to an embodiment of the present disclosure.
Referring to fig. 3, an embodiment of the present disclosure provides a core address updating method, where the core address updating method includes:
s301, determining a preset topological direction and a deletion amount according to a preset size.
The preset size is the size of an array formed by the update addresses of the cores.
S302, when no fault core exists in any one row of cores arranged along the preset topological direction, determining the deleted cores in the row of cores at the preset position as deleted cores.
In the case where there is no faulty core in any one of the rows of cores arranged in the preset topological direction, a core located at a predetermined position in each row of cores may be designated as a deleted core, and the number of cores designated as deleted cores is equal to the deletion amount.
S303, updating the original address of the non-deleted core into an updated address, and deleting the non-updated address of the core.
The updating address arrangement mode of the core is the same as the original address arrangement mode of the core, and no updating address exists in the deleting core.
In some embodiments, when there is no faulty core in any one row of cores arranged along the preset topological direction, the last deleted cores in the row of cores along the preset topological direction are determined as deleted cores.
When there is no faulty core in any one row of cores arranged along the preset topological direction, determining the last deleted cores in the row of cores along the preset topological direction as deleted cores, and updating the original addresses of the non-deleted cores in the row of cores, where the updated addresses of all the non-deleted cores in the row of cores are the same as the original addresses, that is, the updated addresses are unchanged.
Referring to fig. 14, the array of the original addresses of the cores is shown in fig. 14, where the filled circles represent non-faulty cores and the empty circles represent faulty cores. Taking the preset topological direction as the row direction and the deletion amount in the row direction as 1 as an example, at this time, if there is no faulty core in the first and third rows of cores in the row direction among the two rows of cores arranged in the row direction, the last core in the row direction (i.e., the core with the original address of (4, 1) and the core with the original address of (4, 3) in the two rows of cores may be determined as a deleted core, and six cores with the original addresses of (1, 1), (2, 1), (3, 1), (1, 3), (2, 3) and (3, 3) in the two rows of cores are all non-deleted cores, and the update addresses of the six non-deleted cores may be the same as the original addresses and are (1, 1), (2, 1), (3, 1), (1, 3), (2, 3) and (3, 3), respectively).
Fig. 4 is a flowchart of another core address updating method according to an embodiment of the present disclosure.
Referring to fig. 4, an embodiment of the present disclosure provides a core address updating method, where the core address updating method includes:
s401, determining a preset topological direction and a deletion amount according to a preset size.
The preset size is the size of an array formed by the update addresses of the cores.
S402, when a fault core exists in any one row of cores arranged along the preset topological direction, determining that the deleted cores in the row of cores are deleted cores, and determining all the fault cores in the row of cores to be deleted cores.
The faulty core cannot execute the algorithm, and if the arrangement layout of the update address is matched with the compiling arrangement layout of the cores so as to ensure that each core in the update address array can execute the algorithm, the original address of the faulty core cannot be updated, so that when the faulty core exists in any one row of cores arranged along the preset topological direction, all the faulty cores in each row of cores can be determined as deleted cores.
It should be noted that the deletion amount in the preset topology direction may be the number of cores allowed to be deleted in any one row of cores arranged in the preset topology direction, which is determined according to the preset size, and if the number of faulty cores in any one row of cores arranged in the preset topology direction exceeds the deletion amount in the preset topology direction, the core address cannot be updated, and the chip may need to be invalidated.
S403, updating the original address of the non-deleted core into an updated address, and deleting the non-updated address of the core.
The updating address arrangement mode of the core is the same as the original address arrangement mode of the core, and no updating address exists in the deleting core.
In some embodiments, if there is a faulty core in any one row of cores arranged along the preset topological direction, when the number of faulty cores in the row of cores is less than the deletion amount by n, determining all faulty cores in the row of cores as deleted cores, and determining the last n non-faulty cores in the row of cores along the preset topological direction as deleted cores.
When a faulty core exists in any one row of cores arranged in the preset topological direction and the number of the faulty cores in the row of cores is smaller than the deletion amount by n, all the faulty cores in the row of cores are determined as deleted cores, and the last n non-faulty cores in the row of cores in the preset topological direction are determined as deleted cores, wherein the cores except the deleted cores in the row of cores are all non-deleted cores. When the original address of the non-deleted core in the core arrangement is updated, the updated address of the non-deleted core may be the same as or different from the original address.
Referring to fig. 15, the array of original addresses of cores is shown in fig. 15, where the filled circles represent non-faulty cores and the open circles represent faulty cores. Taking the preset topological direction as the row direction and the deletion amount in the row direction as 2 as an example, if only the second row core in the column direction among the rows of cores arranged in the row direction is a faulty core in the row of cores, and the faulty core is the second core in the row direction among the rows of cores (i.e., the core with the original address of (2, 2)), the number of the faulty cores in the row of cores is less than 1 than the deletion amount, the core with the original address of (2, 2) can be determined as the deleted core, and the last core in the row direction (i.e., the core with the original address of (4, 2)) in the row of cores can also be determined as the deleted core. When the original address of the non-deleted core in the row of cores is updated, the original address (1, 2) can be updated to the updated address (1, 2), and the original address (3, 2) can be updated to the updated address (2, 2).
Fig. 5 is a flowchart of another core address updating method according to an embodiment of the present disclosure.
Referring to fig. 5, an embodiment of the present disclosure provides a core address updating method, where the core address updating method includes:
s501, determining the maximum fault core number of each topological direction; the maximum number of faulty cores is the maximum of the numbers of faulty cores present in all the rows of cores arranged along the corresponding topological direction.
After the chip is initialized, the original address of the fault core in the chip can be obtained, and the maximum fault core number in each topological direction can be determined according to the original address of the fault core. In all the rows of cores arranged along a certain topological direction, the number of fault cores included in each row of cores may be the same or different, and the maximum value is the maximum number of fault cores in the topological direction.
Referring to fig. 16, the array of original addresses of cores is shown in fig. 16, where the filled circles represent non-faulty cores and the empty circles represent faulty cores. It can be seen that, if four cores with original addresses of (3, 1), (2, 2), (4, 3) and (3, 4) are all fault cores, then, among the four rows of cores arranged along the row direction, there is one fault core in each row of cores, and then, the maximum number of fault cores in the row direction is 1; and of the four rows of cores arranged in the column direction, the core in the first row in the row direction has no faulty core, the core in the second row in the row direction and the core in the fourth row both have one faulty core, and the core in the third row in the row direction has two faulty cores, then the maximum faulty core number in the column direction is 2.
S502, according to the preset size, determining the allowable deletion amount of each topological direction when different topological directions are taken as the preset topological directions.
The preset size is the size of an array formed by the update addresses of the cores. If the updated addresses of the cores are to form an array with a preset size, when the cores in the original address array are deleted in different topological directions, the number of (original addresses of) cores to be deleted in each row of cores arranged in the corresponding topological direction needs to be determined, that is, the allowed deletion amount.
Assuming that the original addresses of the cores form a 4-row-4-column matrix array and the predetermined size is 3X4, as mentioned above, the size of 3 rows and 4 columns is substantially equivalent to the size of 4 rows and 3 columns in the address array, and it is feasible to use the row direction as the predetermined topological direction or the column direction as the predetermined topological direction. When the row direction is taken as the preset topological direction, the allowable deletion amount in the row direction is 1, and the allowable deletion amount in the column direction is 0. When the column direction is taken as the preset topological direction, the allowed deletion amount in the row direction is 0, and the allowed deletion amount in the column direction is 1. Whether deleting one core (original address) in each row of cores arranged in the row direction results in an updated address array of 4 rows and 3 columns, or deleting one core (original address) in each row of cores arranged in the column-row direction results in an updated address array of 3 rows and 4 columns, the size of the updated address array is actually 3X 4.
S503, determining part of the topological directions as preset topological directions according to the maximum fault kernel number and the allowed deletion amount, and determining the allowed deletion amount of the corresponding topological directions as the deletion amount of the preset topological directions; the maximum fault core number in any preset topological direction does not exceed the deletion amount.
If the maximum number of fault cores in a certain topological direction exceeds the allowed deletion amount, after all (original addresses of) fault cores are deleted, the updated addresses of the non-deleted cores are not enough to form an array which meets the preset size. Therefore, in order to enable the updated addresses of the cores to form an array conforming to a preset size, the condition needs to be satisfied: the maximum fault core number of the preset topological direction does not exceed the allowed deletion amount.
The number of the topology directions with the maximum fault core number not exceeding the allowed deletion amount may be multiple, and any topology direction with the maximum fault core number not exceeding the allowed deletion amount may be selected as the preset topology direction. After the preset topological direction is determined, the allowed deletion amount of the preset topological direction can be determined as the deletion amount, and the deletion amount of the preset topological direction is the number of cores to be deleted in each row of cores arranged along the preset topological direction.
Of course, when the number of the topology directions in which the maximum number of the fault cores does not exceed the allowable deletion amount is multiple, one topology direction with the minimum allowable deletion amount may be selected from the multiple topology directions as the preset topology direction.
S504, determining the deleted cores as deleted cores in each row of cores arranged along the preset topological direction.
And S505, updating the original address of the non-deleted core into an updated address, and deleting the non-updated address of the core.
In some embodiments, the preset arrangement may be a two-dimensional matrix, and then one topological direction is determined as the preset topological direction from a row topological direction and a column topological direction of the two-dimensional matrix.
If the original address and the updated address of the core are arranged in the form of a two-dimensional matrix, the topological directions of the two-dimensional matrix include a row topological direction and a column topological direction, and one topological direction needs to be selected from the row topological direction and the column topological direction as a preset topological direction.
Fig. 6 is a flowchart of a mapping method according to an embodiment of the present disclosure.
Referring to fig. 6, an embodiment of the present disclosure provides a mapping method for updating a chip with a core address according to the foregoing core address updating method.
The mapping method of the embodiment of the disclosure specifically includes:
s601, according to the arrangement situation of the update addresses of the cores in the chip, mapping a plurality of tasks to the cores with the update addresses.
After the chip updates the address according to the aforementioned core address updating method, the plurality of tasks may be mapped to the cores each having the update address, respectively, according to an array configured by the update addresses of the cores in the chip. The cores with the updated addresses can all execute algorithms, and after the tasks are mapped to the cores with the updated addresses, the cores can respectively process the tasks and work cooperatively normally.
Fig. 7 is a flowchart of another mapping method provided in the embodiment of the present disclosure.
Referring to fig. 7, an embodiment of the present disclosure provides a mapping method for updating a chip with a core address according to the foregoing core address updating method.
The mapping method of the embodiment of the disclosure specifically includes:
and S701, compiling the problem to be processed according to the preset size to obtain a plurality of tasks.
The preset size is the size of an array formed by the update addresses of the cores and is matched with the preset compiling arrangement layout of the cores. When compiling the problem to be processed (or an algorithm capable of solving the problem to be processed), the problem to be processed may be compiled into a plurality of tasks according to a preset size, so that the tasks can all be executed by the cores in the updated address array.
S702, according to the arrangement situation of the update addresses of the cores in the chip, mapping a plurality of tasks to the cores with the update addresses.
The cores with the updated addresses can all execute algorithms, and after the tasks are mapped to the cores with the updated addresses, the cores can respectively process the tasks and work cooperatively normally.
Fig. 8 is a flowchart of a data transmission method according to an embodiment of the present disclosure.
Referring to fig. 8, an embodiment of the present disclosure provides a data transmission method, which is used for updating a chip with a core address according to the foregoing core address updating method.
The data transmission method of the embodiment of the present disclosure specifically includes:
s801, acquiring data, wherein the data comprises a destination core updating address.
After the original addresses of at least part of cores in the chip are updated, the arrangement layout of the updated addresses of the cores is matched with the preset compiling layout of the cores, the cores with the updated addresses can execute the algorithm certainly, and the tasks are mapped to the cores with the updated addresses.
And S802, updating the address according to at least the destination core, and transmitting the data to the destination core.
At least part of the cores have the updated address and the original address at the same time, at least part of the cores only have the original address but do not have the updated address, all the cores have the normal routing function, and the data can be transmitted to the target core at least according to the updated address of the target core.
Fig. 9 is a flowchart of another data transmission method according to an embodiment of the disclosure.
Referring to fig. 9, an embodiment of the present disclosure provides a data transmission method, which is used for updating a chip with a core address according to the foregoing core address updating method.
The data transmission method of the embodiment of the present disclosure specifically includes:
s901, data is obtained, and the data comprises a target core updating address.
And S902, transmitting the data to the target core according to the corresponding relation between the original address and the updated address of at least part of cores, the original address of at least part of cores and the updated address of the target core.
After the original addresses of at least part of cores in the chip are updated, each core can store the update address of the core which is adjacent to the core in all directions and has the update address, each core has the original address, and the core with the updated original address also has the update address.
Specifically, the current core may determine whether the current core is the destination core according to the update address condition of the current core, and if not, the current core may select an update address closest to the update address of the destination core in a certain topology direction according to the update address of the core adjacent to the current core in each topology direction and having the update address stored in the current core, transmit data to the core corresponding to the update address according to the original address of each core, and continue to transmit data by the core corresponding to the update address.
Referring to fig. 12 and 13, as shown in fig. 12, the array is formed by the original addresses of the cores, and fig. 13 is formed by the update addresses of the cores. After at least some of the cores have their original addresses updated to the updated addresses according to the predetermined size, the four cores having the original addresses (4, 1), (2, 2), (4, 3) and (3, 4) shown in fig. 12 do not have the updated addresses, and at this time, the updated address of the right core in the row direction stored by the core having the original address (2, 2) is (2, 2), and the updated address of the right core in the row direction stored by the core having the original address (1, 2) is also (2, 2), because the core having the original address (2, 2) does not have the updated address, and the core having the updated address should be the core having the original address (3, 2) and the updated address of the core having the original address (3, 2) should be (2, 2) on the right side of the core having the original address (1, 2) in the row direction.
Assuming that a core with an original address of (2, 3) acquires data and an update address of a destination core carried by the data is (3, 4), at this time, the core with the original address of (2, 3), an update address of a left core in a stored row direction is (1, 3), an update address of a right core in the stored row direction is (3, 3), an update address of an upper core in a stored column direction is (2, 2), and an update address of a lower core in the stored column direction is (2, 4), if selection according to the row direction is preferred, among the four update addresses (1, 3), (3, 3), (2, 2), and (2, 4), an update address closest to the update address of the destination core in the row direction is (3, 3), the core with the original address of (2, 3) may select a core with the update address of (3, 3), and first transfer the data to the core with the update address of (3, 3), and the core with the updated address (3, 3) continues to transmit data.
Fig. 10 is a flowchart of another data transmission method according to an embodiment of the disclosure.
Referring to fig. 10, an embodiment of the present disclosure provides a data transmission method, which is used for updating a chip with a core address according to the foregoing core address updating method.
The data transmission method of the embodiment of the present disclosure specifically includes:
s1001, data is obtained, and the data comprises a target core updating address.
S1002, determining a destination core original address corresponding to the destination core updating address.
After the original addresses of at least part of cores in the chip are updated, a routing address translation table can be maintained in each core, and also can be maintained in a central control core. The corresponding relationship between the original address and the updated address of the core may be stored in the routing address translation table, so that the core may directly query the local routing address translation table to determine the original address corresponding to a certain updated address, or may request the central control core to determine the original address corresponding to a certain updated address, which is not specifically limited in the embodiments of the present disclosure.
In the routing address translation table, the update address of a part of cores may be the same as the original address thereof, or the update address of a part of cores may be different from the original address thereof, and the update address of a part of cores which do not have an update address may be displayed as null.
And S1003, transmitting the data to the target core according to the original address of each core.
The core has a routing function no matter whether the core has the update address or not, so after the destination core original address corresponding to the destination core update address is determined, the data can be transmitted to the destination core original address according to the original address of each core.
Fig. 17 is a block diagram illustrating a core address updating apparatus according to an embodiment of the disclosure.
Referring to fig. 17, an embodiment of the present disclosure provides a core address updating apparatus 170, configured to update a core address of a chip, where the chip includes a plurality of cores, and original addresses of the plurality of cores are arranged according to a preset arrangement manner, where the core address updating apparatus 170 includes:
an update module 1701 for updating original addresses of at least a part of cores to update addresses according to a preset size; the updating address arrangement mode of the core is the same as the original address arrangement mode of the core, the preset size is the size of an array formed by the updating addresses of the core, and at least part of the cores have no updating addresses.
Fig. 18 is a block diagram illustrating a mapping apparatus according to an embodiment of the disclosure.
Referring to fig. 18, an embodiment of the present disclosure provides a mapping apparatus 180, configured to update a chip with a core address according to the foregoing core address updating method, where the mapping apparatus 180 includes:
a mapping module 1801, configured to map multiple tasks to a core having an update address according to an arrangement of the update addresses of the cores in the chip.
In addition, the embodiment of the disclosure further provides a chip, which is used for implementing at least one of the following methods:
the core address update method as described above;
the mapping method as described above;
such as the aforementioned data transmission method.
Furthermore, the disclosed embodiments also provide a computer readable medium, on which a computer program is stored, wherein the computer program, when executed by a processing core, implements at least one of the following methods:
the core address update method as described above;
the mapping method as described above;
such as the aforementioned data transmission method.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, R11M, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.

Claims (10)

1. A core address updating method is used for updating the core address of a chip, wherein the chip comprises a plurality of cores, and the original addresses of the cores are arranged according to a preset arrangement mode; the method comprises the following steps:
updating original addresses of at least part of cores into updated addresses according to the preset size; the updating address arrangement mode of the core is the same as the original address arrangement mode of the core, the preset size is the size of an array formed by the updating addresses of the core, and at least part of the cores have no updating addresses.
2. The core address updating method according to claim 1, wherein the updating the original addresses of at least some cores to the updated addresses according to the preset size includes:
determining a preset topological direction and a deletion amount thereof according to the preset size;
determining a deleted core as a deleted core in each row of cores arranged along a preset topological direction;
and updating the original address of the non-deleted core into an updated address, wherein the deleted core has no updated address.
3. The core address updating method according to claim 2, wherein the determining, in each row of cores arranged in the preset topological direction, that the cores with the deletion amount are the deletion cores includes:
when no fault core exists in any one row of cores arranged along the preset topological direction, determining the deleted cores in the row of cores at the preset positions as deleted cores.
4. The core address updating method according to claim 3, wherein the cores with the deletion amount located at the predetermined position in the row of cores are the last cores with the deletion amount in the preset topological direction in the row of cores.
5. A mapping method for a chip whose core address is updated according to the core address updating method of any one of claims 1 to 4, the mapping method comprising:
and mapping a plurality of tasks to the cores with the updated addresses according to the arrangement condition of the updated addresses of the cores in the chip.
6. A data transfer method for a chip whose core address is updated according to the core address updating method of any one of claims 1 to 4, the data transfer method comprising:
acquiring data, wherein the data comprises a target core updating address;
and updating the address according to at least the destination core, and transmitting the data to the destination core.
7. A kind of kernel address updating device, is used for updating the kernel address of the chip, the said chip includes a plurality of kernels, the original address of the said a plurality of kernels arranges according to the predetermined permutation mode, the updating device of the kernel address includes:
the updating module is used for updating the original addresses of at least part of cores into updated addresses according to the preset size; the updating address arrangement mode of the core is the same as the original address arrangement mode of the core, the preset size is the size of an array formed by the updating addresses of the core, and at least part of the cores have no updating addresses.
8. A mapping apparatus for a chip whose core address is updated according to the core address updating method of any one of claims 1 to 4, comprising:
and the mapping module is used for mapping the tasks to the cores with the updated addresses according to the arrangement condition of the updated addresses of the cores in the chip.
9. A chip comprising a plurality of cores, the chip being configured to implement at least one of the following methods:
the core address updating method of any one of claims 1-4;
the mapping method of claim 5;
the data transmission method of claim 6.
10. A computer-readable medium on which a computer program is stored, wherein the computer program, when executed by a processing core, implements at least one of the following methods:
the core address updating method of any one of claims 1-4;
the mapping method of claim 5;
the data transmission method of claim 6.
CN202110302080.6A 2021-03-22 2021-03-22 Nuclear address updating method, mapping method, data transmission method, device and chip Active CN113010353B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202110302080.6A CN113010353B (en) 2021-03-22 2021-03-22 Nuclear address updating method, mapping method, data transmission method, device and chip
PCT/CN2022/080104 WO2022199390A1 (en) 2021-03-22 2022-03-10 Processing method and apparatus, electronic device, and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110302080.6A CN113010353B (en) 2021-03-22 2021-03-22 Nuclear address updating method, mapping method, data transmission method, device and chip

Publications (2)

Publication Number Publication Date
CN113010353A true CN113010353A (en) 2021-06-22
CN113010353B CN113010353B (en) 2024-05-28

Family

ID=76404248

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110302080.6A Active CN113010353B (en) 2021-03-22 2021-03-22 Nuclear address updating method, mapping method, data transmission method, device and chip

Country Status (1)

Country Link
CN (1) CN113010353B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101464807A (en) * 2009-01-08 2009-06-24 杭州华三通信技术有限公司 Application program loading method and device
CN101581959A (en) * 2009-07-02 2009-11-18 华为技术有限公司 Method and equipment for resetting single core in multicore chip
WO2014204495A1 (en) * 2013-06-19 2014-12-24 Empire Technology Development, Llc Locating cached data in a multi-core processor
CN104657239A (en) * 2015-03-19 2015-05-27 哈尔滨工业大学 Transient fault restoration system and transient fault restoration method of separated log based multi-core processor
CN105653411A (en) * 2015-12-28 2016-06-08 哈尔滨工业大学 Multi-core processor chip reconfigurable system capable of supporting local permanent fault recovery
CN106030541A (en) * 2014-02-23 2016-10-12 高通股份有限公司 Kernel masking of dram defects
CN108139928A (en) * 2015-08-26 2018-06-08 Netapp股份有限公司 Migration between CPU core

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101464807A (en) * 2009-01-08 2009-06-24 杭州华三通信技术有限公司 Application program loading method and device
CN101581959A (en) * 2009-07-02 2009-11-18 华为技术有限公司 Method and equipment for resetting single core in multicore chip
WO2014204495A1 (en) * 2013-06-19 2014-12-24 Empire Technology Development, Llc Locating cached data in a multi-core processor
CN106030541A (en) * 2014-02-23 2016-10-12 高通股份有限公司 Kernel masking of dram defects
CN104657239A (en) * 2015-03-19 2015-05-27 哈尔滨工业大学 Transient fault restoration system and transient fault restoration method of separated log based multi-core processor
CN108139928A (en) * 2015-08-26 2018-06-08 Netapp股份有限公司 Migration between CPU core
CN105653411A (en) * 2015-12-28 2016-06-08 哈尔滨工业大学 Multi-core processor chip reconfigurable system capable of supporting local permanent fault recovery

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CHRISTOPHER LAFRIEDA等: "Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor", 《37TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS (DSN\'07)》, 16 July 2007 (2007-07-16) *
张维强等: "基于MSKPCA和SVM的转子故障诊断模型及应用", 《机械设计与制造》, no. 10, 8 October 2015 (2015-10-08) *
沈杨书: "数字雷达接收***的SoC原型实现与验证", 《中国优秀硕士学位论文全文数据库信息科技辑》, 15 November 2014 (2014-11-15) *

Also Published As

Publication number Publication date
CN113010353B (en) 2024-05-28

Similar Documents

Publication Publication Date Title
CN103354923B (en) A kind of data re-establishing method, device and system
US9983821B2 (en) Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application
US10216578B2 (en) Data storage device for increasing lifetime and RAID system including the same
US7730274B1 (en) Preventing undesired trespass in storage arrays
CN108459974A (en) The high bandwidth memory equipment of integrated flash memory
US9966152B2 (en) Dedupe DRAM system algorithm architecture
US20100306435A1 (en) Reconfigurable virtual backplane systems and methods
US10402113B2 (en) Live migration of data
CN107656834A (en) Recover main frame based on transaction journal to access
US8943359B2 (en) Common hot spare for multiple RAID groups
US20200341639A1 (en) Lattice layout of replicated data across different failure domains
CN107729536A (en) A kind of date storage method and device
CN110737394A (en) Method, apparatus and computer program product for managing cache
US20200174683A1 (en) Method and system for delivering message in storage system
CN109032963A (en) Access control
CN108427584B (en) Chip with parallel computing cores and capable of being started quickly and configuration method of chip
US9003160B2 (en) Active buffered memory
CN113010354A (en) Core classification method, mapping method, data transmission device and chip
CN106462550B (en) For sharing the method, equipment and device of embedded hardware resource
CN113010353B (en) Nuclear address updating method, mapping method, data transmission method, device and chip
WO2022199390A1 (en) Processing method and apparatus, electronic device, and storage medium
US11256428B2 (en) Scaling raid-based storage by redistributing splits
CN113296685B (en) Data processing method and device and computer readable storage medium
US10108691B2 (en) Atomic clustering operations for managing a partitioned cluster online
US9396077B2 (en) Redundant location address mapper

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant