CN112951851A - Display substrate and display device - Google Patents
Display substrate and display device Download PDFInfo
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- CN112951851A CN112951851A CN202110230986.1A CN202110230986A CN112951851A CN 112951851 A CN112951851 A CN 112951851A CN 202110230986 A CN202110230986 A CN 202110230986A CN 112951851 A CN112951851 A CN 112951851A
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- 239000000758 substrate Substances 0.000 title claims abstract description 128
- 239000002184 metal Substances 0.000 claims abstract description 86
- 239000004065 semiconductor Substances 0.000 claims abstract description 74
- 230000000903 blocking effect Effects 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 159
- 238000000034 method Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides a display substrate and a display device. The display substrate comprises a substrate, a source drain metal layer, a semiconductor layer and a gate metal layer, wherein the source drain metal layer is formed on the substrate and comprises a data line pattern, the data line pattern is connected with the semiconductor layer, the semiconductor layer is located on one side, far away from the substrate, of the source drain metal layer, and the gate metal layer is located on one side, far away from the substrate, of the semiconductor layer. In the embodiment of the invention, the semiconductor layer is arranged on one side of the source drain metal layer away from the substrate, and the gate metal layer is arranged on one side of the semiconductor layer away from the substrate, namely, the source drain metal layer is closer to the substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate and a display device.
Background
The display substrate generally includes a thin film transistor on a substrate, and generally, the thin film transistor includes a semiconductor layer, a gate insulating layer, a gate layer, and a source and drain metal layer disposed in a direction away from the substrate, where the source and drain metal layer includes a data line, and the data line is generally made of a conductive metal material to transmit a data signal. However, the metal material may have a certain amount of residue during the etching process, and the residue may cause adverse effects such as structural short circuit. However, since the data line and the gate layer are relatively close to each other, the gate layer may be damaged by a repair operation on an overlapping region of the data line and the gate layer, so that the product may be damaged unrepairable, and therefore, the yield of the display substrate may be reduced due to etching residue of the source-drain metal layer.
Disclosure of Invention
The embodiment of the invention provides a display substrate and a display device, and aims to solve the problem that the yield of the display substrate is reduced due to etching residues of a source drain metal layer.
In a first aspect, an embodiment of the present invention provides a display substrate, including a substrate, a source-drain metal layer, a semiconductor layer, and a gate metal layer, where the source-drain metal layer is formed on the substrate, the source-drain metal layer includes a data line pattern, the data line pattern is connected to the semiconductor layer, the semiconductor layer is located on a side of the source-drain metal layer away from the substrate, and the gate metal layer is located on a side of the semiconductor layer away from the substrate.
Optionally, the source drain metal layer is in direct contact with the substrate.
Optionally, the gate metal layer includes a gate signal line, an overlapping region exists between an orthogonal projection of the gate signal line on the substrate and an orthogonal projection of the semiconductor layer on the substrate, the source-drain metal layer further includes a light blocking pattern, the light blocking pattern is located between the semiconductor layer and the substrate, the overlapping region is covered by an orthogonal projection of the light blocking pattern on the substrate, and the light blocking pattern is separated from the data line pattern.
Optionally, the display substrate includes a first insulating layer and a second insulating layer, the first insulating layer is located between the semiconductor layer and the source-drain metal layer, the second insulating layer is located between the semiconductor layer and the gate metal layer, the gate metal layer includes a first conductive structure, and the semiconductor layer is connected to the source-drain metal layer through the first conductive structure.
Optionally, the display substrate includes a first via hole, the first via hole penetrates through the first insulating layer, the semiconductor layer and the second insulating layer, the first conductive structure is connected with a side surface, away from the substrate, of the source-drain metal layer through the first via hole, the semiconductor layer includes a first conductive pattern and a second conductive pattern, the semiconductor layer further includes an active layer of the thin film transistor, the first conductive pattern, the active layer and the second conductive pattern are sequentially connected, and the first conductive structure is connected with the first conductive pattern.
Optionally, an orthographic projection of a portion, located on a side of the semiconductor layer away from the substrate, of the first conductive structure on the substrate and an orthographic projection of the covered first via hole on the substrate are provided, and the first conductive structure is in contact with a surface of the side of the semiconductor layer away from the substrate.
Optionally, the display substrate further includes a common electrode layer, a third insulating layer, and a pixel electrode layer, which are sequentially stacked along a direction away from the substrate, and the gate metal layer further includes a second conductive structure, the second conductive structure is connected to the pixel electrode layer, and the second conductive structure is connected to the second conductive pattern.
Optionally, the display substrate includes a second via hole, the second via hole penetrates through the semiconductor layer and the second insulating layer, the second conductive structure is connected to the pixel electrode layer through the second via hole, and the second conductive structure is connected to the semiconductor layer through the second via hole.
Optionally, the source-drain metal layer further includes a dummy electrode pattern, the dummy electrode pattern is connected to the second conductive structure, an orthogonal projection of the dummy electrode pattern on the substrate covers an orthogonal projection of a side surface of the second conductive structure close to the dummy electrode pattern on the substrate, and the dummy electrode pattern is separated from the data line pattern.
In a second aspect, an embodiment of the present invention provides a display module, including the display substrate of any one of the first aspects.
In the embodiment of the invention, the semiconductor layer is arranged on the side of the source drain metal layer far away from the substrate, and the gate metal layer is arranged on the side of the semiconductor layer far away from the substrate, namely, the source drain metal layer is closer to the substrate, so that in the manufacturing process, the source drain metal is firstly manufactured, the semiconductor layer is manufactured next, and the gate metal layer is finally manufactured, the structures between the source drain metal layer and the substrate are relatively fewer, if the source drain metal layer has residues, the influence on other structures caused by the repair of the source drain metal layer is relatively smaller, the repairability of the display substrate is favorably improved, and the yield of the product is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic view of a stack of a source drain metal layer, a semiconductor layer, and a gate metal layer in an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a source-drain metal layer in an embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of a semiconductor layer according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a gate metal layer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an intermediate process for manufacturing a display substrate according to an embodiment of the present invention;
FIG. 6 is a schematic view of another intermediate process of a display substrate according to an embodiment of the present invention;
FIG. 7 is a schematic view of another intermediate process of a display substrate according to an embodiment of the present invention;
FIG. 8 is a schematic view of another intermediate process of a display substrate according to an embodiment of the present invention;
FIG. 9 is a schematic view of another intermediate process of a display substrate according to an embodiment of the present invention;
FIG. 10 is a schematic intermediate process diagram of a display substrate according to yet another embodiment of the present invention;
FIG. 11 is a schematic view of another intermediate process of a display substrate according to yet another embodiment of the present invention;
FIG. 12 is a schematic view of another intermediate process of a display substrate according to yet another embodiment of the present invention;
FIG. 13 is a schematic view of another intermediate process of a display substrate according to yet another embodiment of the present invention;
FIG. 14 is a schematic view of another intermediate process of a display substrate according to yet another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a display substrate.
As shown in fig. 1, 9 and 14, the display substrate includes a substrate 10, a source-drain metal layer 20, a semiconductor layer 30 and a gate metal layer 40, wherein the source-drain metal layer 20 is formed on the substrate 10.
As shown in fig. 2, the source-drain metal layer 20 includes a data line pattern 201, and the data line pattern 201 is connected to the semiconductor layer 30.
As shown in fig. 9 and 14, the semiconductor layer 30 is located on a side of the source-drain metal layer 20 away from the substrate 10, and the gate metal layer 40 is located on a side of the semiconductor layer 30 away from the substrate 10.
In the embodiment of the invention, the semiconductor layer 30 is arranged on the side of the source-drain metal layer 20 away from the substrate 10, and the gate metal layer 40 is arranged on the side of the semiconductor layer 30 away from the substrate 10, that is, the source-drain metal layer 20 is closer to the substrate 10, so that in the manufacturing process, the source-drain metal layer 20 is firstly manufactured on the substrate 10, the semiconductor layer 30 is manufactured next, and the gate metal layer 40 is manufactured finally, the structure between the source-drain metal layer 20 and the substrate 10 is relatively small, if the source-drain metal layer 20 has residues, the influence on other structures caused by the repair of the source-drain metal layer 20 is relatively small, the repairability of the display substrate is favorably improved, and the yield of the product is improved.
In some embodiments, the source-drain metal layer 20 is in direct contact with the substrate 10, that is, the source-drain metal layer 20 is directly fabricated on the substrate 10, so that, if etching residues of the source-drain metal layer 20 need to be repaired, the repairing process is performed on the substrate 10, and the repairing process does not affect or damage other structures, so that the repairability of products can be remarkably improved, and the yield of the products can be improved.
In some embodiments, as shown in fig. 4, the gate metal layer 40 includes a gate signal line 401, an overlapping region exists between an orthogonal projection of the gate signal line 401 on the substrate 10 and an orthogonal projection of the semiconductor layer 30 on the substrate 10, as shown in fig. 2, the source-drain metal layer 20 further includes a light-blocking pattern 202, the light-blocking pattern 202 is located between the semiconductor layer 30 and the substrate 10, an orthogonal projection of the light-blocking pattern 202 on the substrate 10 covers the overlapping region, and the light-blocking pattern 202 is separated from the data line pattern 201.
In this embodiment, there is an overlap region between the orthographic projection of the gate signal line 401 on the substrate 10 and the orthographic projection of the semiconductor layer 30 on the substrate 10, as shown in fig. 3, the semiconductor layer 30 corresponding to the overlap region may be understood as the active layer 301 of the thin film transistor, and more specifically, may be a channel region of the active layer 301, and the source region and the drain region of the active layer 301 may be located outside the overlap region. Other portions of the semiconductor layer 30 may be understood to perform primarily a conductive function. The gate signal line 401 corresponding to the overlap region may be understood as a gate electrode of a thin film transistor, and the other portion of the gate signal line 401 may be understood as mainly realizing signal transmission.
In this embodiment, the light blocking pattern 202 is further formed to block light, so as to prevent the light from directly irradiating the active layer 301 of the thin film transistor, which is helpful for improving the reliability of the thin film transistor. In this embodiment, the light blocking pattern 202 is located on the source/drain metal layer 20, that is, a separate step is not required to fabricate the light blocking layer, which is helpful to save the process and the fabrication cost.
In some embodiments, the display substrate includes a first insulating layer 51 and a second insulating layer 52, the first insulating layer 51 is located between the semiconductor layer 30 and the source-drain metal layer 20, and the second insulating layer 52 is located between the semiconductor layer 30 and the gate metal layer 40, as shown in fig. 4, the gate metal layer 40 includes a first conductive structure 402, and the semiconductor layer 30 is connected to the source-drain metal layer 20 through the first conductive structure 402.
In this embodiment, the first insulating layer 51 is used to realize insulation between the semiconductor layer 30 and the source-drain metal layer 20, and the second insulating layer 52 is used to realize insulation between the semiconductor layer 30 and the gate signal line 401.
In some embodiments, the display substrate includes a first via penetrating through the first insulating layer 51, the semiconductor layer 30 and the second insulating layer 52, and the first conductive structure 402 is connected to a side surface of the source-drain metal layer 20 away from the substrate 10 through the first via.
In this embodiment, as shown in fig. 3, the semiconductor layer 30 further includes a first conductive pattern 302 and a second conductive pattern 303, the first conductive pattern 302, the active layer 301 and the second conductive pattern 303 are sequentially connected, and the first conductive structure 402 is connected to the first conductive pattern 302, so as to connect the data line and the thin film transistor.
In some embodiments, an orthographic projection of the portion of the first conductive structure 402 on the side of the semiconductor layer 30 away from the substrate 10 on the substrate 10 is in contact with an orthographic projection of the covered first via on the substrate 10, and the first conductive structure 402 is in contact with a side surface of the semiconductor layer 30 away from the substrate 10.
In this embodiment, a part of the surface of the first conductive structure 402 is in contact with the upper surface of the semiconductor layer 30, which is helpful to increase the contact area between the first conductive structure 402 and the semiconductor layer 30 and improve the signal transmission effect.
In some embodiments, the display substrate further includes a common electrode layer 54, a third insulating layer, and a pixel electrode layer 60 sequentially stacked along a direction away from the substrate 10, as shown in fig. 4, the gate metal layer 40 further includes a second conductive structure 403, the second conductive structure 403 is connected to the pixel electrode layer 60, and the second conductive structure 403 is connected to the second conductive pattern 303.
In this embodiment, the pixel electrode layer 60 is connected to the semiconductor layer 30 through the second conductive structure 403, so as to transmit the data signal transmitted by the data line to the pixel electrode through the thin film transistor.
In some embodiments, the display substrate includes a second via hole penetrating the semiconductor layer 30 and the second insulating layer 52, the second conductive structure 403 is connected to the pixel electrode layer 60 through the second via hole, and the second conductive structure 403 is connected to the semiconductor layer 30 through the second via hole.
Similar to the first via, in this embodiment, the second via is used to connect the second conductive structure 403 with the semiconductor layer 30 and the pixel electrode, and in order to improve uniformity of different positions of the display substrate and simplify process steps, in this embodiment, the first via and the second via are obtained by patterning in substantially the same process, and accordingly, the thicknesses of the first conductive structure 402 and the second conductive structure 403 in a direction perpendicular to the substrate 10 are substantially equal, where substantially equal means that the sizes thereof are equal under the condition of ignoring process errors and the like. By providing the first conductive structure 402 and the second conductive structure 403, connection between the data line and the semiconductor layer 30 and connection between the semiconductor and the pixel electrode can be achieved.
In some embodiments, as shown in fig. 2, the source-drain metal layer 20 further includes a dummy electrode pattern 203, the dummy electrode pattern 203 is connected to the second conductive structure 403, an orthogonal projection of the dummy electrode pattern 203 on the substrate 10 covers an orthogonal projection of a side surface of the second conductive structure 403 close to the dummy electrode pattern 203 on the substrate 10, and the dummy electrode pattern 203 is separated from the data line pattern 201.
In this embodiment, the dummy electrode pattern 203 is mainly used for supporting the second conductive structure 403, and it should be understood that the thin film transistor is connected to the pixel electrode layer 60 sequentially through the second conductive pattern 303 and the second conductive structure 403, so that the second conductive structure 403 is not used for implementing a conductive function, but is mainly used for supporting the second conductive structure 403, and by providing the second conductive structure 403, over-etching during forming the second via hole can be avoided, so that the depth of the second via hole is substantially the same as that of the first via hole, further, the distances between the first conductive structure 402 and the second conductive structure 403 and the substrate 10 are substantially the same, and the uniformity of the thicknesses of the structures at different positions of the display substrate is improved.
As shown in fig. 5 and 10, in this embodiment, first, a source/drain metal layer 20 is formed on a substrate 10 by a patterning process; as shown in fig. 6 and fig. 11, next, a first insulating layer 51 covering the source-drain metal layer 20 is fabricated; as shown in fig. 7 and 12, next, the semiconductor layer 30 and the second insulating layer 52 are sequentially formed, and a first via hole and a second via hole are opened at specified positions; as shown in fig. 8 and 13, a gate metal layer 40 is next fabricated; as shown in fig. 9 and 14, subsequent structures such as the planarization layer 53, the common electrode layer 54, the protective layer 55, and the pixel electrode layer 60 are formed, and thus, the display substrate is completed.
An embodiment of the invention provides a display module, which comprises the display substrate.
Since the technical solution of this embodiment includes all the technical solutions of the above display substrate embodiments, at least all technical effects can be achieved, and details are not described here.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A display substrate is characterized by comprising a substrate, a source drain metal layer, a semiconductor layer and a gate metal layer, wherein the source drain metal layer is formed on the substrate and comprises a data line pattern, the data line pattern is connected with the semiconductor layer, the semiconductor layer is positioned on one side, away from the substrate, of the source drain metal layer, and the gate metal layer is positioned on one side, away from the substrate, of the semiconductor layer.
2. The display substrate of claim 1, wherein the source drain metal layer is in direct contact with the substrate.
3. The display substrate according to claim 1, wherein the gate metal layer comprises a gate signal line, an overlapping region exists between an orthographic projection of the gate signal line on the substrate and an orthographic projection of the semiconductor layer on the substrate, the source and drain metal layers further comprise a light blocking pattern, the light blocking pattern is located between the semiconductor layer and the substrate, the overlapping region is covered by an orthographic projection of the light blocking pattern on the substrate, and the light blocking pattern is separated from the data line pattern.
4. The display substrate according to claim 1, wherein the display substrate comprises a first insulating layer and a second insulating layer, the first insulating layer is located between the semiconductor layer and the source-drain metal layer, the second insulating layer is located between the semiconductor layer and the gate metal layer, the gate metal layer comprises a first conductive structure, and the semiconductor layer is connected with the source-drain metal layer through the first conductive structure.
5. The display substrate according to claim 4, wherein the display substrate comprises a first via hole, the first via hole penetrates through the first insulating layer, the semiconductor layer and the second insulating layer, the first conductive structure is connected with the surface of one side, away from the substrate, of the source drain metal layer through the first via hole, the semiconductor layer comprises a first conductive pattern and a second conductive pattern, the semiconductor layer further comprises an active layer of the thin film transistor, the first conductive pattern, the active layer and the second conductive pattern are sequentially connected, and the first conductive structure is connected with the first conductive pattern.
6. The display substrate according to claim 5, wherein an orthographic projection of a portion of the first conductive structure on a side of the semiconductor layer away from the substrate on the substrate is in contact with an orthographic projection of the covered first via on the substrate, and the first conductive structure is in contact with a surface of the side of the semiconductor layer away from the substrate.
7. The display substrate according to claim 5, wherein the display substrate further comprises a common electrode layer, a third insulating layer and a pixel electrode layer, which are sequentially stacked along a direction away from the substrate, the gate metal layer further comprises a second conductive structure, the second conductive structure is connected with the pixel electrode layer, and the second conductive structure is connected with the second conductive pattern.
8. The display substrate according to claim 7, wherein the display substrate comprises a second via hole penetrating the semiconductor layer and the second insulating layer, the first conductive structure is connected to the pixel electrode layer through the second via hole, and the first conductive structure is connected to the semiconductor layer through the second via hole.
9. The display substrate according to claim 7 or 8, wherein the source-drain metal layer further comprises a dummy electrode pattern, the dummy electrode pattern is connected to the second conductive structure, an orthogonal projection of the dummy electrode pattern on the substrate covers an orthogonal projection of a side surface of the second conductive structure close to the dummy electrode pattern on the substrate, and the dummy electrode pattern is separated from the data line pattern.
10. A display module comprising the display substrate according to any one of claims 1 to 9.
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| CN202110230986.1A CN112951851B (en) | 2021-03-02 | 2021-03-02 | Display substrate and display device |
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| CN202110230986.1A CN112951851B (en) | 2021-03-02 | 2021-03-02 | Display substrate and display device |
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| JPH08181325A (en) * | 1994-12-27 | 1996-07-12 | Sharp Corp | Manufacture of semiconductor element and manufacture of substrate for display device |
| CN1828963A (en) * | 2005-01-15 | 2006-09-06 | 三星Sdi株式会社 | A thin film transistor, a method for preparing the same and a flat panel display employing the same |
| CN105206570A (en) * | 2015-10-27 | 2015-12-30 | 深圳市华星光电技术有限公司 | Display panel and production method thereof |
| CN106981478A (en) * | 2017-04-07 | 2017-07-25 | 京东方科技集团股份有限公司 | Top gate type thin film transistor and preparation method thereof, array base palte, display panel |
| US20180190831A1 (en) * | 2016-04-05 | 2018-07-05 | Boe Technology Group Co., Ltd. | Thin film transistor and method for manufacturing the same, array substrate and display device |
| CN111312731A (en) * | 2020-02-28 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
-
2021
- 2021-03-02 CN CN202110230986.1A patent/CN112951851B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08181325A (en) * | 1994-12-27 | 1996-07-12 | Sharp Corp | Manufacture of semiconductor element and manufacture of substrate for display device |
| CN1828963A (en) * | 2005-01-15 | 2006-09-06 | 三星Sdi株式会社 | A thin film transistor, a method for preparing the same and a flat panel display employing the same |
| CN105206570A (en) * | 2015-10-27 | 2015-12-30 | 深圳市华星光电技术有限公司 | Display panel and production method thereof |
| US20180190831A1 (en) * | 2016-04-05 | 2018-07-05 | Boe Technology Group Co., Ltd. | Thin film transistor and method for manufacturing the same, array substrate and display device |
| CN106981478A (en) * | 2017-04-07 | 2017-07-25 | 京东方科技集团股份有限公司 | Top gate type thin film transistor and preparation method thereof, array base palte, display panel |
| CN111312731A (en) * | 2020-02-28 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
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