CN112928162B - High electron mobility transistor epitaxial wafer and preparation method thereof - Google Patents

High electron mobility transistor epitaxial wafer and preparation method thereof Download PDF

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CN112928162B
CN112928162B CN202110048325.7A CN202110048325A CN112928162B CN 112928162 B CN112928162 B CN 112928162B CN 202110048325 A CN202110048325 A CN 202110048325A CN 112928162 B CN112928162 B CN 112928162B
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CN112928162A (en
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胡加辉
苏晨
李鹏
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract

The present disclosure provides a high electron mobility transistor epitaxial wafer and a preparation method thereof, which belong to the technical field of semiconductor devices. The high electron mobility transistor epitaxial wafer comprises a substrate, and a first composite layer and a second composite layer which are sequentially laminated on the substrate, wherein the first composite layer comprises AlN sublayers and first GaN sublayers which are alternately laminated on the substrate, the mobility of gallium atoms is higher during growth, the movement and growth of Al atoms with lower mobility in the AlN sublayers can be promoted, the overall growth quality of the first composite layer is ensured, and a good growth foundation is provided for the growth of a subsequent film. The InAlGaN sub-layers and the second GaN sub-layers are alternately laminated, the lattice constants of the InAlGaN sub-layers are located between the AlN sub-layers and the first GaN sub-layers, good transition from the first composite layer to the second composite layer can be achieved, and the overall quality of the epitaxial wafer of the high electron mobility transistor can be finally improved by improving the crystal quality of the bottom layer structure.

Description

High electron mobility transistor epitaxial wafer and preparation method thereof
Technical Field
The present disclosure relates to the field of semiconductor devices, and in particular, to a transistor epitaxial wafer with high electron mobility and a method for preparing the same.
Background
HEMTs (High Electron Mobility Transistor, high electron mobility transistors) are a type of heterojunction field effect transistor that is widely used in a variety of electrical appliances. The HEMT epitaxial wafer is a basis for preparing HEMT devices, and the current HEMT epitaxial wafer comprises a substrate, and an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer, an AlGaN barrier layer and a GaN cover layer which are sequentially laminated on the substrate, wherein the substrate can be a silicon carbide substrate, a sapphire substrate or a monocrystalline silicon substrate.
However, because larger lattice mismatch exists between the GaN layer and the silicon carbide substrate, the sapphire substrate or the monocrystalline silicon substrate, even if the AlN nucleation layer and the AlGaN buffer layer play a role in buffering between the substrate and the GaN layer, the crystal quality of the finally grown GaN layer is not good enough, and the quality of the HEMT is further affected.
Disclosure of Invention
The embodiment of the disclosure provides a high electron mobility transistor epitaxial wafer and a preparation method thereof, which can improve the crystal quality of the high electron mobility transistor epitaxial wafer so as to improve the quality of HEMTs. The technical scheme is as follows:
the embodiment of the disclosure provides a high electron mobility transistor epitaxial wafer, which comprises a substrate, and a first composite layer, a second composite layer, a GaN channel layer, an AlGaN barrier layer and a GaN cover layer which are sequentially laminated on the substrate, wherein the first composite layer comprises an AlN sub-layer and a first GaN sub-layer which are alternately laminated, and the second composite layer comprises an InAlGaN sub-layer and a second GaN sub-layer which are alternately laminated.
Optionally, the thickness of the AlN sub-layer is 5-20 nm, the thickness of the first GaN sub-layer is 5-20 nm, the thickness of the InAlGaN sub-layer is 10-30 nm, and the thickness of the second GaN sub-layer is 10-30 nm.
Optionally, the high electron mobility transistor epitaxial wafer further comprises a buffer GaN layer located between the second composite layer and the GaN channel layer.
Optionally, the thickness of the buffer GaN layer is 1 um-3 um.
Optionally, CCl is doped in the GaN buffer layer 4 。
Optionally, the high electron mobility transistor epitaxial wafer further comprises an AlN insertion layer located between the AlGaN barrier layer and the GaN cap layer.
Optionally, the thickness of the AlN intercalation layer is 0.5 nm-2 nm.
The embodiment of the disclosure provides a preparation method of a high electron mobility transistor epitaxial wafer, which comprises the following steps:
providing a substrate;
and sequentially growing a first composite layer, a second composite layer, a GaN channel layer, an AlGaN barrier layer and a GaN cover layer on the substrate, wherein the first composite layer comprises an AlN sub-layer and a first GaN sub-layer which are alternately laminated, and the second composite layer comprises an InAlGaN sub-layer and a second GaN sub-layer which are alternately laminated.
Optionally, the preparation method of the high electron mobility transistor epitaxial wafer further comprises the following steps:
and growing a buffer GaN layer between the second composite layer and the GaN channel layer, wherein the growth temperature of the buffer GaN layer gradually rises in the growth process of the buffer GaN layer.
Optionally, the difference between the highest growth temperature of the buffer GaN layer and the lowest growth temperature of the buffer GaN layer is 10 to 80 ℃.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that:
the high electron mobility transistor epitaxial wafer comprises a substrate, a first composite layer, a second composite layer, a GaN channel layer, an AlGaN barrier layer and a GaN cover layer which are sequentially laminated on the substrate. The first composite layer comprises an AlN sub-layer and a first GaN sub-layer which are alternately laminated on the substrate, the mobility of gallium atoms is higher during growth, the movement and growth of Al atoms with lower mobility in the AlN sub-layer can be promoted, the growth efficiency of the AlN sub-layer and the first GaN sub-layer is higher, the stress deposited by the AlN sub-layer and the first GaN sub-layer can be gradually released during growth of the AlN sub-layer and the first GaN sub-layer, the overall growth quality of the first composite layer is ensured, and a good growth foundation is provided for the growth of subsequent films. In the second composite layer laminated on the first composite layer, the InAlGaN sub-layer and the second GaN sub-layer which are alternately laminated can further release the stress accumulated by the first composite layer on one hand, ensure the quality of the second composite layer and provide a good growth foundation. The lattice constant of the InAlGaN sub-layer in the second composite layer is positioned between the AlN sub-layer and the first GaN sub-layer, so that good transition from the first composite layer to the second composite layer can be realized, the crystal quality of the second composite layer is improved, and the improvement of the crystal quality of the bottom layer structure can finally improve the overall quality of the high electron mobility transistor epitaxial wafer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a high electron mobility transistor epitaxial wafer according to an embodiment of the present disclosure;
FIG. 2 is a comparative graph of the composition of an InAlGaN sublayer provided by embodiments of the disclosure;
fig. 3 is a schematic structural diagram of another high electron mobility transistor epitaxial wafer provided in an embodiment of the present disclosure;
fig. 4 is a flowchart of a high electron mobility transistor epitaxial wafer and a method for manufacturing the same according to an embodiment of the present disclosure;
fig. 5 is a flowchart of another high electron mobility transistor epitaxial wafer and a method for fabricating the same according to an embodiment of the present disclosure.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a light emitting diode epitaxial wafer according to an embodiment of the present disclosure, as shown in fig. 1, where the embodiment of the present disclosure provides a high electron mobility transistor epitaxial wafer, and the high electron mobility transistor epitaxial wafer includes a substrate 1, and a first composite layer 2, a second composite layer 3, a GaN channel layer 4, an AlGaN barrier layer 5, and a GaN cap layer 6 sequentially stacked on the substrate 1, where the first composite layer 2 includes an AlN sub-layer 21 and a first GaN sub-layer 22 that are alternately stacked, and the second composite layer 3 includes an InAlGaN sub-layer 31 and a second GaN sub-layer 32 that are alternately stacked.
The high electron mobility transistor epitaxial wafer comprises a substrate 1, a first composite layer 2, a second composite layer 3, a GaN channel layer 4, an AlGaN barrier layer 5 and a GaN cap layer 6 which are sequentially laminated on the substrate 1. The first composite layer 2 comprises the AlN sub-layer 21 and the first GaN sub-layer 22 which are alternately laminated on the substrate 1, the mobility of gallium atoms is higher during growth, the movement and growth of Al atoms with lower mobility in the AlN sub-layer 21 can be promoted, the growth efficiency of the AlN sub-layer 21 and the first GaN sub-layer 22 is higher, the alternately laminated AlN sub-layer 21 and the first GaN sub-layer 22 can gradually release self-deposited stress during growth, the overall growth quality of the first composite layer 2 is ensured, and a good growth foundation is provided for the growth of subsequent films. In the second composite layer 3 laminated on the first composite layer 2, the InAlGaN sub-layers 31 and the second GaN sub-layers 32 are alternately laminated, so that on one hand, the stress accumulated by the first composite layer 2 can be further released, and meanwhile, the quality of the second composite layer 3 is ensured, and a good growth foundation is provided. The lattice constant of the InAlGaN sub-layer 31 in the second composite layer 3 is located between the AlN sub-layer 21 and the first GaN sub-layer 22, so that good transition from the first composite layer 2 to the second composite layer 3 can be realized, the crystal quality of the second composite layer 3 is improved, and the improvement of the crystal quality of the bottom layer structure can finally improve the overall quality of the high electron mobility transistor epitaxial wafer.
Illustratively, oxygen is also doped within AlN sub-layer 21 in first composite layer 2.
The AlN sub-layer 21 in the first composite layer 2 is doped with oxygen, so that lattice mismatch between the AlN sub-layer 21 and the first GaN sub-layer 22 can be reduced, and the overall quality of the first composite layer 2 can be improved.
Optionally, the thickness of the first composite layer 2 is smaller than the thickness of the second composite layer 3.
The thickness of the first composite layer 2 is smaller than that of the second composite layer 3, the first composite layer 2 realizes basic growth on the substrate 1, and the whole thickness of the first composite layer 2 is not excessively large in order to avoid excessive defects in the first composite layer 2. The second composite layer 3 having a large thickness is laminated on the first composite layer 2 to relieve stress, thereby improving the overall crystal quality. The second composite layer 3 itself has a sufficient thickness to release the stress, and the surface quality of the second composite layer 3 on the side close to the GaN channel layer 4 is better, whereby the quality of the GaN channel layer 4 itself grown on the second composite layer 3 can be ensured to be better.
Illustratively, the thickness of the first composite layer 2 as a whole may be 0.5um to 1.5um, and the thickness of the second composite layer 3 may be 1um to 3um.
When the thickness of the first composite layer 2 and the thickness of the second composite layer 3 are within the above ranges, the crystal quality of the finally obtained first composite layer 2 and second composite layer 3 is good, and the quality of the GaN channel layer 4 grown on the second composite layer 3 can be ensured to be also good.
In other implementations provided by the present disclosure, the thickness of the first composite layer 2 may also be less than 100nm, and the thickness of the second composite layer 3 may be less than 1.5um. The present disclosure is not limited in this regard.
Illustratively, the thickness of AlN sub-layer 21 may be less than the thickness of the first GaN sub-layer 22, and the thickness of InAlGaN sub-layer 31 may be less than the thickness of the second GaN sub-layer 32. It can be ensured that the GaN channel layer 4 laminated on the second composite layer 3 achieves good matching and growth with the second composite layer 3.
Alternatively, alN sublayer 21 has a thickness of 5 to 20nm, first GaN sublayer 22 has a thickness of 5 to 20, inAlGaN sublayer 31 has a thickness of 10 to 30, and second GaN sublayer 32 has a thickness of 10 to 30.
The thicknesses of all the sub-layers in the first composite layer 2 and all the sub-layers in the second composite layer 3 are within the above range, the quality of the sub-layers is stable, the effect of releasing stress of all the sub-layers during alternate cyclic growth is good, and the crystal quality of the finally obtained first composite layer 2 and second composite layer 3 can be further improved.
In one implementation provided by the present disclosure, the thickness of the InAlGaN sublayer 31 and the thickness of the second GaN sublayer 32 may each be 30nm. The present disclosure is not limited in this regard.
Alternatively, the number of layers of the AlN sub-layer 21 in the first composite layer 2 is 20 to 100, and the number of layers of the InAlGaN sub-layer 31 in the second composite layer 3 is 20 to 100.
The number of layers of the AlN sub-layer 21 and the number of layers of the InAlGaN sub-layer 31 are in the above range, so that the first composite layer 2 and the second composite layer 3 can be ensured to realize good release of stress, and the crystal quality of the finally obtained first composite layer 2 and second composite layer 3 can be ensured.
In one implementation provided by the present disclosure, the number of layers of AlN sub-layer 21 may be 3 and the number of layers of inalgan sub-layer 31 may be 5. The present disclosure is not limited in this regard.
Alternatively, in the second composite layer 3, the Al composition In the InAlGaN sublayer 31 is graded, and the sum of the Al composition, ga composition, and In composition is 1. To adjust the quality and barrier of the InAlGaN sublayer 31.
In one implementation of this embodiment, in the second composite layer 3, the Al composition of the InAlGaN sublayer 31 increases in gradient along the growth direction of the transition layer.
In another implementation of this embodiment, in the second composite layer 3, the Al composition of the InAlGaN sublayer 31 increases and decreases along the growth direction of the transition layer.
In yet another implementation of this embodiment, in the second composite layer 3, the Al composition of the InAlGaN sublayer 31 decreases and then increases along the growth direction of the transition layer.
In yet another implementation of this embodiment, in the second composite layer 3, the gradient of the Al composition of the InAlGaN sublayer 31 along the growth direction of the transition layer is reduced.
For ease of understanding, fig. 2 is provided herein, and fig. 2 is a comparative diagram of the composition of the InAlGaN sublayer provided in the embodiments of the present disclosure, and referring to fig. 2, the barrier of the InAlGaN sublayer 31 gradually increases as the Al composition increases in gradient along the growth direction of the transition layer, gradually increases and then decreases as the Al composition increases and then decreases in gradient along the growth direction of the transition layer, gradually decreases and then increases as the Al composition decreases in gradient along the growth direction of the transition layer, and gradually decreases as the Al composition decreases in gradient along the growth direction of the transition layer in four diagrams from left to right in fig. 2.
In one implementation provided by the present disclosure, the number of layers of the InAlGaN sublayer 31 In the second composite layer 3 is 5, and the Al composition of the InAlGaN sublayer 31 may be 40%, 35%, 30%, 25%, 20%, the content of In composition of each layer is uniform and is 15%,
fig. 3 is a schematic structural diagram of another high electron mobility transistor epitaxial wafer according to an embodiment of the present disclosure, referring to fig. 3, it can be seen that the high electron mobility transistor epitaxial wafer may include a substrate 1, a first composite layer 2, a second composite layer 3, a GaN buffer layer 7, a GaN channel layer 4, an AlN interlayer 8, an AlGaN barrier layer 5 and a GaN cap layer 6 sequentially stacked on the substrate 1, the first composite layer 2 includes an AlN sub-layer 21 and a first GaN sub-layer 22 alternately stacked, and the second composite layer 3 includes an InAlGaN sub-layer 31 and a second GaN sub-layer 32 alternately stacked.
It should be noted that, the structures of the first composite layer 2 and the second composite layer 3 shown in fig. 3 are the same as the structures of the first composite layer 2 and the second composite layer 3 shown in fig. 1, and are not described herein.
In fig. 3, compared with fig. 1, a GaN buffer layer 7 is added between the second composite layer 3 and the GaN channel layer 4, so that the transition from the second composite layer 3 to the GaN channel layer 4 can be realized to improve the growth quality of the GaN channel layer 4.
Optionally, the thickness of the buffer GaN layer is 1um to 3um.
When the thickness of the buffer GaN layer is within the above range, lattice mismatch between the second composite layer 3 and the GaN channel layer 4 can be effectively relieved, the buffer GaN layer serves as a transition layer, good butt joint with the GaN channel layer 4 can be realized, and crystal quality of the finally obtained GaN channel layer 4 is improved.
In one implementation provided by the present disclosure, the thickness of the buffer GaN layer may be 300nm. The present disclosure is not limited in this regard.
Illustratively, the GaN buffer layer 7 has CCl incorporated therein 4 。
CCl doped in GaN buffer layer 7 4 The resistance value of the GaN buffer layer 7 can be improved, the possibility of leakage of the high electron mobility transistor epitaxial wafer can be reduced, a certain current expansion effect is provided, and the quality of the finally obtained high electron mobility transistor epitaxial wafer is ensured.
Optionally, the concentration of C doped in the GaN buffer layer 7 is 9e1018 to 5e1019.
CCl 4 The concentration of the (B) is in the above range, the crystal quality of the GaN buffer layer 7 is not excessively influenced, the leakage condition of the high electron mobility transistor epitaxial wafer is effectively controlled, and the quality of the high electron mobility transistor epitaxial wafer is greatly improved as a whole.
The GaN buffer layer 7 may have a thickness of 15 to 40nm, for example. The obtained GaN buffer layer 7 has better quality and better effect of relieving lattice mismatch.
Alternatively, the thickness of the GaN channel layer 4 may be 100 to 400nm.
The GaN channel layer 4 has proper thickness and reasonable cost, and can effectively improve the quality of the high electron mobility transistor epitaxial wafer.
In one implementation provided by the present disclosure, the GaN channel layer 4 may have a thickness of 400nm. The present disclosure is not limited in this regard.
In fig. 3, compared with fig. 1, an AlN insertion layer is added between the AlGaN barrier layer and the GaN channel layer, so that two-dimensional electron gas can be formed at the interface between the AlN insertion layer and the GaN channel layer, and the interface between the AlN insertion layer and the AlGaN barrier layer, and the accumulation of carriers at the interface can be increased by the two-dimensional electron gas, so that the use effect of the high electron mobility transistor epitaxial wafer can be ensured.
Alternatively, the AlN intercalated layer has a thickness of 0.5 to 2nm.
The thickness of the AlN insertion layer is within the above range, the two-dimensional electron gas can be effectively traveled, and the cost is not excessively increased.
In one implementation provided by the present disclosure, the AlN insertion layer may have a thickness of 2nm. The present disclosure is not limited in this regard.
Alternatively, the AlGaN barrier layer may have a thickness of 15-40 nm. The quality of the high electron mobility transistor epitaxial wafer can be ensured.
In one implementation provided by the present disclosure, the AlGaN barrier layer may have a thickness of 100nm. The present disclosure is not limited in this regard.
The GaN cap layer may be a P-type GaN layer, for example. Is convenient for preparation and acquisition.
Optionally, the GaN cap layer has a thickness of 300nm. The obtained GaN cap layer has better overall quality.
Illustratively, the impurity within the GaN cap layer is Mg. Is convenient for preparation and acquisition.
It should be noted that fig. 3 is only one implementation of the hemt epitaxial wafer provided in the embodiments of the present disclosure, and in other implementations provided in the present disclosure, the hemt epitaxial wafer may be another form of hemt epitaxial wafer including the reflective layer 5, which is not limited in this disclosure.
Referring to fig. 3, the high electron mobility transistor epitaxial wafer may further include a gate electrode, a source electrode and a drain electrode, wherein the gate electrode is located on and connected to the GaN cap layer, and the source electrode and the drain electrode are spaced apart on the AlGaN barrier layer.
Fig. 4 is a flowchart of a method for preparing an epitaxial wafer of a high electron mobility transistor according to an embodiment of the present disclosure, where, as shown in fig. 4, the method for preparing an epitaxial wafer of a high electron mobility transistor includes:
s101: a substrate is provided.
S102: and sequentially growing a first composite layer, a second composite layer, a GaN channel layer, an AlGaN barrier layer and a GaN cover layer on the substrate, wherein the first composite layer comprises an AlN sub-layer and a first GaN sub-layer which are alternately laminated, and the second composite layer comprises an InAlGaN sub-layer and a second GaN sub-layer which are alternately laminated.
It should be noted that the technical effects of the method shown in fig. 3 may refer to the technical effects of the high electron mobility transistor epitaxial wafer shown in fig. 1, and thus will not be described herein.
The structure of the high electron mobility transistor epitaxial wafer after the completion of step S102 can be seen in fig. 1.
Fig. 5 is a flowchart of another method for preparing an epitaxial wafer of a high electron mobility transistor according to an embodiment of the present disclosure, where, as shown in fig. 5, the method for preparing an epitaxial wafer of a high electron mobility transistor includes:
s201: a substrate is provided.
Alternatively, the substrate has a size of 2inch to 10inch. The epitaxial wafer of the transistor with high electron mobility and reasonable size can be obtained.
S202: and baking and bombarding the substrate sequentially.
Impurities on the surface of the substrate can be removed and the polarity of the surface of the substrate can be changed. The crystal quality of the second composite layer grown on the substrate is improved.
Optionally, baking the substrate in vacuum environment for 1-20 min at 200-900 deg.c under pressure less than 10 -7 torr。
And the substrate is baked under the condition in the last section, so that most of impurities on the substrate can be cleaned, and the quality of the second composite layer grown on the substrate is ensured.
Illustratively, ion bombardment of the substrate includes:
and bombarding the surface of the substrate by nitrogen plasma in a pure nitrogen atmosphere, covering a layer of nitrogen atoms on the surface of the substrate, and changing the polarity of the surface of the substrate. And adhesion and growth on the surface of the substrate in the first composite layer are facilitated. And after baking, the surface atoms of the substrate are more active, so that partial nitrogen atoms can be ensured to stably permeate into the surface of the substrate, and the efficiency of polarity change is improved.
Optionally, the power of the plasma bombardment is 30-100W, the bombardment time is 1-20 min, and the bombardment temperature is 300-800 ℃. It is possible to ensure that the surface of the substrate rapidly accumulates nitrogen atoms.
S203: a first composite layer is grown on a substrate.
Alternatively, the first composite layer may be obtained by physical vapor deposition. The surface flatness and the overall quality of the first composite layer can be ensured.
Optionally, the first composite layer is at O 2 In the atmosphere of mixed gas of Ar and N2, the deposition temperature is 300-800 ℃, the deposition pressure is 1-10 mtorr, the sputtering power is 1 kw-10 kw, and the sputtering time is 10 s-1000 s.
Under the condition of the last section, the first composite layer doped with oxygen can be obtained, the lattice mismatch between the first composite layer and the substrate is smaller, and the quality of the first composite layer is improved to a certain extent.
S204: and growing a second composite layer on the first composite layer.
Alternatively, the second composite layer may be grown under pure nitrogen atmosphere, and in the second composite layer, the InAlGaN sub-layer is grown at 940 ℃ and the second GaN sub-layer is grown at 980 ℃.
S205: and growing a GaN buffer layer on the second composite layer.
Step S205 may include: during the growth of the buffer GaN layer, the growth temperature of the buffer GaN layer gradually increases.
The growth temperature of the buffer GaN layer is gradually increased, the buffer GaN layer can achieve good contact and transition with the InAlGaN sub-layer In the second composite layer with In elements, in elements In the InAlGaN sub-layer are prevented from being separated out into the buffer GaN layer, the crystal quality of the buffer GaN layer is affected, the temperature of the part, close to the GaN channel layer, of the buffer GaN layer is higher, the quality of the part, close to the GaN channel layer, of the buffer GaN layer is better, and good growth of the GaN channel layer can be guaranteed.
In one implementation provided by the present disclosure, the temperature of the buffer GaN layer may be stepped up. And can be raised from 1000 ℃ to 1020 ℃ and then raised from 1020 ℃ to 1040 ℃.
Step S205 may further include: when the buffer GaN layer grows, CCl with 200-600 sccm is introduced into the reaction cavity 4 . Enough carbon elements can be ensured to be doped in the buffer GaN layer, and the effect of preventing leakage and expanding current is achieved.
S206: and growing a GaN channel layer on the GaN buffer layer.
Alternatively, the growth temperature of the GaN channel layer is 1000 ℃ to 1200 ℃. The quality of the obtained GaN channel layer is better.
In one implementation provided by the present disclosure, the growth temperature of the GaN channel layer may be 1040 ℃. The present disclosure is not limited in this regard.
S207: an AlN insert layer is grown on the GaN channel layer.
Alternatively, the AlN insert layer is grown at 900-1100 deg.C and at 50-150 torr. An AlN intercalation layer of good quality can be obtained.
S208: an AlGaN barrier layer is grown on the AlN insert layer.
Alternatively, the growth temperature of the AlGaN barrier layer is 1000 ℃ to 1200 ℃. The quality of the obtained AlGaN barrier layer is better.
In one implementation provided by the present disclosure, the growth temperature of the AlGaN barrier layer may be 1020 ℃. The present disclosure is not limited in this regard.
S209: and growing a GaN cover layer on the AlGaN barrier layer.
Alternatively, the growth temperature of the GaN cap layer is 1000 ℃ to 1200 ℃. The quality of the obtained GaN cap layer is better.
In one implementation provided by the present disclosure, the growth temperature of the GaN cap layer may be 970 ℃. The present disclosure is not limited in this regard.
It should be noted that in the embodiments of the present disclosure, veecoK465iorC4orRBMOCVD (Metalorganic)Chemical vapor deposition, metal organic chemical vapor deposition) equipment to achieve the growth method of LEDs. Adopts high-purity H 2 (Hydrogen) or high purity N 2 (Nitrogen) or high purity H 2 And high purity N 2 High purity NH using the mixed gas of (2) as carrier gas 3 As N source, trimethylgallium (TMGa) and triethylgallium (TEGa) as gallium source, trimethylindium (TMIn) as indium source, silane (SiH 4) as N-type dopant, trimethylaluminum (TMAL) as aluminum source, magnesium-cyclopentadienyl (CP 2 Mg) as P-type dopant.
The foregoing disclosure is not intended to be limited to any form of embodiment, but is not intended to limit the disclosure, and any simple modification, equivalent changes and adaptations of the embodiments according to the technical principles of the disclosure are intended to be within the scope of the disclosure, as long as the modifications or equivalent embodiments are possible using the technical principles of the disclosure without departing from the scope of the disclosure.

Claims (10)

1. The high electron mobility transistor epitaxial wafer is characterized by comprising a substrate, a first composite layer, a second composite layer, a GaN channel layer, an AlGaN barrier layer and a GaN cover layer, wherein the first composite layer, the second composite layer, the GaN channel layer, the AlGaN barrier layer and the GaN cover layer are sequentially laminated on the substrate, the first composite layer comprises an AlN sub-layer and a first GaN sub-layer which are alternately laminated, the second composite layer comprises an InAlGaN sub-layer and a second GaN sub-layer which are alternately laminated, and the substrate is a silicon carbide substrate, a sapphire substrate or a monocrystalline silicon substrate.
2. The hemt epitaxial wafer of claim 1, wherein the AlN sub-layer has a thickness of 5-20 nm, the first GaN sub-layer has a thickness of 5-20 nm, the InAlGaN sub-layer has a thickness of 10-30 nm, and the second GaN sub-layer has a thickness of 10-30 nm.
3. The high electron mobility transistor epitaxial wafer of claim 1, further comprising a buffer GaN layer between the second composite layer and the GaN channel layer.
4. The hemt epitaxial wafer of claim 3, wherein the buffer GaN layer has a thickness of 1um to 3um.
5. The hemt epitaxial wafer of claim 3, wherein CCl is doped in said buffer GaN layer 4 。
6. The hemt epitaxial wafer of any one of claims 1-5, further comprising an AlN insertion layer between said AlGaN barrier layer and said GaN cap layer.
7. The high electron mobility transistor epitaxial wafer of claim 6, wherein the AlN insertion layer has a thickness of 0.5nm to 2nm.
8. The preparation method of the high electron mobility transistor epitaxial wafer is characterized by comprising the following steps of:
providing a substrate;
and sequentially growing a first composite layer, a second composite layer, a GaN channel layer, an AlGaN barrier layer and a GaN cover layer on the substrate, wherein the first composite layer comprises an AlN sub-layer and a first GaN sub-layer which are alternately laminated, the second composite layer comprises an InAlGaN sub-layer and a second GaN sub-layer which are alternately laminated, and the substrate is a silicon carbide substrate, a sapphire substrate or a monocrystalline silicon substrate.
9. The method of manufacturing a high electron mobility transistor epitaxial wafer according to claim 8, further comprising:
and growing a buffer GaN layer between the second composite layer and the GaN channel layer, wherein the growth temperature of the buffer GaN layer gradually rises in the growth process of the buffer GaN layer.
10. The method of claim 9, wherein the difference between the highest growth temperature of the buffer GaN layer and the lowest growth temperature of the buffer GaN layer is 10 ℃ to 80 ℃.
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