CN112910590B - Clock synchronization system and method - Google Patents
Clock synchronization system and method Download PDFInfo
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- CN112910590B CN112910590B CN202110121419.2A CN202110121419A CN112910590B CN 112910590 B CN112910590 B CN 112910590B CN 202110121419 A CN202110121419 A CN 202110121419A CN 112910590 B CN112910590 B CN 112910590B
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Abstract
The invention discloses a clock synchronization system and a clock synchronization method, wherein the system comprises a main control board, at least one service board slot and at least one service board, wherein the main control board is provided with at least one communication interface, and the communication interfaces are electrically connected with the service board slot in a one-to-one correspondence manner through a back board bus; the service boards are correspondingly spliced with the service board slots one by one; the service board comprises a clock recovery module and an adjusting value calculation module; the output end of the clock recovery module is electrically connected with the first input end of the adjustment value calculation, the output end of the main control board is connected with the second input end of the adjustment value calculation, and the input end of the main control board is connected with the output end of the adjustment value calculation; the master control board and the service board slot adopt the backboard bus to transmit the clock and the adjustment value, no additional clock signal line is needed to be arranged, the signal line resource is saved, meanwhile, the clock adjustment and evaluation function can be realized on the service board of any service board slot, the master control board selects the clock and the adjustment value, the dynamic expansion is realized, and the slot resource is saved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a clock synchronization system and method.
Background
In a communication system, communication devices are networked in a hierarchical fashion, e.g., national level communication devices are first level, provincial level communication devices are second level, urban level communication devices are third level, and so on. The clock synchronization of the whole network is realized by a stage-down transfer, for example, the communication device of one stage directly synchronizes the clock with the satellite, and then the communication device of the next stage synchronizes the clock with the communication device of the previous stage.
At present, in order to improve the convenience of networking and reduce the overhead, the communication device at the next stage is generally synchronized with the clock recovered from the communication signal, but as the network becomes more complex and the requirement for the clock source becomes more complex, the traditional scheme for realizing clock synchronization by using a dedicated phase-locked loop chip has no expansibility, and in order to realize the clock input channels of a plurality of channels, sufficient slot positions and signal line resources need to be distributed on a main control board and a back board, which results in resource waste.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a clock synchronization system and method, which can effectively implement dynamic expansion of clock synchronization and save slot and signal line resources.
In a first aspect, an embodiment of the present invention provides a clock synchronization system, including: the system comprises a main control board, at least one service board slot and at least one service board, wherein the main control board is provided with at least one communication interface which is electrically connected with the service board slot in a one-to-one correspondence manner through a backboard bus; the service boards are correspondingly spliced with the service board slots one by one; the service board comprises a clock recovery module and an adjusting value calculation module; the output end of the clock recovery module is electrically connected with the first input end of the adjustment value calculation, the output end of the main control board is connected with the second input end of the adjustment value calculation, and the input end of the main control board is connected with the output end of the adjustment value calculation; wherein, the first and the second end of the pipe are connected with each other,
the clock recovery module is used for recovering a reference clock from a received communication signal transmitted by superior communication equipment and sending the reference clock to the adjustment value calculation module;
the main control board is used for sending a local system clock to the adjusting value calculating module;
the adjusting value calculating module is used for calculating an adjusting value according to the reference clock and the local system clock and sending the adjusting value to the main control board;
the main control board is used for selecting an adjustment value from adjustment values output by the adjustment value calculation module of at least one service board and adjusting a local system clock according to the selected adjustment value.
As an improvement of the above scheme, the adjustment value calculation module includes a phase discriminator module and an adjustment value evaluation module; a first input end of the phase discriminator module is electrically connected with a first input end of the adjustment value calculation, a second input end of the phase discriminator module is electrically connected with a second input end of the adjustment value calculation, an output end of the phase discriminator module is connected with an input end of the adjustment value evaluation module, and an output end of the adjustment value evaluation module is electrically connected with an output end of the adjustment value calculation; wherein the content of the first and second substances,
the phase discriminator module is used for detecting the phase difference between the reference clock and the local system clock and sending the phase difference to the adjustment value evaluation module;
and the adjustment value evaluation module is used for calculating an adjustment value according to the phase difference and sending the adjustment value to the main control board.
As an improvement of the above scheme, the service board further includes: the first frequency reduction module and the second frequency reduction module; the first frequency reduction module is connected between the output end of the clock recovery module and the first input end of the phase detector module, and the second frequency reduction module is connected between the output end of the main control board and the second input end of the phase detector module; wherein, the first and the second end of the pipe are connected with each other,
the first frequency reduction module is used for reducing the frequency of the received reference clock to a first set frequency; the second frequency reduction module is used for reducing the frequency of the received local system clock to the first set frequency.
As an improvement of the above scheme, the main control board comprises a main processor and a program control clock module; the input end of the main processor is electrically connected with the input end of the main control board, the output end of the main processor is electrically connected with the input end of the program-controlled clock module, and the output end of the program-controlled clock module is electrically connected with the output end of the main control board; wherein the content of the first and second substances,
the main processor is used for selecting an adjusting value from adjusting values output by the adjusting value calculating module of at least one service board and sending the selected adjusting value to the program control clock module;
and the program control clock module is used for adjusting a local system clock according to the adjustment value and sending the adjusted local system clock to the phase discriminator module.
As an improvement of the above scheme, the program-controlled clock module includes: the system comprises a secondary processor, a digital-to-analog converter and a voltage-controlled crystal oscillator; the input end of the auxiliary processor is electrically connected with the input end of the program control clock module, the output end of the auxiliary processor is electrically connected with the input end of the digital-to-analog converter, the output end of the digital-to-analog converter is electrically connected with the input end of the voltage-controlled crystal oscillator, and the output end of the voltage-controlled crystal oscillator is electrically connected with the output end of the program control clock module;
the secondary processor is used for outputting a set value to the digital-to-analog converter;
the digital-to-analog converter is used for converting the set value into a voltage value and sending the voltage value to the voltage-controlled crystal oscillator;
and the voltage-controlled crystal oscillator is used for outputting a local system clock with a second set frequency according to the voltage value, and adjusting the local system clock according to the adjustment value when receiving the adjustment value.
As an improvement of the above scheme, the adjustment value evaluation module includes a filtering processor, an integration processor and a comparison processor;
the filtering processor is used for calculating the variation of the phase difference of a set time period and performing smooth filtering processing on the variation to obtain a frequency difference value in the set time period;
the integration processor is used for integrating the frequency difference value in the set time period to obtain an integral value;
the comparison processor is used for calculating the product of the integral value and a preset proportional value to obtain a candidate adjusting value, and comparing the candidate adjusting value with a set maximum value and a set minimum value; when the candidate adjustment value is larger than the set maximum value, outputting the set maximum value as an adjustment value; when the candidate adjustment value is smaller than the set minimum value, outputting the set minimum value as an adjustment value; outputting the candidate adjustment value as an adjustment value when the candidate adjustment value is between the set maximum value and the set minimum value.
In a second aspect, an embodiment of the present invention provides a clock synchronization method, which is performed by a clock synchronization system, where the clock synchronization system includes: the system comprises a main control board, at least one service board slot and at least one service board, wherein the main control board is provided with at least one communication interface which is electrically connected with the service board slot in a one-to-one correspondence manner through a backboard bus; the service boards are correspondingly spliced with the service board slots one by one; the service board comprises a clock recovery module and an adjusting value calculation module; the output end of the clock recovery module is electrically connected with the first input end of the adjustment value calculation, the output end of the main control board is connected with the second input end of the adjustment value calculation, and the input end of the main control board is connected with the output end of the adjustment value calculation;
the method comprises the following steps:
the clock recovery module recovers a reference clock from a received communication signal transmitted by superior communication equipment and sends the reference clock to the adjustment value calculation module;
the main control board sends a local system clock to the adjusting value calculating module;
the adjusting value calculating module calculates an adjusting value according to the reference clock and the local system clock and sends the adjusting value to the main control board;
and the main control board selects an adjusting value from adjusting values output by the adjusting value calculating module of at least one service board, and adjusts the local system clock according to the selected adjusting value.
As an improvement of the above scheme, the adjustment value calculation module includes a phase discriminator module and an adjustment value evaluation module; a first input end of the phase discriminator module is electrically connected with a first input end of the adjustment value calculation, a second input end of the phase discriminator module is electrically connected with a second input end of the adjustment value calculation, an output end of the phase discriminator module is connected with an input end of the adjustment value evaluation module, and an output end of the adjustment value evaluation module is electrically connected with an output end of the adjustment value calculation;
the adjusting value calculating module calculates an adjusting value according to the reference clock and the local system clock, and sends the adjusting value to the main control board, including:
the phase discriminator module detects the phase difference between the reference clock and the local system clock and sends the phase difference to the adjustment value evaluation module;
and the adjustment value evaluation module calculates an adjustment value according to the phase difference and sends the adjustment value to the main control board.
As an improvement of the above scheme, the main control board comprises a main processor and a program control clock module; the input end of the main processor is electrically connected with the input end of the main control board, the output end of the main processor is electrically connected with the input end of the program-controlled clock module, and the output end of the program-controlled clock module is electrically connected with the output end of the main control board;
the main control board selects an adjustment value from adjustment values output by the adjustment value calculation module of at least one service board, and adjusts a local system clock according to the selected adjustment value, including:
the main processor selects an adjusting value from adjusting values output by an adjusting value calculation module of at least one service board and sends the selected adjusting value to the program control clock module;
and the program control clock module adjusts a local system clock according to the adjustment value and sends the adjusted local system clock to the phase discriminator module.
As an improvement of the above scheme, the adjustment value evaluation module includes a filtering processor, an integration processor and a comparison processor;
the adjustment value evaluation module calculates an adjustment value according to the phase difference and sends the adjustment value to the main control board, and the method comprises the following steps:
the filtering processor calculates the variation of the phase difference of a set time period and carries out smooth filtering processing on the variation to obtain a frequency difference value in the set time period;
the integration processor integrates the frequency difference value in the set time period to obtain an integration value;
the comparison processor calculates the product of the integral value and a preset proportional value to obtain a candidate adjustment value, and compares the candidate adjustment value with a set maximum value and a set minimum value; when the candidate adjustment value is larger than the set maximum value, outputting the set maximum value as an adjustment value; when the candidate adjustment value is smaller than the set minimum value, outputting the set minimum value as an adjustment value; outputting the candidate adjustment value as an adjustment value when the candidate adjustment value is between the set maximum value and the set minimum value.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: the system comprises a main control board, at least one service board slot and at least one service board, wherein the main control board is provided with at least one communication interface which is electrically connected with the service board slot in a one-to-one correspondence manner through a back board bus; the service boards are correspondingly spliced with the service board slots one by one; the service board comprises a clock recovery module and an adjusting value calculation module; the output end of the clock recovery module is electrically connected with the first input end of the adjustment value calculation, the output end of the main control board is connected with the second input end of the adjustment value calculation, and the input end of the main control board is connected with the output end of the adjustment value calculation; the clock recovery module is used for recovering a reference clock from a received communication signal transmitted by superior communication equipment and sending the reference clock to the adjusting value calculation module; the main control board is used for sending a local system clock to the adjusting value calculating module; the adjusting value calculating module is used for calculating an adjusting value according to the reference clock and the local system clock and sending the adjusting value to the main control board; the main control board is used for selecting an adjusting value from adjusting values output by the adjusting value calculating module of at least one service board and adjusting the local system clock according to the selected adjusting value. The master control board and the service board slot adopt the backplane bus to transmit the clock and the adjustment value, no additional clock signal line is needed to be arranged, the signal line resource is saved, meanwhile, the clock adjustment and evaluation function can be realized on the service board of any service board slot, the master control board is used for selection, the dynamic expansion is realized, and the slot resource is saved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art clock synchronization system based on a dedicated phase-locked loop chip;
fig. 2 is a schematic diagram of a slot connection between a main control board and a service board according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a clock synchronization system provided by a first embodiment of the present invention;
FIG. 4 is a schematic block diagram of the clock synchronization system of FIG. 3;
FIG. 5 is a schematic of the phase difference of the local system clock being slower than the reference clock;
FIG. 6 is a schematic of the phase difference of a local system clock being faster than a reference clock;
FIG. 7 is a schematic of the phase difference between the local system clock and the reference clock;
fig. 8 is a flowchart of a clock synchronization method according to a second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2-4, a clock synchronization system according to a first embodiment of the present invention includes: the system comprises a main control board 1, at least one service board slot position 3 and at least one service board 2, wherein the main control board 1 is provided with at least one communication interface which is electrically connected with the service board slot position 3 in a one-to-one correspondence manner through a backboard bus; the service boards 2 are correspondingly spliced with the service board slots 3 one by one; the service board 2 comprises a clock recovery module 21 and an adjustment value calculation module 22; the output end of the clock recovery module 21 is electrically connected with the first input end of the adjustment value calculation, the output end of the main control board 1 is connected with the second input end of the adjustment value calculation, and the input end of the main control board 1 is connected with the output end of the adjustment value calculation; wherein the content of the first and second substances,
the clock recovery module 21 is configured to recover a reference clock from a received communication signal transmitted by a higher-level communication device, and send the reference clock to the adjustment value calculation module 22;
the main control board 1 is configured to send a local system clock to the adjustment value calculation module 22;
the adjustment value calculating module 22 is configured to calculate an adjustment value according to the reference clock and the local system clock, and send the adjustment value to the main control board 1;
the main control board 1 is configured to select an adjustment value from adjustment values output by the adjustment value calculation module 22 of at least one service board 2, and adjust a local system clock according to the selected adjustment value.
In the embodiment of the present invention, the service board slot 3 is disposed on the backplane, and a backplane bus is used between the main control board 1 and the service board slot 3 to transmit the clock and the adjustment value, which does not depend on a dedicated clock input channel of the backplane and does not need to set an additional clock signal line, thereby reducing the number of signal lines between the main control board 1 and the backplane, and saving signal line resources, and simplifying the design of the system due to the reduction of signal line requirements; in addition, any one of the service boards 2 can be selectively plugged in any one of the service board slots 3, the service board 2 is powered on through the main control board 1, then the clock adjustment and evaluation function can be realized on the service board 2 of any service board slot 3, the main control board 1 is used for selection, dynamic expansion is realized, and slot resources are saved.
The clock recovery module 21 transmits communication signals with a higher-level communication system via an encoded data transmission channel, for example, an E1 transmission channel. The clock recovery module 21 realizes symbol synchronization and reference clock recovery by determining symbol hopping after receiving a communication signal, and specifically, the clock recovery module 21 may be a PHY (physical interface transceiver) chip employing corresponding coding.
In an alternative embodiment, the adjustment value calculation module 22 includes a phase detector module 221 and an adjustment value evaluation module 222; a first input end of the phase detector module 221 is electrically connected to a first input end of the adjustment value calculation, a second input end of the phase detector module 221 is electrically connected to a second input end of the adjustment value calculation, an output end of the phase detector module 221 is connected to an input end of the adjustment value evaluation module 222, and an output end of the adjustment value evaluation module 222 is electrically connected to an output end of the adjustment value calculation; wherein, the first and the second end of the pipe are connected with each other,
the phase detector module 221 is configured to detect a phase difference between the reference clock and the local system clock, and send the phase difference to the adjustment value evaluation module 222;
the adjustment value evaluation module 222 is configured to calculate an adjustment value according to the phase difference, and send the adjustment value to the main control board 1.
In this embodiment of the present invention, the phase detector module 221 may be implemented by using an MCU, and the phase detector module 221 is provided with two input ends, one of which is used to receive the reference clock sent by the clock recovery module 21, and the other is used to receive the local system clock sent by the main control board 1. Measuring the phase difference between the reference clock and the local system clock by using a local counter of the high-frequency clock; when the falling edge of the reference clock arrives, clearing the counter and starting counting; when the falling edge of the local system clock arrives, the counter is turned off, and the count value of the counter is read and output to the adjustment value evaluation module 222 as the phase difference.
The adjustment value evaluation module 222 may be implemented by an MCU, and calculates an adjustment value after receiving the phase difference sent by the phase detector module 221. As shown in fig. 5, when the local system clock is slower than the reference clock, the amount of change in the phase difference is a positive number; as shown in fig. 6, when the local system clock is faster than the reference clock, the amount of change in the phase difference is negative; as shown in fig. 7, when the local system clock is synchronized with the reference clock, the amount of change in the phase difference is 0.
The adjustment value evaluation module 222 performs sliding window smoothing filtering on the variation of the phase difference to obtain a relatively smooth frequency difference value, and filters out accidental clock jitter to avoid overflow and jitter of a following algorithm; then, integrating the frequency difference value, and counting the frequency difference value within a set time period (for example, 1s-10 s) to realize the suppression of clock jitter; finally, multiplying a preset proportional value to obtain a candidate adjusting value; wherein, the preset proportion value is determined by the adjusting speed of the clock. If the output is within the range of the set maximum value and the set minimum value, the output is directly output, if the output is greater than the set maximum value, the output is set maximum value, if the output is less than the set minimum value, the output is set minimum value, thereby realizing adjustable adjustment steps and ensuring that the system clock is relatively stable in the adjusting process. Finally, the value output by the adjustment value evaluation module 222 is transmitted to the main control board 1 through a backplane bus as a regulation value. The instantaneous jitter and the long-time jitter are filtered by using a sliding window smoothing filtering algorithm and an integral algorithm, and a system clock is more stable in a clock synchronization process.
In an optional embodiment, the service board 2 further includes: a first downconversion module 23 and a second downconversion module 24; the first down-conversion module 23 is connected between the output end of the clock recovery module 21 and the first input end of the phase detector module 221, and the second down-conversion module 24 is connected between the output end of the main control board 1 and the second input end of the phase detector module 221; wherein, the first and the second end of the pipe are connected with each other,
the first frequency-reducing module 23 is configured to reduce the frequency of the received reference clock to a first set frequency;
the second frequency-reducing module 24 is used for reducing the frequency of the received local system clock to the first set frequency.
In the embodiment of the present invention, the first frequency-reducing module and the second frequency-reducing module can be implemented by using a programmable logic device (FPGA). The first frequency reducing module is used for reducing the frequency of the received reference clock to a first set frequency, and the second frequency reducing module is used for reducing the frequency of the received local system clock to the first set frequency, so that the frequencies of the reference clock and the local system clock can be reduced to the same frequency, the higher or inconsistent proportion of the two clocks can be avoided, and the output frequency is low enough, such as 500HZ, so that the phase discriminator module 221 can compare the phase difference.
In an alternative embodiment, the main control board 1 includes a main processor 11, a programmable clock module 12; the input end of the main processor 11 is electrically connected with the input end of the main control board 1, the output end of the main processor 11 is electrically connected with the input end of the program-controlled clock module 12, and the output end of the program-controlled clock module 12 is electrically connected with the output end of the main control board 1; wherein, the first and the second end of the pipe are connected with each other,
the main processor 11 is configured to select an adjustment value from adjustment values output by the adjustment value calculation module 22 of at least one service board 2, and send the selected adjustment value to the program-controlled clock module 12;
the program-controlled clock module 12 is configured to adjust a local system clock according to the adjustment value, and send the adjusted local system clock to the phase detector module 221.
In the embodiment of the present invention, the main processor 11 may adopt a CPU processor of an x86 architecture, an ARM architecture, or other architectures, and is configured to process normal services and also configured to implement clock source selection and control of the program-controlled clock module 12. The main processor 11 receives the adjustment values sent from the service boards 2 in the plurality of slot positions at the same time, and then selects the adjustment value output by one of the service boards 2 from the service boards 2 in the N slot positions according to a preset dynamic selection rule, thereby realizing the dynamically expandable function. For example, when the service board 2 of a slot is disconnected from the main control board 1, the service board 2 of another slot may be switched to obtain the adjustment value of the clock.
In an alternative embodiment, the programmable clock module 12 comprises: a secondary processor 121, a digital-to-analog converter 122 and a voltage controlled crystal oscillator 123; the input end of the secondary processor 121 is electrically connected to the input end of the program-controlled clock module 12, the output end of the secondary processor 121 is electrically connected to the input end of the digital-to-analog converter 122, the output end of the digital-to-analog converter 122 is electrically connected to the input end of the voltage-controlled crystal oscillator 123, and the output end of the voltage-controlled crystal oscillator 123 is electrically connected to the output end of the program-controlled clock module 12;
the secondary processor 121 is configured to output a setting value to the digital-to-analog converter 122;
the digital-to-analog converter 122 is configured to convert the setting value into a voltage value, and send the voltage value to the voltage controlled crystal oscillator 123;
the vcxo 123 is configured to output a local system clock with a second set frequency according to the voltage value, and adjust the local system clock according to the adjustment value when receiving the adjustment value.
In the embodiment of the present invention, the programmable clock module 12 is implemented by a local secondary processor 121, a digital-to-analog converter 122 (DAC) and a voltage controlled crystal oscillator 123 (VCXO). The local sub-processor 121 outputs a default setting value to the digital-to-analog converter 122, the digital-to-analog converter 122 performs digital-to-analog conversion on the setting value, and then outputs a voltage value to the vcq 123, and the vcq 123 outputs a clock with a second setting frequency according to the voltage value. After receiving the adjustment value output by the main processor 11, the program-controlled clock module 12 adjusts the clock through the voltage-controlled crystal oscillator 123, affects the frequency of the clock output by the voltage-controlled crystal oscillator 123, and determines the clock output by the voltage-controlled crystal oscillator 123 as a local system clock, sends the local system clock to the service board 2 of each slot position through the backplane bus, and then performs the next round of adjustment value evaluation on the relevant modules of the service board 2, thereby realizing the function that the system clock follows the reference clock of the superior communication device.
In an alternative embodiment, the adjustment value evaluation module 222 includes a filter processor, an integration processor, and a comparison processor;
the filtering processor is used for calculating the variation of the phase difference in a set time period and performing smooth filtering processing on the variation to obtain a frequency difference value in the set time period;
the integration processor is used for integrating the frequency difference value in the set time period to obtain an integration value;
the comparison processor is used for calculating the product of the integral value and a preset proportional value to obtain a candidate adjustment value, and comparing the candidate adjustment value with a set maximum value and a set minimum value; when the candidate adjustment value is larger than the set maximum value, outputting the set maximum value as an adjustment value; when the candidate adjustment value is smaller than the set minimum value, outputting the set minimum value as an adjustment value; outputting the candidate adjustment value as an adjustment value when the candidate adjustment value is between the set maximum value and the set minimum value.
Compared with the prior art, the embodiment of the invention has the beneficial effects that:
1. the master control board and the service board slot adopt the backboard bus to transmit the clock and the adjustment value, no additional clock signal line is needed to be arranged, the signal line resource is saved, the system design is simplified, meanwhile, the clock adjustment and evaluation function can be realized on the service board of any service board slot, the master control board selects the clock and the adjustment value, the dynamic expansion is realized, and the slot resource is saved.
2. Compared with the existing problem that the synchronization speed of the special phase-locked loop is very high, and if the clock is sent for switching, the clock of the lower-level communication equipment is easy to lose synchronization, the embodiment of the invention does not depend on the special phase-locked loop chip to select the clock source, but adopts the main processor of the main control board to dynamically select the clock source of the reference clock, and the clock adjustment and evaluation function can be realized on the service board at any service board slot position, thereby realizing dynamic expansion.
3. The step of clock adjustment is adjustable, the integral statistical time is adjustable, larger clock jitter can be filtered, and a system clock is more stable during clock switching.
4. The sliding window smoothing filtering algorithm and the integral algorithm are used for filtering instant jitter and long-time jitter, and a system clock is more stable in a clock synchronization process.
Referring to fig. 8, a clock synchronization method according to a second embodiment of the present invention is executed by a clock synchronization system, the clock synchronization system including: the system comprises a main control board, at least one service board slot and at least one service board, wherein the main control board is provided with at least one communication interface which is electrically connected with the service board slot in a one-to-one correspondence manner through a backboard bus; the service boards are correspondingly spliced with the service board slots one by one; the service board comprises a clock recovery module and an adjusting value calculation module; the output end of the clock recovery module is electrically connected with the first input end of the adjustment value calculation, the output end of the main control board is connected with the second input end of the adjustment value calculation, and the input end of the main control board is connected with the output end of the adjustment value calculation;
the method comprises the following steps:
s1: the clock recovery module recovers a reference clock from a received communication signal transmitted by superior communication equipment and sends the reference clock to the adjustment value calculation module;
s2: the main control board sends a local system clock to the adjusting value calculating module;
s3: the adjusting value calculating module calculates an adjusting value according to the reference clock and the local system clock and sends the adjusting value to the main control board;
s4: and the main control board selects an adjusting value from adjusting values output by the adjusting value calculating module of at least one service board, and adjusts the local system clock according to the selected adjusting value.
In an alternative embodiment, the adjustment value calculation module includes a phase detector module and an adjustment value evaluation module; a first input end of the phase discriminator module is electrically connected with a first input end of the adjustment value calculation, a second input end of the phase discriminator module is electrically connected with a second input end of the adjustment value calculation, an output end of the phase discriminator module is connected with an input end of the adjustment value evaluation module, and an output end of the adjustment value evaluation module is electrically connected with an output end of the adjustment value calculation;
the adjustment value calculating module calculates an adjustment value according to the reference clock and the local system clock, and sends the adjustment value to the main control board, and the method includes:
the phase discriminator module detects the phase difference between the reference clock and the local system clock and sends the phase difference to the adjustment value evaluation module;
and the adjustment value evaluation module calculates an adjustment value according to the phase difference and sends the adjustment value to the main control board.
In an optional embodiment, the main control board comprises a main processor, a programmable clock module; the input end of the main processor is electrically connected with the input end of the main control board, the output end of the main processor is electrically connected with the input end of the program-controlled clock module, and the output end of the program-controlled clock module is electrically connected with the output end of the main control board;
the main control board selects an adjustment value from adjustment values output by the adjustment value calculation module of at least one service board, and adjusts a local system clock according to the selected adjustment value, including:
the main processor selects an adjusting value from adjusting values output by an adjusting value calculation module of at least one service board and sends the selected adjusting value to the program control clock module;
and the program control clock module adjusts a local system clock according to the adjustment value and sends the adjusted local system clock to the phase discriminator module.
In an optional embodiment, the service board further includes: the first frequency reduction module and the second frequency reduction module; the first frequency reduction module is connected between the output end of the clock recovery module and the first input end of the phase discriminator module, and the second frequency reduction module is connected between the output end of the main control board and the second input end of the phase discriminator module;
the method further comprises the following steps:
the first frequency reduction module reduces the frequency of the received reference clock to a first set frequency;
the second frequency reduction module reduces the frequency of the received local system clock to the first set frequency.
In an alternative embodiment, the programmable clock module comprises: the system comprises a secondary processor, a digital-to-analog converter and a voltage-controlled crystal oscillator; the input end of the auxiliary processor is electrically connected with the input end of the program control clock module, the output end of the auxiliary processor is electrically connected with the input end of the digital-to-analog converter, the output end of the digital-to-analog converter is electrically connected with the input end of the voltage-controlled crystal oscillator, and the output end of the voltage-controlled crystal oscillator is electrically connected with the output end of the program control clock module;
the program-controlled clock module adjusts a local system clock according to the adjustment value, and the method comprises the following steps:
the secondary processor outputs a set value to the digital-to-analog converter;
the digital-to-analog converter converts the set value into a voltage value and sends the voltage value to the voltage-controlled crystal oscillator;
and the voltage-controlled crystal oscillator outputs a local system clock with a second set frequency according to the voltage value, and adjusts the local system clock according to the adjustment value when receiving the adjustment value.
In an alternative embodiment, the adjustment value evaluation module includes a filtering processor, an integration processor, and a comparison processor;
the adjustment value evaluation module calculates an adjustment value according to the phase difference and sends the adjustment value to the main control board, and the method comprises the following steps:
the filtering processor calculates the variation of the phase difference in a set time period and carries out smooth filtering processing on the variation to obtain a frequency difference value in the set time period;
the integration processor integrates the frequency difference value in the set time period to obtain an integration value;
the comparison processor calculates the product of the integral value and a preset proportional value to obtain a candidate adjustment value, and compares the candidate adjustment value with a set maximum value and a set minimum value; when the candidate adjustment value is larger than the set maximum value, outputting the set maximum value as an adjustment value; when the candidate adjustment value is smaller than the set minimum value, outputting the set minimum value as an adjustment value; when the candidate adjustment value is between the set maximum value and the set minimum value, outputting the candidate adjustment value as an adjustment value.
It should be noted that the principle of the clock synchronization method provided by the embodiment of the present invention is the same as that of the always synchronous system of the first embodiment, and a detailed description thereof is omitted.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: the master control board and the service board slot adopt the backplane bus to transmit the clock and the adjustment value, no additional clock signal line is needed to be arranged, the signal line resource is saved, meanwhile, the clock adjustment and evaluation function can be realized on the service board of any service board slot, the master control board is used for selection, the dynamic expansion is realized, and the slot resource is saved.
It should be noted that the above-described device embodiments are merely illustrative, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the embodiment of the apparatus provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A clock synchronization system, comprising: the system comprises a main control board, at least one service board slot and at least one service board, wherein the main control board is provided with at least one communication interface which is electrically connected with the service board slot in a one-to-one correspondence manner through a backboard bus; the service boards are correspondingly spliced with the service board slots one by one; the service board comprises a clock recovery module and an adjusting value calculation module; the output end of the clock recovery module is electrically connected with the first input end of the adjustment value calculation module, the output end of the main control board is connected with the second input end of the adjustment value calculation module, and the input end of the main control board is connected with the output end of the adjustment value calculation module; wherein the content of the first and second substances,
the clock recovery module is used for recovering a reference clock from a received communication signal transmitted by superior communication equipment and sending the reference clock to the adjusting value calculation module;
the main control board is used for sending a local system clock to the adjusting value calculating module;
the adjusting value calculating module is used for calculating an adjusting value according to the reference clock and the local system clock and sending the adjusting value to the main control board;
the main control board is used for selecting an adjusting value from adjusting values output by the adjusting value calculating module of at least one service board and adjusting the local system clock according to the selected adjusting value.
2. The clock synchronization system of claim 1, wherein the adjustment value calculation module comprises a phase detector module and an adjustment value evaluation module; the first input end of the phase discriminator module is electrically connected with the first input end of the adjusting value calculating module, the second input end of the phase discriminator module is electrically connected with the second input end of the adjusting value calculating module, the output end of the phase discriminator module is connected with the input end of the adjusting value evaluating module, and the output end of the adjusting value evaluating module is electrically connected with the output end of the adjusting value calculating module; wherein the content of the first and second substances,
the phase discriminator module is used for detecting the phase difference between the reference clock and the local system clock and sending the phase difference to the adjustment value evaluation module;
and the adjustment value evaluation module is used for calculating an adjustment value according to the phase difference and sending the adjustment value to the main control board.
3. The clock synchronization system of claim 2, wherein the service board further comprises: the first frequency reduction module and the second frequency reduction module; the first frequency reduction module is connected between the output end of the clock recovery module and the first input end of the phase discriminator module, and the second frequency reduction module is connected between the output end of the main control board and the second input end of the phase discriminator module; wherein the content of the first and second substances,
the first frequency reduction module is used for reducing the frequency of the received reference clock to a first set frequency;
the second frequency reduction module is used for reducing the frequency of the received local system clock to the first set frequency.
4. The clock synchronization system of claim 2, wherein the master board comprises a master processor, a programmable clock module; the input end of the main processor is electrically connected with the input end of the main control board, the output end of the main processor is electrically connected with the input end of the program-controlled clock module, and the output end of the program-controlled clock module is electrically connected with the output end of the main control board; wherein, the first and the second end of the pipe are connected with each other,
the main processor is used for selecting an adjusting value from adjusting values output by the adjusting value calculating module of at least one service board and sending the selected adjusting value to the program control clock module;
and the program control clock module is used for adjusting a local system clock according to the adjustment value and sending the adjusted local system clock to the phase discriminator module.
5. The clock synchronization system of claim 4, wherein the programmable clock module comprises: the system comprises a secondary processor, a digital-to-analog converter and a voltage-controlled crystal oscillator; the input end of the auxiliary processor is electrically connected with the input end of the program control clock module, the output end of the auxiliary processor is electrically connected with the input end of the digital-to-analog converter, the output end of the digital-to-analog converter is electrically connected with the input end of the voltage-controlled crystal oscillator, and the output end of the voltage-controlled crystal oscillator is electrically connected with the output end of the program control clock module;
the secondary processor is used for outputting a set value to the digital-to-analog converter;
the digital-to-analog converter is used for converting the set value into a voltage value and sending the voltage value to the voltage-controlled crystal oscillator;
the voltage-controlled crystal oscillator is used for outputting a local system clock with a second set frequency according to the voltage value, and adjusting the local system clock according to the adjustment value when receiving the adjustment value.
6. The clock synchronization system of claim 2, wherein the adjustment value evaluation module comprises a filtering processor, an integration processor, and a comparison processor;
the filtering processor is used for calculating the variation of the phase difference of a set time period and performing smooth filtering processing on the variation to obtain a frequency difference value in the set time period;
the integration processor is used for integrating the frequency difference value in the set time period to obtain an integration value;
the comparison processor is used for calculating the product of the integral value and a preset proportional value to obtain a candidate adjustment value, and comparing the candidate adjustment value with a set maximum value and a set minimum value; when the candidate adjustment value is larger than the set maximum value, outputting the set maximum value as an adjustment value; when the candidate adjustment value is smaller than the set minimum value, outputting the set minimum value as an adjustment value; outputting the candidate adjustment value as an adjustment value when the candidate adjustment value is between the set maximum value and the set minimum value.
7. A clock synchronization method performed by a clock synchronization system, the clock synchronization system comprising: the system comprises a main control board, at least one service board slot and at least one service board, wherein the main control board is provided with at least one communication interface which is electrically connected with the service board slot in a one-to-one correspondence manner through a backboard bus; the service boards are correspondingly spliced with the service board slots one by one; the service board comprises a clock recovery module and an adjusting value calculation module; the output end of the clock recovery module is electrically connected with the first input end of the adjusting value calculation module, the output end of the main control board is connected with the second input end of the adjusting value calculation module, and the input end of the main control board is connected with the output end of the adjusting value calculation module;
the method comprises the following steps:
the clock recovery module recovers a reference clock from a received communication signal transmitted by superior communication equipment and sends the reference clock to the adjustment value calculation module;
the main control board sends a local system clock to the adjustment value calculation module;
the adjustment value calculating module calculates an adjustment value according to the reference clock and the local system clock and sends the adjustment value to the main control board;
the main control board selects an adjustment value from adjustment values output by the adjustment value calculation module of at least one service board, and adjusts the local system clock according to the selected adjustment value.
8. The clock synchronization method of claim 7, wherein the adjustment value calculation module comprises a phase detector module and an adjustment value evaluation module; the first input end of the phase discriminator module is electrically connected with the first input end of the adjusting value calculation module, the second input end of the phase discriminator module is electrically connected with the second input end of the adjusting value calculation module, the output end of the phase discriminator module is connected with the input end of the adjusting value evaluation module, and the output end of the adjusting value evaluation module is electrically connected with the output end of the adjusting value calculation module;
the adjusting value calculating module calculates an adjusting value according to the reference clock and the local system clock, and sends the adjusting value to the main control board, including:
the phase discriminator module detects the phase difference between the reference clock and the local system clock and sends the phase difference to the adjustment value evaluation module;
and the adjustment value evaluation module calculates an adjustment value according to the phase difference and sends the adjustment value to the main control board.
9. The clock synchronization method of claim 8, wherein the master control board comprises a master processor, a programmable clock module; the input end of the main processor is electrically connected with the input end of the main control board, the output end of the main processor is electrically connected with the input end of the program-controlled clock module, and the output end of the program-controlled clock module is electrically connected with the output end of the main control board;
the main control board selects an adjustment value from adjustment values output by the adjustment value calculation module of at least one service board, and adjusts a local system clock according to the selected adjustment value, including:
the main processor selects an adjustment value from adjustment values output by the adjustment value calculation module of at least one service board and sends the selected adjustment value to the program control clock module;
and the program control clock module adjusts a local system clock according to the adjustment value and sends the adjusted local system clock to the phase discriminator module.
10. The clock synchronization method of claim 8, wherein the adjustment value evaluation module comprises a filtering processor, an integrating processor, and a comparing processor;
the adjustment value evaluation module calculates an adjustment value according to the phase difference and sends the adjustment value to the main control board, and the method comprises the following steps:
the filtering processor calculates the variation of the phase difference of a set time period and carries out smooth filtering processing on the variation to obtain a frequency difference value in the set time period;
the integration processor integrates the frequency difference value in the set time period to obtain an integration value;
the comparison processor calculates the product of the integral value and a preset proportional value to obtain a candidate adjustment value, and compares the candidate adjustment value with a set maximum value and a set minimum value; when the candidate adjustment value is larger than the set maximum value, outputting the set maximum value as an adjustment value; when the candidate adjustment value is smaller than the set minimum value, outputting the set minimum value as an adjustment value; outputting the candidate adjustment value as an adjustment value when the candidate adjustment value is between the set maximum value and the set minimum value.
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