CN112910564A - High-speed receiving circuit and high-speed transmitting-receiving circuit - Google Patents
High-speed receiving circuit and high-speed transmitting-receiving circuit Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/501—Structural aspects
- H04B10/503—Laser transmitters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/564—Power control
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Abstract
The invention discloses a high-speed receiving circuit and a high-speed transceiving circuit, and relates to the technical field of semiconductor integrated circuits, wherein the high-speed receiving circuit comprises a signal conversion unit, a clock recovery unit, a clock processing and output unit and a PAM4 and NRZ integrated data conversion unit, wherein the signal conversion unit is used for converting input serial signals into three groups of different digital signals; the clock recovery unit comprises a phase locked loop outputting a clock signal, relclk 1; the clock processing and output unit is used for obtaining a PAM4 clock signal and an NRZ clock signal according to the code pattern selection control signal; the PAM4 and NRZ integrated data conversion unit is used for converting an input PAM4 clock signal or an NRZ clock signal into two paths of parallel output signals. The high-speed receiving circuit provided by the invention is suitable for ultra-high-speed signals, and realizes the same maximum modulation rate for PAM4 signals and NRZ signals.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a high-speed receiving circuit and a high-speed transmitting-receiving circuit.
Background
With the popularization and application of broadband services such as electronic commerce, 4K/8K videos, internet of things, cloud computing and the like and the gradual rise of ultra-wideband services such as unmanned intelligent driving, Virtual Reality (VR), Artificial Intelligence (AI), smart cities and the like, companies such as operators, internet and the like are greatly promoted to actively upgrade the existing network equipment so as to meet the requirements of emerging services on ultra-wideband, ultra-large capacity, low delay and the like.
Meanwhile, the upgrading and deployment of these existing network devices require the whole industrial chain to rapidly develop high-speed optical devices, high-speed electrical chips, radio frequency/microwave electrical chips, ultra-high-speed optical modules, ultra-large-capacity network devices, and the like.
However, in the development process of the ultra-high speed optical module, due to the limitation of bandwidth capabilities of PCB plate materials, optical component materials, connectors between the optical component and the PCB, and the like, the transmission loss of the ultra-high speed signal is large, the transmission distance is very limited, and the ultra-high speed optical module faces the problem of the limit of the transmission rate.
In order to solve the problem of the limit of the transmission rate of the ultra-high-speed optical module, two ways are generally available, the first is to explore a miniaturized packaging scheme for the optical module and the optical module, and shorten the transmission distance of the ultra-high-speed signal to a range required by the specification, but the realization difficulty of the ultra-high-frequency/microwave scene is very high; the second method is to search for a link path of photoelectric conversion to convert a super high speed signal into multiple parallel high speed/medium low speed signals to realize a longer transmission distance.
In the prior art, a mode of converting an ultra-high-speed signal into a multi-path parallel high-speed/medium-low-speed signal is widely adopted in an ultra-high-speed optical module, for example, a high-order modulation technology is adopted to replace a commonly used NRZ modulation technology.
Generally, an optical receiver of an ultra-high speed optical module can only support NRZ signal transmission, but cannot support PAM4 signal transmission; or although both NRZ signal transmission and PAM4 signal transmission can be supported, the maximum modulation rate of the supported NRZ signal is half of that of PAM4 signal, for example, in an optical receiver supporting 25GBaud/s PAM4, the signal bit rate corresponding to 25GBaud/s is 50Gbps, and the maximum modulation rate of the NRZ signal that the optical receiver can support is 25Gbps and cannot reach 50Gbps, so that the application range is very limited and the requirement of a 50G PON system cannot be met.
Disclosure of Invention
In view of the defects in the prior art, the present invention is directed to a high-speed receiving circuit, which is applicable to ultra-high-speed signals and achieves the same maximum modulation rate for PAM4 signals and NRZ signals.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows:
a high speed receive circuit comprising:
a signal conversion unit for converting an input serial signal into three different sets of digital signals, which are denoted as vouthhigh, voutMid, and voutLow, respectively;
a clock recovery unit comprising a phase locked loop for outputting a clock signal reCLK1 from one of the sets of digital signals;
the clock processing and output unit is used for obtaining a PAM4 clock signal and an NRZ clock signal according to the code type selection control signal, performing buffer shaping processing on the clock signal recCLK 1 and outputting the clock signal recCLK;
and the PAM4 and NRZ integrated data conversion unit is used for selecting a control signal according to a code pattern, carrying out signal processing on three groups of different digital signals by utilizing a PAM4 clock signal, an NRZ clock signal and a clock signal recLK, and converting an input PAM4 clock signal or NRZ clock signal into two paths of parallel output signals.
On the basis of the technical scheme, the signal conversion unit specifically comprises a signal top detection circuit, a signal bottom detection circuit and three comparators, wherein the signal top detection circuit is used for processing an input serial signal to obtain a top voltage, and the signal bottom detection circuit is used for processing the input serial signal to obtain a bottom voltage;
a plurality of resistors are connected in series between the output ends of the signal top detection circuit and the signal bottom detection circuit, three different potentials are selected at the connection positions of the resistors to be three threshold voltages, one input end of each of the three comparators is correspondingly connected with one threshold voltage, and the other input end of each of the three comparators is connected with an input serial signal;
the output ends of the three comparators output three groups of different digital signals.
On the basis of the technical scheme, the clock processing and output unit comprises a transmission gate 1, a transmission gate 2, a phase inverter NOT21 and a trigger 21, wherein the input end of the phase inverter NOT21, the normal phase control input end of the transmission gate 1 and the reverse phase control input end of the transmission gate 2 are all connected with a code type selection control signal, the reverse phase control input end of the transmission gate 1 and the normal phase control input end of the transmission gate 2 are all connected with the output end of the phase inverter NOT21, the input end of the transmission gate 1 and the input end IN of the transmission gate 2 are all connected with the output end of a phase locker, the output end of the transmission gate 1 outputs a PAM4 clock signal, and the output end of the transmission gate 2 outputs an NRZ clock signal after passing through the trigger 21.
On the basis of the technical scheme, the transmission gate 1 and the second transmission gate 2 have the same structure.
On the basis of the technical scheme, the transmission gate 1 and the transmission gate 2 are formed by connecting an NMOS tube and a PMOS tube in parallel.
On the basis of the technical scheme, the three threshold voltages are in an arithmetic progression.
On the basis of the technical scheme, the PAM4 and NRZ integrated data conversion unit comprises a PAM4 data conversion unit and an NRZ data conversion unit;
the PAM4 data conversion unit comprises an inverter NOT32, an inverter NOT33, an OR gate 31, an AND gate 31, a flip-flop 34, an inverter NOT34, a transmission gate 3, an OR gate 32, an AND gate 32, a flip-flop 35, an inverter NOT35 and a transmission gate 4, wherein the input end of the inverter NOT32 is connected with voutMid, the output end of the inverter NOT32 is sequentially connected with the inverter NOT33, the OR gate 31, the AND gate 31, the flip-flop 34 and the transmission gate 3 and then outputs a parallel signal, or the other input end of the gate 31 is connected with voutHigh, the other input end of the AND gate 31 is connected with voutLow, the other input end of the flip-flop 34 is connected with a PAM4 clock signal, the other two input ends of the transmission gate 3 are respectively connected with the input end and the output end of the inverter NOT34, and the input end of the inverter NOT34 is;
meanwhile, the output end of the inverter NOT32 is sequentially connected with the or gate 32, the and gate 32, the flip-flop 35 and the transmission gate 4, and then outputs another parallel signal, the other input end of the or gate 32 is connected with vouthhigh, the other input end of the and gate 32 is connected with voutLow, the other input end of the flip-flop 35 is connected with a PAM4 clock signal, the other two input ends of the transmission gate 4 are respectively connected with the input end and the output end of the inverter NOT35, and the input end of the inverter NOT35 is connected with a code type selection control signal.
The NRZ data conversion unit comprises an inverter NOT31, a transmission gate 5, a flip-flop 31, a flip-flop 32, a flip-flop 33, a flip-flop 36, an inverter NOT36, an inverter NOT37, a transmission gate 6 and a transmission gate 7, wherein one input end of the transmission gate 5 is connected with voutMid, the other two input ends of the transmission gate 5 are respectively connected with an input end and an output end of the inverter NOT31, two input ends of the flip-flop 31 are respectively connected with an output end of a fifth transmission gate and a clock signal recCLK 1, two input ends of the flip-flop 32 are respectively connected with a clock signal recCLK 2 and an output end of the flip-flop 31, two input ends of the flip-flop 33 are respectively connected with an output end of the flip-flop 31 and an NRZ clock signal, two input ends of the flip-flop 36 are respectively connected with an output end of the flip-flop 32 and an NRZ clock signal, input ends of the inverter NOT36 and the inverter NOT 64 are respectively connected with a, the three input ends of the transmission gate 6 are respectively connected with the output end of the trigger 36, the input end of the inverter NOT36 and the output end of the inverter NOT36, the three input ends of the transmission gate 7 are respectively connected with the output end of the trigger 33, the input end of the inverter NOT37 and the output end of the inverter NOT37, the transmission gate 6 outputs one path of parallel signals, and the transmission gate 7 outputs the other path of parallel signals.
On the basis of the technical scheme, the transmission gate 3, the transmission gate 4, the transmission gate 5, the transmission gate 6 and the transmission gate 7 have the same structure.
The present invention also provides a high-speed transceiver circuit, comprising:
the high-speed receiving circuit is located on a receiving side;
a transmission module at a transmission side, comprising:
the encoder is used for converting two paths of parallel input signals into one path of serial data to be output according to a clock signal relclk;
the laser driver is connected with one input end of the encoder and used for converting the output signal of the encoder into a high-speed differential data signal and outputting a bias current;
a laser connected to the laser driver;
and the input end of the photoelectric detector is connected with the laser, the output end of the photoelectric detector is connected with the other input end of the laser driver, the photoelectric detector is used for monitoring the optical power of the laser and sending an optical power signal to the laser driver, and the laser driver adjusts the bias current in real time according to the optical power signal so as to maintain the optical power of the laser within a preset power range.
On the basis of the technical scheme, the optical fiber receiving device further comprises a linear amplifier, wherein the input end of the linear amplifier is connected with the output end of the external optical receiving component, the output end of the linear amplifier is connected with the input end of the signal conversion unit, and the linear amplifier is used for linearly amplifying the output signal of the external optical receiving component to obtain a serial signal.
Compared with the prior art, the invention has the advantages that: the high-speed receiving circuit is suitable for ultra-high-speed signals, realizes the same maximum modulation rate for PAM4 signals and NRZ signals, can meet the requirements of high-speed interface circuits in a 50G PON system, and lays a foundation for the 50G PON.
Drawings
FIG. 1 is a schematic diagram of a high-speed receiving circuit according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a signal conversion unit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a clock processing and output unit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a PAM4 and NRZ unified data conversion unit according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating simulation results of a high-speed receiving circuit when a data signal of PAM4 code type with 25GBaud/s data is input according to an embodiment of the present invention;
FIG. 6 is a diagram showing simulation results of a high-speed receiving circuit when an NRZ code type data signal having data at 50Gbps is input according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a high-speed transceiver circuit according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Referring to fig. 1, an embodiment of the present invention provides a high-speed receiving circuit, which includes a signal conversion unit, a clock recovery unit, a clock processing and output unit, and a PAM4 and NRZ unified data conversion unit.
The signal conversion unit is used for converting the input serial signals into three groups of different digital signals; the specific process is as follows: three threshold voltages are obtained through a signal detection circuit and a resistance voltage division circuit, and are converted into three groups of different digital signals through a comparator, wherein the three groups of different digital signals are marked as voutHigh, voutMid and voutLow respectively;
the clock recovery unit comprises a phase-locked loop, wherein the phase-locked loop is used for outputting a clock signal reCLK1 from one group of digital signals, and in the embodiment of the invention, voutMid is selected, namely the input end of the phase-locked loop is connected with the output end voutMid of a comparator, and the clock signal reCLK1 is recovered and output from the signal voutMid;
the clock processing and output unit is used for performing PAM (pulse amplitude modulation) code type processing or NRZ (non-zero cross correlation) code type processing on the clock signal recCLK 1 according to the code type selection control signal Vcode, correspondingly obtaining a PAM4 clock signal recCLPAM corresponding to PAM4 code type input data and an NRZ clock signal recCLKD 2 corresponding to NRZ code type input data, and simultaneously performing buffer shaping processing on the clock signal recCLK 1 and outputting the clock signal recCLK;
the input end of the PAM4 and NRZ integrated data conversion unit is connected with the output ends of the signal conversion unit and the clock processing and output unit, and the data conversion unit is used for selecting a control signal Vcode according to a code pattern, performing signal processing on three digital level signals voutHigh, voutMid and voutLow by using clock signals reCLPAM, reCLKD2 and reCLK, and converting an input PAM4 signal or an NRZ signal into two parallel output signals outDA1 and outDB 2.
Referring to fig. 2, specifically, in the embodiment of the present invention, the signal conversion unit specifically includes a signal top detection circuit, a signal bottom detection circuit and three comparators, where the signal top detection circuit is configured to process an input serial signal Din to obtain a top voltage, and the signal bottom detection circuit is configured to process the input serial signal Din to obtain a bottom voltage; and a plurality of resistors are connected in series between the output ends of the signal top detection circuit and the signal bottom detection circuit, three different potentials are selected at the joints of the plurality of resistors to be three threshold voltages, one input end of each of the three comparators is correspondingly connected with one threshold voltage, and the other input end of each of the three comparators is connected with the serial signal Din.
Preferably, in the embodiment of the present invention, three threshold voltages are in an arithmetic progression and are respectively denoted as Vth _ H, Vth _ M, Vth _ L, six resistors are sequentially connected in series between output terminals of the signal top detection circuit and the signal bottom detection circuit, the six resistors are respectively a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, and a resistor R6, and resistances of the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, and the resistor R6 are all the same, a connection point between the resistor R1 and the resistor R2 is taken as the threshold voltage Vth _ H, a connection point between the resistor R3 and the resistor R4 is taken as the threshold voltage Vth _ M, a connection point between the resistor R5 and the resistor R6 is taken as the threshold voltage Vth _ L, and three comparators correspondingly output three different digital level signals, which are respectively denoted as vouthuthid, voutMid, and vonlow.
The working process of the signal conversion unit is as follows: the signal top detection circuit monitors and outputs the averaged stable top voltage in real time, the signal bottom detection circuit monitors and outputs the averaged stable bottom voltage in real time, the stable top voltage and the stable bottom voltage are used as reference voltages, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5 and the resistor R6 divide the reference voltages to obtain three different threshold voltages Vth _ H, Vth _ M and Vth _ L, then the three threshold voltages respectively pass through three comparators to correspondingly output three different digital level signals, taking the comparator 1 as an example, if the input data signal Din is greater than the threshold voltage Vth _ H, the digital level signal voutHigh output by the comparator 1 is high level 1, otherwise, the digital level signal voutHigh is low level 0.
Further, referring to fig. 3, IN the embodiment of the present invention, the clock processing and output unit includes a transmission gate 1, a transmission gate 2, an inverter NOT21, an inverter NOT22, an inverter NOT23, a flip-flop 21, an inverter NOT24, and an inverter NOT25, an input terminal of the inverter NOT21, a non-inverting control input terminal VP of the transmission gate 1, and an inverting control input terminal VN of the transmission gate 2 are all connected to a code type selection control signal Vcode, an inverting control input terminal VN of the transmission gate 1 and a non-inverting control input terminal VP of the transmission gate 2 are all connected to an output terminal Vcode of the inverter NOT21, an input terminal IN of the transmission gate 1 and an input terminal IN of the transmission gate 2 are all connected to an output terminal clk1 of the phase locker, an output terminal of the transmission gate 1 sequentially passes through the inverter NOT22 and the inverter NOT23 connected IN series to output a PAM4 clock signal reCLKPAM, an output terminal of the transmission gate 2 passes through the flip-flop 21 to output an NRZ clock signal reCLKd2, the input end of the inverter NOT24 is connected with the clock signal recCLK 1, the output end of the inverter NOT24 is connected with the input end of the inverter NOT25, and the output end of the inverter NOT25 outputs the clock signal recCLK.
Preferably, the transmission gate 1 and the transmission gate 2 are identical in structure. The transmission gate 1 and the transmission gate 2 are both formed by connecting an NMOS tube and a PMOS tube in parallel.
Referring to fig. 4, more specifically, the PAM4 and NRZ unified data conversion unit includes a PAM4 data conversion unit and an NRZ data conversion unit.
The PAM4 data conversion unit comprises an inverter NOT32, an inverter NOT33, an OR gate 31, an AND gate 31, a flip-flop 34, an inverter NOT34, a transmission gate 3, an OR gate 32, an AND gate 32, a flip-flop 35, an inverter NOT35 and a transmission gate 4, wherein the input end of the inverter NOT32 is connected with voutMid, the output end of the inverter NOT32 is sequentially connected with the inverter NOT33, the OR gate 31, the AND gate 31, the flip-flop 34 and the transmission gate 3 to output a parallel signal OutDB2, the other input end of the OR gate 31 is connected with voutHigh, the other input end of the AND gate 31 is connected with voutLow, the other input end of the flip-flop 34 is connected with a PAM4 clock signal ReCLKL, the other two input ends of the transmission gate 3 are respectively connected with the input end and the output end of the inverter NOT34, and the input end of the inverter NOT34 is connected with;
meanwhile, the output end of the inverter NOT32 is sequentially connected with the or gate 32, the and gate 32, the flip-flop 35 and the transmission gate 4, and then outputs another parallel signal OutDA1, the other input end of the or gate 32 is connected with vouthhigh, the other input end of the and gate 32 is connected with voutLow, the other input end of the flip-flop 35 is connected with a PAM4 clock signal reCLKPAM, the other two input ends of the transmission gate 4 are respectively connected with the input end and the output end of the inverter NOT35, and the input end of the inverter NOT35 is connected with a code type selection control signal Vcode.
The NRZ data conversion unit comprises an inverter NOT31, a transmission gate 5, a flip-flop 31, a flip-flop 32, a flip-flop 33, a flip-flop 36, an inverter NOT36, an inverter NOT37, a transmission gate 6 and a transmission gate 7, wherein one input end of the transmission gate 5 is connected with voutMid, the other two input ends of the transmission gate 5 are respectively connected with an input end and an output end of the inverter NOT31, two input ends of the flip-flop 31 are respectively connected with an output end of a fifth transmission gate and a clock signal recCLK 1, two input ends of the flip-flop 32 are respectively connected with a clock signal recCLK 1 and an output end of the flip-flop 31, two input ends of the flip-flop 33 are respectively connected with an output end of the flip-flop 31 and an NRZ clock signal recCLKD 2, two input ends of the flip-flop 36 are respectively connected with an output end of the flip-flop 32 and an NRZ clock signal recD 2, and input ends of the inverter NOT36 and the inverter NOT37 are respectively connected with a, three input ends of the transmission gate 6 are respectively connected with an output end of the trigger 36, an input end of the inverter NOT36 and an output end of the inverter NOT36, three input ends of the transmission gate 7 are respectively connected with an output end of the trigger 33, an input end of the inverter NOT37 and an output end of the inverter NOT37, the transmission gate 6 outputs one path of parallel signal OutDB2, and the transmission gate 7 outputs the other path of parallel signal OutDA 1.
Preferably, in the embodiment of the present invention, the transmission gate 3, the transmission gate 4, the transmission gate 5, the transmission gate 6, and the transmission gate 7 have the same structure. The transmission gate 3, the transmission gate 4, the transmission gate 5, the transmission gate 6 and the transmission gate 7 are all formed by connecting an NMOS tube and a PMOS tube in parallel.
More preferably, flip-flop 21, flip-flop 31, flip-flop 32, flip-flop 33, flip-flop 34, flip-flop 35, and flip-flop 36 are all D flip-flops.
In the embodiment of the present invention, an example of the operation process of the PAM4 and NRZ integrated data conversion unit is as follows: when the Vcode is low level 0, a link aiming at a PAM4 data conversion unit of a PAM4 code type is selected, when the Vcode is high level 1, a link aiming at an NRZ data conversion unit of an NRZ code type is selected, output signals of the PAM4 and the NRZ integrated data conversion unit are OutDA1 and OutDB2 respectively, wherein the OutDA1 is a low-bit signal, and the OutDB2 is a low-bit signal.
Furthermore, the high-speed receiving circuit in the embodiment of the present invention is subjected to analog simulation, and the obtained output signal is different for different input conditions, which is as follows:
referring to fig. 5, when a PAM4 code type data signal with 25GBaud/s of Rxin data is input, time domain waveform diagrams of Rxin, vouthhigh, voutMid, voutLow, reCLKPAM, OutDB2 and OutDA1 are sequentially arranged from top to bottom.
Referring to fig. 6, when Rxin is an NRZ code type data signal of 50Gbps, time domain waveform diagrams of Rxin, relclk, nrzOutDA, nrzOutDB, reCLKd2, OutDB2, OutDA1 are arranged from top to bottom, where nrzOutDA represents an output signal of the flip-flop 31 and nrzOutDB represents an output signal of the flip-flop 32.
Therefore, compared with the prior art that the maximum modulation rate of the supported NRZ signal is half of the maximum modulation rate of the PAM4 signal and cannot reach the maximum modulation rate same as that of the PAM4 signal, the high-speed receiving circuit provided by the embodiment of the invention is suitable for ultra-high-speed signals, not only supports PAM4 coding, but also supports frequency multiplication coding of the NRZ signal, realizes the same maximum modulation rate for the PAM4 signal and the NRZ signal, can meet the requirements of high-speed interface circuits in a 50G and higher rate system, and lays a foundation for the realization of a next-generation PON system (50G PON).
Referring to fig. 7, an embodiment of the present invention further provides a high-speed transceiver circuit, which includes the above-mentioned high-speed receiver circuit and a transmitter module located at a transmitting side, where the high-speed receiver circuit is located at a receiving side.
The sending module comprises an encoder, a laser driver, a laser and a photoelectric detector. The encoder is used for converting the two parallel input signals into a serial data output according to a clock signal relCLK; one input end of the laser driver is connected with the output end of the encoder and is used for converting the output signal of the encoder into a high-speed differential data signal and outputting a bias current; the laser is connected with the laser driver; the input end of the photoelectric detector is connected with the laser, the output end of the photoelectric detector is connected with the other input end of the laser driver, the photoelectric detector is used for monitoring the optical power of the laser and sending the optical power signal to the laser driver, and the laser driver adjusts the bias current in real time according to the optical power signal so as to maintain the optical power of the laser within a preset power range.
In the embodiment of the invention, an input signal of the high-speed receiving circuit is Din, output signals are OutDA1 and OutDB2, input signals of the encoder are Data1 and Data2, an output signal is Dout, high-speed differential Data signals output by the laser driver are a signal LDP output from a equidirectional output end and a signal LDN output from a reverse output end respectively, the signal LDP is connected with an anode of the laser, the signal LDN is connected with a cathode of the laser, a bias current Ibias is connected to the anode or the cathode of the laser according to actual needs, the photodetector detects the optical power of the laser, and sends an optical power signal Imon to the laser driver.
In the embodiment of the invention, a laser driver converts serial data Dout input by an encoder into a high-speed differential data signal, the laser driver provides bias current Ibias to a laser to enable the laser to be in a working state, a signal LDN and a signal LDP are electrical modulation signals, the high-speed differential data signal drives the laser to convert the electrical modulation signals into optical signals to be output, a photoelectric detector detects the optical power of the laser in real time and sends an optical power signal Imon to the laser driver, the laser and the photoelectric detector form a closed-loop system, and the laser driver dynamically adjusts the bias current Ibias according to the received optical power signal Imon to enable the optical power output by the laser to be maintained in a preset power range.
Furthermore, the high-speed transceiver circuit according to the embodiment of the present invention further includes a linear amplifier, an input end of the linear amplifier is connected to an output end of the external light receiving component, an output end of the linear amplifier is connected to an input end of the signal conversion unit, and the linear amplifier is configured to perform linear amplification on an output signal of the external light receiving component to obtain the serial signal Din. The present invention is not limited to the above-described embodiments, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements are also considered to be within the scope of the present invention. Those not described in detail in this specification are within the skill of the art.
Claims (10)
1. A high speed receive circuit, comprising:
a signal conversion unit for converting an input serial signal into three different sets of digital signals, which are denoted as vouthhigh, voutMid, and voutLow, respectively;
a clock recovery unit comprising a phase locked loop for outputting a clock signal reCLK1 from one of the sets of digital signals;
the clock processing and output unit is used for obtaining a PAM4 clock signal and an NRZ clock signal according to the code type selection control signal, performing buffer shaping processing on the clock signal recCLK 1 and outputting the clock signal recCLK;
and the PAM4 and NRZ integrated data conversion unit is used for selecting a control signal according to a code pattern, carrying out signal processing on three groups of different digital signals by utilizing a PAM4 clock signal, an NRZ clock signal and a clock signal recLK, and converting an input PAM4 clock signal or NRZ clock signal into two paths of parallel output signals.
2. The high-speed receiving circuit according to claim 1, wherein the signal conversion unit specifically includes a signal top detection circuit, a signal bottom detection circuit and three comparators, the signal top detection circuit is configured to process an input serial signal to obtain a top voltage, and the signal bottom detection circuit is configured to process the input serial signal to obtain a bottom voltage;
a plurality of resistors are connected in series between the output ends of the signal top detection circuit and the signal bottom detection circuit, three different potentials are selected at the connection positions of the resistors to be three threshold voltages, one input end of each of the three comparators is correspondingly connected with one threshold voltage, and the other input end of each of the three comparators is connected with an input serial signal;
the output ends of the three comparators output three groups of different digital signals.
3. The high-speed receiving circuit as claimed IN claim 1, wherein the clock processing and output unit comprises a transmission gate 1, a transmission gate 2, an inverter NOT21 and a flip-flop 21, wherein an input terminal of the inverter NOT21, a non-inverting control input terminal of the transmission gate 1 and an inverting control input terminal of the transmission gate 2 are all connected to the code pattern selection control signal, an inverting control input terminal of the transmission gate 1 and a non-inverting control input terminal of the transmission gate 2 are all connected to an output terminal of the inverter NOT21, an input terminal of the transmission gate 1 and an input terminal IN of the transmission gate 2 are all connected to an output terminal of the phase locker, an output terminal of the transmission gate 1 outputs a PAM4 clock signal, and an output terminal of the transmission gate 2 outputs an NRZ clock signal after passing through the flip-flop 21.
4. A high speed receive circuit as claimed in claim 3, wherein: the transmission gate 1 and the second transmission gate 2 have the same structure.
5. The high speed receive circuit of claim 4, wherein: the transmission gate 1 and the transmission gate 2 are both formed by connecting an NMOS tube and a PMOS tube in parallel.
6. A high speed receive circuit as recited in claim 2, wherein: the three threshold voltages are in an arithmetic progression.
7. The high-speed receiving circuit of claim 1, wherein the PAM4 and NRZ integrated data conversion unit includes a PAM4 data conversion unit and an NRZ data conversion unit;
the PAM4 data conversion unit comprises an inverter NOT32, an inverter NOT33, an OR gate 31, an AND gate 31, a flip-flop 34, an inverter NOT34, a transmission gate 3, an OR gate 32, an AND gate 32, a flip-flop 35, an inverter NOT35 and a transmission gate 4, wherein the input end of the inverter NOT32 is connected with voutMid, the output end of the inverter NOT32 is sequentially connected with the inverter NOT33, the OR gate 31, the AND gate 31, the flip-flop 34 and the transmission gate 3 and then outputs a parallel signal, or the other input end of the gate 31 is connected with voutHigh, the other input end of the AND gate 31 is connected with voutLow, the other input end of the flip-flop 34 is connected with a PAM4 clock signal, the other two input ends of the transmission gate 3 are respectively connected with the input end and the output end of the inverter NOT34, and the input end of the inverter NOT34 is;
meanwhile, the output end of the inverter NOT32 is sequentially connected with the or gate 32, the and gate 32, the flip-flop 35 and the transmission gate 4, and then outputs another parallel signal, the other input end of the or gate 32 is connected with vouthhigh, the other input end of the and gate 32 is connected with voutLow, the other input end of the flip-flop 35 is connected with a PAM4 clock signal, the other two input ends of the transmission gate 4 are respectively connected with the input end and the output end of the inverter NOT35, and the input end of the inverter NOT35 is connected with a code type selection control signal.
The NRZ data conversion unit comprises an inverter NOT31, a transmission gate 5, a flip-flop 31, a flip-flop 32, a flip-flop 33, a flip-flop 36, an inverter NOT36, an inverter NOT37, a transmission gate 6 and a transmission gate 7, wherein one input end of the transmission gate 5 is connected with voutMid, the other two input ends of the transmission gate 5 are respectively connected with an input end and an output end of the inverter NOT31, two input ends of the flip-flop 31 are respectively connected with an output end of a fifth transmission gate and a clock signal recCLK 1, two input ends of the flip-flop 32 are respectively connected with a clock signal recCLK 2 and an output end of the flip-flop 31, two input ends of the flip-flop 33 are respectively connected with an output end of the flip-flop 31 and an NRZ clock signal, two input ends of the flip-flop 36 are respectively connected with an output end of the flip-flop 32 and an NRZ clock signal, input ends of the inverter NOT36 and the inverter NOT 64 are respectively connected with a, the three input ends of the transmission gate 6 are respectively connected with the output end of the trigger 36, the input end of the inverter NOT36 and the output end of the inverter NOT36, the three input ends of the transmission gate 7 are respectively connected with the output end of the trigger 33, the input end of the inverter NOT37 and the output end of the inverter NOT37, the transmission gate 6 outputs one path of parallel signals, and the transmission gate 7 outputs the other path of parallel signals.
8. A high speed receive circuit as recited in claim 7, wherein: the transmission gate 3, the transmission gate 4, the transmission gate 5, the transmission gate 6 and the transmission gate 7 have the same structure.
9. A high-speed transceiver circuit, comprising:
a high speed receiving circuit as claimed in any one of claims 1 to 8, said high speed receiving circuit being located on a receiving side;
a transmission module at a transmission side, comprising:
the encoder is used for converting two paths of parallel input signals into one path of serial data to be output according to a clock signal relclk;
the laser driver is connected with one input end of the encoder and used for converting the output signal of the encoder into a high-speed differential data signal and outputting a bias current;
a laser connected to the laser driver;
and the input end of the photoelectric detector is connected with the laser, the output end of the photoelectric detector is connected with the other input end of the laser driver, the photoelectric detector is used for monitoring the optical power of the laser and sending an optical power signal to the laser driver, and the laser driver adjusts the bias current in real time according to the optical power signal so as to maintain the optical power of the laser within a preset power range.
10. The high-speed transceiver circuit according to claim 9, further comprising a linear amplifier, wherein an input terminal of the linear amplifier is connected to an output terminal of the external light receiving element, an output terminal of the linear amplifier is connected to an input terminal of the signal conversion unit, and the linear amplifier is configured to linearly amplify an output signal of the external light receiving element to obtain a serial signal.
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