CN112909019B - Array substrate, preparation method of array substrate and display device - Google Patents
Array substrate, preparation method of array substrate and display device Download PDFInfo
- Publication number
- CN112909019B CN112909019B CN202110068843.5A CN202110068843A CN112909019B CN 112909019 B CN112909019 B CN 112909019B CN 202110068843 A CN202110068843 A CN 202110068843A CN 112909019 B CN112909019 B CN 112909019B
- Authority
- CN
- China
- Prior art keywords
- conductive pattern
- insulating
- substrate
- insulating structure
- array substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 153
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 26
- 239000010409 thin film Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 11
- 238000010276 construction Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 53
- 238000010586 diagram Methods 0.000 description 16
- 239000000463 material Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 11
- 238000003860 storage Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 239000010408 film Substances 0.000 description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 229910052755 nonmetal Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 241001391944 Commicarpus scandens Species 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910001257 Nb alloy Inorganic materials 0.000 description 2
- 229910000583 Nd alloy Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UBSJOWMHLJZVDJ-UHFFFAOYSA-N aluminum neodymium Chemical compound [Al].[Nd] UBSJOWMHLJZVDJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The disclosure provides an array substrate, a preparation method of the array substrate and a display device, and belongs to the field of display. The array substrate comprises a substrate and a first insulating structure, a first conductive pattern, a second insulating structure and a second conductive pattern which are sequentially arranged on the substrate, wherein the first insulating structure is located on the substrate, the first conductive pattern is located on one side, away from the substrate, of the first insulating structure, the second insulating structure is located on one side, away from the substrate, of the first conductive pattern, the second conductive pattern is located on one side, away from the substrate, of the second insulating structure, the orthographic projection of the second conductive pattern on the substrate is overlapped with the orthographic projection of the first conductive pattern on the substrate, the first insulating structure comprises a first insulating part and a second insulating part, the first insulating part is located on one side, away from the substrate, of the second insulating part, and the lower surface of the first conductive pattern is overlapped with the orthographic projection of the upper surface of the first insulating part on the substrate.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display device.
Background
The array substrate of the conventional display panel has a plurality of thin film transistors and capacitors, for example, a gate driving circuit of the display device has a storage capacitor for maintaining a voltage of each pixel region after the transistors are turned off.
However, in the prior art, a non-metal layer between an upper polar plate and a lower polar plate of a storage capacitor is easy to break, so that the upper polar plate and the lower polar plate of the capacitor are short-circuited, and the display circuit is abnormal.
Disclosure of Invention
The disclosure aims to at least solve one of the technical problems in the prior art, and provides an array substrate, a preparation method of the array substrate and a display device.
In a first aspect, an embodiment of the present disclosure provides an array substrate, including a substrate, and a first insulating structure, a first conductive pattern, a second insulating structure, and a second conductive pattern sequentially disposed on the substrate, where the first insulating structure is located on the substrate, the first conductive pattern is located on a side of the first insulating structure facing away from the substrate, the second insulating structure is located on a side of the first conductive pattern facing away from the substrate, the second conductive pattern is located on a side of the second insulating structure facing away from the substrate, a front projection of the second conductive pattern on the substrate overlaps with a front projection of the first conductive pattern on the substrate, and the first insulating structure includes a first insulating portion and a second insulating portion, the first insulating portion is located on a side of the second insulating portion facing away from the substrate, and a lower surface of the first conductive pattern overlaps with a front projection of an upper surface of the first insulating portion on the substrate.
Optionally, the side surface of the first insulating portion and the upper surface of the second insulating portion contact to form a first dihedral angle, the second insulating structure forms a second dihedral angle at the first dihedral angle position, and the second insulating structure contacts only the first insulating structure at the second dihedral angle position.
Optionally, the first insulating portion and the second insulating portion are of unitary construction.
Optionally, the orthographic projection of the second conductive pattern on the substrate covers the orthographic projection of the first conductive pattern on the substrate.
Optionally, the thickness of the second insulating structure is greater than the thickness of the first insulating structure.
Optionally, the thickness of the first insulating structure at the position where the first insulating part and the second insulating part are projected to overlap on the substrate is larger than the thickness of the first insulating structure at the position where the first insulating part and the second insulating part are projected to be non-overlapping on the substrate.
Optionally, the first insulating portion has a thickness of 200-500 angstroms.
Optionally, the array substrate includes a display area and a non-display area, a gate driving circuit is disposed in the non-display area, the gate driving circuit includes at least one capacitor, the capacitor has a first plate and a second plate, and the first conductive pattern and the second conductive pattern are the first plate and the second plate of the capacitor, respectively.
Optionally, the gate driving circuit further includes at least one thin film transistor, the thin film transistor includes a gate electrode, a source electrode, and a drain electrode, the first conductive pattern is disposed in a same layer as the gate electrode of the thin film transistor, and the second conductive pattern is disposed in a same layer as the source electrode and the drain electrode of the thin film transistor.
Optionally, the array substrate includes a display area and a non-display area, a pixel driving circuit is disposed in the display area, the pixel driving circuit includes at least one thin film transistor, and the thin film transistor includes a first gate and a second gate, and the first conductive pattern and the second conductive pattern are the first gate and the second gate of the thin film transistor, respectively.
Optionally, a buffer layer is disposed between the first insulating structure and the substrate.
In a second aspect, an embodiment of the present disclosure provides a method for manufacturing an array substrate, including:
sequentially forming a first insulating structure and a first metal layer on a substrate, and forming a first conductive pattern through a patterning process;
forming a pattern of a first insulating part through a one-time patterning process, wherein the lower surface of the first conductive pattern overlaps with the orthographic projection of the upper surface of the first insulating part on the substrate;
forming a second insulating structure on the first conductive pattern;
and forming a second metal layer on the second insulating structure, and forming a second conductive pattern through a patterning process, wherein the orthographic projection of the second conductive pattern on a substrate overlaps with the orthographic projection of the first conductive pattern on the substrate.
In a third aspect, an embodiment of the present disclosure provides a display device including the above array substrate.
Drawings
FIG. 1 is a schematic diagram of an array substrate in the prior art;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram of another array substrate according to an embodiment of the disclosure;
FIG. 4 is a circuit diagram of an exemplary shift register;
FIG. 5 is a schematic diagram of an exemplary pixel circuit;
fig. 6 is a schematic structural diagram of an array substrate including a dual-gate threshold compensation transistor according to an embodiment of the disclosure;
fig. 7a is a schematic structural diagram corresponding to a step of forming a first conductive pattern in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 7b is a schematic structural diagram corresponding to a step of forming a bump pattern in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 7c is a schematic structural diagram corresponding to a step of forming a second insulating structure in the method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 7d is a schematic structural diagram corresponding to a step of forming a second conductive pattern in the method for manufacturing an array substrate according to an embodiment of the disclosure.
Detailed Description
In order that those skilled in the art will better understand the technical solutions of the present disclosure, the present disclosure will be described in further detail with reference to the accompanying drawings and detailed description.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
In the embodiments of the present disclosure, the "patterning process" refers to a step of forming a structure having a specific pattern, which may be a photolithography process including one or more of forming a material layer, coating photoresist, exposing, developing, etching, photoresist stripping, and the like; of course, the "patterning process" may also be an imprinting process, an inkjet printing process, or other processes.
The array substrate of the conventional display device has a plurality of thin film transistors and capacitors each having an electrode plate, for example, a storage capacitor in a gate driving circuit of the display device for maintaining a voltage of each pixel region after the transistors are turned off. Fig. 1 is a schematic structural diagram of an array substrate in the prior art, as shown in fig. 1, a storage capacitor in the array substrate includes an upper polar plate 05 and a lower polar plate 03, a non-metal layer 04 between the upper polar plate 05 and the lower polar plate 03 is easy to break due to the action of stress, and after the break, a crack 06 appears at a corner of the non-metal layer 04, so that the upper polar plate 05 and the lower polar plate 03 of the storage capacitor are short-circuited, and an abnormality of a display circuit is caused.
In view of the foregoing, in a first aspect, an embodiment of the present disclosure provides an array substrate, and fig. 2 is a schematic structural diagram of the array substrate provided in the embodiment of the present disclosure, as shown in fig. 2, the array substrate includes a base 11, a first insulating structure, a first conductive pattern 14, a second insulating structure 15, and a second conductive pattern 16. Specifically, the first insulating structure is located on the substrate 11, the first conductive pattern 14 is located on a side of the first insulating structure facing away from the substrate 11, the second insulating structure 15 is located on a side of the first conductive pattern 14 facing away from the substrate 11, the second conductive pattern 16 is located on a side of the second insulating structure 15 facing away from the substrate 11, and an orthographic projection of the second conductive pattern 16 on the substrate 11 overlaps an orthographic projection of the first conductive pattern 14 on the substrate 11, wherein the first insulating structure includes a first insulating portion 13 and a second insulating portion 12, the first insulating portion 13 is located on a side of the second insulating portion 12 facing away from the substrate 11, and a lower surface of the first conductive pattern 14 overlaps an orthographic projection of an upper surface of the first insulating portion 13 on the substrate 11. The lower surface of the first conductive pattern 14 is a surface of the first conductive pattern 14 near the substrate 11, the upper surface of the first insulating portion 13 is a surface of the first insulating portion 13 far from the substrate 11, and the lower surface of the first insulating portion 13 is a surface of the first insulating portion 13 near the substrate 11.
It should be noted that, in this embodiment, the front projection of the lower surface of the first conductive pattern 14 and the upper surface of the first insulating portion 13 on the substrate 11 may completely overlap, or the non-overlapping area of the front projection of the lower surface of the first conductive pattern 14 and the upper surface of the first insulating portion 13 on the substrate 11 is also considered to overlap the front projection of the lower surface of the first conductive pattern 14 and the upper surface of the first insulating portion 13 on the substrate 11 within a preset error range.
In the present embodiment, the side surface of the first insulating portion 13 and the upper surface of the second insulating portion 12 are in contact to form a first dihedral angle, the second insulating structure 15 is in a second dihedral angle position, and the second insulating structure 15 is in contact with only the first insulating structure at the second dihedral angle position, that is, only the first insulating portion 13 and the second insulating portion 12 of the first insulating structure, and is not in contact with the first conductive pattern 14, it is to be noted that the upper surface of the second insulating portion 12 is the surface of the second insulating portion 12 on the side away from the substrate 11, and the side surface of the first insulating portion 13 is disposed between the upper surface and the upper surface of the first insulating portion 13.
In this embodiment, the substrate 11 may be made of transparent material such as glass or sapphire or flexible material such as PI. The materials of the first conductive pattern 14 and the second conductive pattern 16 may be the same or different, and the materials of the first insulating portion 13, the second insulating portion 12, and the second insulating structure 15 may be the same or different, and the embodiment of the present disclosure will be described taking as an example that the materials of the first conductive pattern 14 and the second conductive pattern 16 are the same, and the materials of the first insulating portion 13, the second insulating portion 12, and the second insulating structure 15 are the same. The materials of the first conductive pattern 14 and the second conductive pattern 16 may include: the single-layer or multi-layer composite laminate formed by one or more materials of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-neodymium alloy (AlNd), titanium (Ti) and copper (Cu) is preferably a single-layer or multi-layer composite film formed by Mo, al or alloy containing Mo and Al. The first insulating portion 13, the second insulating portion 12, and the second insulating structure 15 may each be silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), or the like, or a multilayer film composed of two or three thereof.
In this embodiment, the first insulating structure includes the first insulating portion 13, the lower surface of the first conductive pattern 14 overlaps with the orthographic projection of the upper surface of the first insulating portion 13 on the substrate 11, the first conductive pattern 14 is lifted by a certain height through the first insulating portion 13, so that the second insulating structure 15 contacts with the first insulating structure only at the second dihedral angle position, and when the array substrate is subjected to an external force, even if the second insulating structure 15 cracks at the second dihedral angle position, the cracks only extend in the direction of the first insulating portion 13 or the second insulating portion 12, but do not extend in the direction of the first conductive pattern 14, and therefore, the first conductive pattern 14 and the second conductive pattern 16 do not have a short circuit, thereby ensuring the normal operation of the display circuit in the array substrate.
In some embodiments, as shown in fig. 2, a buffer layer 17 may be disposed between the second insulating portion 12 and the substrate 11 in order to block moisture and oxygen, wherein the buffer layer 17 may be made of silicon nitride, silicon oxide, or the like.
In some embodiments, as shown in fig. 2, the thickness of the first insulating structure at the position where the first insulating portion 13 and the second insulating portion 12 are projected to overlap on the substrate 11 is greater than the thickness of the first insulating structure at the position where the first insulating portion 13 and the second insulating portion 12 are projected to not overlap on the substrate 11, in this way, the first conductive pattern 14 and the second conductive pattern 16 are prevented from shorting, which would cause defects.
To further prevent shorting of the first conductive pattern 14 to the second conductive pattern 16, the first insulating portion 13 is preferably 200-500 angstroms thick in some embodiments.
In some embodiments, fig. 3 is a schematic structural diagram of another array substrate provided in the embodiments of the present disclosure, where the array substrate shown in fig. 3 is modified on the basis of the array substrate shown in fig. 1, and as shown in fig. 3, the first insulating portion 13 and the second insulating portion 12 in fig. 2 together form a first insulating structure 18 of an integral structure in fig. 3, where the integral structure refers to a structure integrally formed by the same material and the same process and the same flow. In this embodiment, since the first insulating structure 18 has a protruding structure, the first conductive pattern 14 can be lifted to a certain height by the protruding structure, so that the second dihedral angle position of the second insulating structure 15, which is originally in contact with the first conductive pattern 14 and the first insulating structure 18, is only in contact with the first insulating structure 18, and when the array substrate is subjected to an external force, even if a crack occurs at the second dihedral angle position of the second insulating structure 15, the crack extends only in the direction of the first insulating structure 18, but does not extend in the direction of the first conductive pattern 14, and further the first conductive pattern 14 and the second conductive pattern 16 are not shorted, thereby ensuring the normal operation of the display circuit in the array substrate. And, set up the first insulating structure 18 as the unitary structure, reduced the manufacturing procedure of the array base plate, has saved manufacturing cost.
In some embodiments, as shown in fig. 3, a buffer layer 17 may be disposed between the first insulating structure 18 and the substrate 11 in order to block moisture and oxygen, wherein the buffer layer 17 may be made of silicon nitride, silicon oxide, or the like.
In some embodiments, the array substrate includes a display area and a non-display area surrounding the display area, a plurality of pixel units arranged in an array are disposed in the display area, and a pixel circuit is disposed in each pixel unit, where pixel units located in the same row are connected to the same gate line, and pixel units located in the same column are connected to the same data line. The non-display area is provided with a Gate On Array (GOA) which comprises a plurality of cascaded shift registers, wherein the shift registers are arranged in one-to-one correspondence with the Gate lines, i.e. each shift register is connected with one Gate line. When each frame of picture is displayed, a grid scanning signal is output to the corresponding grid line through the step-by-step shift register so as to finish progressive scanning of the pixel circuit, and each data line writes a data voltage signal into the pixel circuit of the row to lighten the pixel unit of the row when each row of grid line is scanned. Fig. 4 is a circuit diagram of an exemplary shift register, and as shown in fig. 4, the shift register includes a plurality of thin film transistors (first transistor M1 to eleventh transistor M11) and a first capacitor (C1). The source electrode and the grid electrode of the first transistor M1 are both connected with the Input signal end Input, and the drain electrode of the first transistor M1 is connected with the pull-up node PU; a source electrode of the second transistor M2 is connected with the pull-up node PU, a drain electrode of the second transistor M2 is connected with the low-level signal end VGL, and a grid electrode of the second transistor M2 is connected with the Reset signal end Reset; the source of the third transistor M3 is connected to the clock signal terminal CLK, the drain of the third transistor M3 is connected to the signal Output terminal Output, and the gate of the third transistor M3 is connected to the pull-up node PU; the source of the fourth transistor M4 is connected to the signal Output terminal Output, the drain of the fourth transistor M4 is connected to the low level signal terminal VGL, and the gate of the fourth transistor M4 is connected to the reset signal terminal Trst; a source of the fifth transistor M5 is connected to the first power voltage terminal VDD, a drain of the fifth transistor M5 is connected to the pull-down node PD, and a gate of the fifth transistor M5 is connected to a drain of the ninth transistor M9; a source pull-down node PD of the sixth transistor M6, a drain of the sixth transistor M6 being connected to the low-level signal terminal VGL, a gate of the sixth transistor M6 being connected to the pull-up node PU; a source of the seventh transistor M7 is connected to the pull-up node PU, a drain of the seventh transistor M7 is connected to the low-level signal terminal VGL, and a gate of the seventh transistor M7 is connected to the reset signal terminal Trst; the source electrode of the eighth transistor M8 is connected with the pull-down control circuit 4, the drain electrode of the eighth transistor M8 is connected with the low-level signal end VGL, and the gate electrode of the eighth transistor M8 is connected with the pull-up node PU; the source and gate of the ninth transistor M9 are connected to the first power supply voltage terminal VDD; a source of the tenth transistor M10 is connected to the pull-up node PU, a drain of the tenth transistor M10 is connected to the low-level signal terminal VGL, and a gate of the tenth transistor M10 is connected to the pull-down node PD; the source of the eleventh transistor M11 is connected to the signal Output terminal Output, the drain of the eleventh transistor M11 is connected to the low level signal terminal VGL, and the gate of the eleventh transistor M11 is connected to the pull-down node PD; the first polar plate of the first capacitor C1 is connected to the pull-up node PU, and the second polar plate of the first capacitor C1 is connected to the signal Output terminal Output.
In this embodiment, the specific structure of the first capacitor C1 may be the structure shown in fig. 2 or fig. 3, and this embodiment is described taking the specific structure of the first capacitor C1 as the structure shown in fig. 3 as an example, where the first conductive pattern 14 in fig. 3 corresponds to the first plate of the first capacitor C1, and the second conductive pattern 16 corresponds to the second plate of the first capacitor C1. Specifically, as shown in fig. 3, a first insulating structure 18 is disposed on the substrate 11, a first polar plate 14 is disposed on a side, facing away from the substrate 11, of the first insulating structure 18, a second insulating structure 15 is disposed on a side, facing away from the substrate 11, of the first polar plate 14, a second polar plate 16 is disposed on a side, facing away from the substrate 11, of the second insulating structure 15, an orthographic projection of the second polar plate 16 on the substrate 11 overlaps an orthographic projection of the first polar plate 14 on the substrate 11, the first insulating structure 18 includes a convex structure, and an orthographic projection of the first polar plate 14 on the substrate 11 overlaps an orthographic projection of the convex structure on the substrate 11.
With continued reference to fig. 4, the shift register circuit includes a plurality of thin film transistors (M1 to M11), and the transistors in the shift register are arranged with their gates in the same layer, with their active layers in the same layer, and with their sources and drains in the same layer. For convenience of description, only the positional relationship between the third thin film transistor M3 and the first capacitor C1 will be described as an example. For example: in this embodiment, the first plate 14 of the first capacitor C1 may be disposed in the same layer as the gate of the third thin film transistor M3, and the second plate 16 of the first capacitor C1 may be disposed in the same layer as the source and drain of the third thin film transistor M3.
In this embodiment, since the first insulating structure 18 has a protruding structure, the first electrode plate 14 can be lifted to a certain height by the protruding structure, so that the second dihedral angle position of the second insulating structure 15, which is originally in contact with the first electrode plate 14 and the first insulating structure 18, is changed to be in contact with only the first insulating structure 18, when the array substrate is subjected to an external force, even if a crack occurs at the second dihedral angle position of the second insulating structure 15, the crack extends only in the direction of the first insulating structure 18, but does not extend in the direction of the first electrode plate 14, and therefore, no short circuit occurs between the first electrode plate 14 and the second electrode plate 16, thereby ensuring the normal operation of the gate driving circuit. Because the electrode plates of the capacitor and the electrodes of the thin film transistor can be made of the same material, the first electrode plate 14 of the capacitor and the grid electrode of the thin film transistor can be arranged in the same layer, and the second electrode plate 16 of the capacitor and the source electrode and the drain electrode of the thin film transistor are arranged in the same layer, so that the process steps are reduced, and the manufacturing cost is saved.
It should be noted that, the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and the source and the drain of the transistors are symmetrical, so that the source and the drain are not different. In the embodiments of the present disclosure, to distinguish between the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a control pole. In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and the following embodiments are described by N-type transistors, where the N-type transistor is used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and when the gate inputs a high level, the source and drain are turned on, and the P-type is opposite. It is contemplated that implementation with P-type transistors will be readily apparent to those skilled in the art without undue burden and therefore are within the scope of the disclosed embodiments.
It should be further noted that, in the embodiment of the present disclosure, the shift register circuit may be a structure including other numbers of transistors and capacitors in addition to the structure shown in fig. 4, which is not illustrated one by one in the embodiment of the present disclosure.
In some embodiments, the array substrate includes a display area and a non-display area, in which a plurality of pixel units arranged in an array are disposed, and a pixel circuit is disposed in each pixel unit, and fig. 5 is an exemplary schematic diagram of a pixel circuit, and as shown in fig. 5, the pixel driving circuit includes a driving transistor T3, a data writing transistor T4, a threshold compensating transistor T2, a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, and a storage capacitor Cst. The source electrode of the data writing transistor T4 is electrically connected to the source electrode of the driving transistor T3, the first plate CC1 of the storage capacitor Cst is electrically connected to the first power supply terminal VDD, the second plate of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T3, the source electrode of the threshold compensating transistor T2 is electrically connected to the drain electrode of the driving transistor T3, the drain electrode of the threshold compensating transistor T2 is electrically connected to the gate electrode of the driving transistor T3, the drain electrode of the first reset transistor T1 is electrically connected to the gate electrode of the driving transistor T3, the drain electrode of the second reset transistor T7 is electrically connected to the first electrode D1 of the light emitting device D, the gate electrode of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2, the source electrode of the first light emitting control transistor T5 is electrically connected to the first power supply terminal VDD, the drain electrode of the first light emitting control transistor T5 is electrically connected to the source electrode of the driving transistor T3, the source electrode of the second light emitting control transistor T6 is electrically connected to the drain electrode of the driving transistor T3, and the first electrode D1 of the second light emitting control transistor T6 is electrically connected to the second power supply terminal VSS.
In the embodiment of the present disclosure, a dual gate type threshold compensation transistor T2 is taken as an example, and the specific structure of the dual gate type threshold compensation transistor T2 is shown in fig. 6, where the dual gate type threshold compensation transistor T2 includes a first gate 14, a second gate 16, an active layer 19, a source 21 and a drain 22. Specifically, the active layer 19 is disposed on the substrate 11, the first gate insulating layer 18 is disposed on a side of the active layer 19 facing away from the substrate 11, the first gate 14 is disposed on a side of the first gate insulating layer 18 facing away from the substrate 11, the second gate insulating layer 15 is disposed on a side of the first gate 14 facing away from the substrate 11, the second gate 16 is disposed on a side of the second gate insulating layer 15 facing away from the substrate 11, the interlayer insulating layer 20 is disposed on a side of the second gate 16 facing away from the substrate 11, the source 21 and the drain 22 are respectively connected with the active layer through vias, the orthographic projection of the second gate 16 on the substrate 11 overlaps with the orthographic projection of the first gate 14 on the substrate 11, the first gate insulating layer 18 includes a bump structure, and the orthographic projection of the first gate 14 on the substrate 11 overlaps with the orthographic projection of the bump structure on the substrate 11.
In this embodiment, since the first insulating structure 18 has a protruding structure, the first gate 14 can be lifted to a certain height by the protruding structure, so that the second dihedral angle position of the second gate insulating layer 15, which is originally in contact with the first gate 14 and the first gate insulating layer 18, becomes in contact with only the first gate insulating layer 18, and when the array substrate is subjected to an external force, even if a crack occurs at the second dihedral angle position of the second gate insulating layer 15, the crack extends only in the direction of the first gate insulating layer 18, but does not extend in the direction of the first gate 14, so that no short circuit occurs between the first gate 14 and the second gate 16, thereby ensuring the normal operation of the pixel driving circuit.
It will be appreciated that any structure of the pixel driving circuit having the double gate thin film transistor may be the structure of the thin film transistor shown in fig. 6, and the storage capacitor of the pixel driving circuit may be the capacitor structure shown in fig. 3, which will not be described herein by way of example.
It should be noted that, in the embodiment of the present disclosure, the pixel circuit of the sub-pixel may be a structure including other number of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, in addition to the 7T1C structure (i.e., seven transistors and one capacitor) shown in fig. 5, which is not limited in the embodiment of the present disclosure.
In some embodiments, the orthographic projection of the second conductive pattern onto the substrate may overlap the orthographic projection of the first conductive pattern onto the substrate, or the orthographic projection of the second conductive pattern onto the substrate overlaps the orthographic projection of the first conductive pattern onto the substrate. Preferably, as shown in fig. 3, the orthographic projection of the second conductive pattern 16 on the substrate covers the orthographic projection of the first conductive pattern 14 on the substrate 11.
In some embodiments, the thickness of the second insulating structure is greater than the thickness of the first insulating structure, preferably the first insulating structure may be 1000-1200 angstroms and the thickness of the second insulating structure 15 may be 1100-1300 angstroms.
In a second aspect, an embodiment of the present disclosure provides a method for manufacturing an array substrate, and fig. 7a to fig. 7d are schematic structural diagrams corresponding to each step in the method for manufacturing an array substrate provided in the embodiment of the present disclosure, where the embodiment is illustrated by taking a first insulating structure as an integrated structure, and the method for manufacturing an array substrate in this embodiment includes:
s701, sequentially forming a first insulating structure and a first metal layer on a substrate, and forming a first conductive pattern through a patterning process.
Specifically, as shown in fig. 7a, a buffer layer 72, a first insulating layer 73, and a first metal layer are sequentially deposited on a substrate 71, and then coated with a photoresist 75, exposed to light, developed, baked, and stripped off the photoresist, to obtain a first conductive pattern 74.
The material of the first insulating layer 73 may be silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), or the like, or a multilayer film composed of two or three thereof. The metal film layer comprises: the single-layer or multi-layer composite laminate formed by one or more materials of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-neodymium alloy (AlNd), titanium (Ti) and copper (Cu) is preferably a single-layer or multi-layer composite film formed by Mo, al or alloy containing Mo and Al. The thickness of the first insulating layer 73 may be selected according to practical situations, and in this embodiment, the thickness of the first insulating layer 73 is preferably 1000 to 1200 angstroms.
S702, forming a graph comprising a first insulating part through a one-time patterning process.
Specifically, as shown in fig. 7b, a pattern of the first insulating portion (i.e., a convex portion of the first insulating structure 73) is etched on the first insulating structure 73 by a dry etching process. The etching depth can be selected according to practical situations, and in this embodiment, the etching depth is preferably 200-500 angstroms.
S703, forming a second insulating structure on the first conductive pattern.
Specifically, as shown in fig. 7c, a second insulating structure 76 is deposited on the first conductive pattern 74. The material of the second insulating structure 76 may be silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), or the like, or a multilayer film composed of two or three thereof. The thickness of the second insulating structure 76 may be selected according to practical situations, and in this embodiment, it is preferable that the thickness of the second insulating structure 76 is 1100 to 1300 a.
And S704, forming a second metal layer on the second insulating structure, and forming a second conductive pattern through a patterning process, wherein the orthographic projection of the second conductive pattern on the substrate overlaps with the orthographic projection of the first conductive pattern on the substrate.
Specifically, as shown in fig. 7d, a second metal layer is deposited on the second insulating structure 76, and then photoresist coating, exposure, development, baking, and photoresist stripping are performed to obtain a second conductive pattern 77. The material of the second metal layer may be selected according to practical needs, and in this embodiment, preferably, the material of the second metal layer is the same as the material of the first metal layer.
In this embodiment, the pattern of the first insulating portion (i.e., the protruding portion of the first insulating structure 73) is etched on the first insulating structure 73, and the first conductive pattern 74 is lifted by the protruding structure, so that the corner portion in the second insulating structure 76 becomes only in contact with the first insulating structure 73 but not in contact with the first conductive pattern 74, and when the array substrate is subjected to an external force, even if a crack occurs at the second dihedral angle position of the second insulating structure 76, the crack extends only in the direction of the first insulating structure 73 but not in the direction of the first conductive pattern 74, and therefore the first conductive pattern 74 and the second conductive pattern 77 are not shorted, thereby ensuring the normal operation of the display circuit in the array substrate.
In a third aspect, an embodiment of the present disclosure provides a display device including the above array substrate. The display device can be a mobile phone, a tablet personal computer, a vehicle-mounted central control instrument and other terminal equipment, and the implementation effect of the display device is similar to that of the array substrate provided by the embodiment, and is not repeated here.
It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.
Claims (12)
1. An array substrate is characterized by comprising a substrate, a first insulating structure, a first conductive pattern, a second insulating structure and a second conductive pattern, wherein the first insulating structure is positioned on the substrate, the first conductive pattern is positioned on one side of the first insulating structure, which is away from the substrate, the second insulating structure is positioned on one side of the first conductive pattern, which is away from the substrate, the second conductive pattern is positioned on one side of the second insulating structure, which is away from the substrate, and the orthographic projection of the second conductive pattern on the substrate overlaps with the orthographic projection of the first conductive pattern on the substrate, wherein the first insulating structure comprises a first insulating part and a second insulating part, the first insulating part is positioned on one side of the second insulating part, which is away from the substrate, and the lower surface of the first conductive pattern overlaps with the orthographic projection of the upper surface of the first insulating part on the substrate;
the side surface of the first insulating portion and the upper surface of the second insulating portion are in contact to form a first dihedral angle, the second insulating structure is in a second dihedral angle position, and the second insulating structure is in contact with only the first insulating structure at the second dihedral angle position.
2. The array substrate of claim 1, wherein the first insulating portion and the second insulating portion are of unitary construction.
3. The array substrate of claim 1, wherein the orthographic projection of the second conductive pattern on the base covers the orthographic projection of the first conductive pattern on the base.
4. The array substrate of claim 1, wherein the thickness of the second insulating structure is greater than the thickness of the first insulating structure.
5. The array substrate of claim 1, wherein a thickness of the first insulating structure where the first insulating portion and the second insulating portion are projected to overlap on the base is greater than a thickness of the first insulating structure where the first insulating portion and the second insulating portion are projected to not overlap on the base.
6. The array substrate of claim 1, wherein the first insulating portion has a thickness of 200-500 angstroms.
7. The array substrate of claim 1, comprising a display region and a non-display region, wherein a gate driving circuit is disposed in the non-display region, the gate driving circuit comprising at least one capacitor having a first plate and a second plate, wherein the first conductive pattern and the second conductive pattern are the first plate and the second plate of the capacitor, respectively.
8. The array substrate of claim 7, wherein the gate driving circuit further comprises at least one thin film transistor, the thin film transistor comprising a gate electrode, a source electrode, and a drain electrode, the first conductive pattern being disposed in a same layer as the gate electrode of the thin film transistor, and the second conductive pattern being disposed in a same layer as the source electrode and the drain electrode of the thin film transistor.
9. The array substrate of claim 1, comprising a display region and a non-display region, wherein a pixel driving circuit is disposed in the display region, the pixel driving circuit comprising at least one thin film transistor, the thin film transistor comprising a first gate and a second gate, wherein the first conductive pattern and the second conductive pattern are the first gate and the second gate of the thin film transistor, respectively.
10. The array substrate according to any one of claims 1 to 9, wherein a buffer layer is provided between the first insulating structure and the base.
11. The preparation method of the array substrate is characterized by comprising the following steps:
sequentially forming a first insulating structure and a first metal layer on a substrate, and forming a first conductive pattern through a patterning process;
forming a graph comprising a first insulating part through a primary patterning process, wherein the first insulating structure comprises a first insulating part and a second insulating part, the first insulating part is positioned on one side of the second insulating part away from the substrate, and the lower surface of the first conductive pattern is overlapped with the orthographic projection of the upper surface of the first insulating part on the substrate;
forming a second insulating structure on the first conductive pattern;
forming a first dihedral angle at which the side surface of the first insulating portion and the upper surface of the second insulating portion are in contact, the second insulating structure forming a second dihedral angle at the first dihedral angle position, and the second insulating structure being in contact with only the first insulating structure at the second dihedral angle position;
and forming a second metal layer on the second insulating structure, and forming a second conductive pattern through a patterning process, wherein the orthographic projection of the second conductive pattern on a substrate overlaps with the orthographic projection of the first conductive pattern on the substrate.
12. A display device comprising the array substrate of any one of claims 1-10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110068843.5A CN112909019B (en) | 2021-01-19 | 2021-01-19 | Array substrate, preparation method of array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110068843.5A CN112909019B (en) | 2021-01-19 | 2021-01-19 | Array substrate, preparation method of array substrate and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112909019A CN112909019A (en) | 2021-06-04 |
| CN112909019B true CN112909019B (en) | 2023-06-06 |
Family
ID=76115580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110068843.5A Active CN112909019B (en) | 2021-01-19 | 2021-01-19 | Array substrate, preparation method of array substrate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112909019B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113571535B (en) * | 2021-07-23 | 2024-02-20 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1048668A (en) * | 1996-08-02 | 1998-02-20 | Sharp Corp | Liquid crystal display device and its production |
| JP2009099824A (en) * | 2007-10-18 | 2009-05-07 | Mitsubishi Electric Corp | Thin-film transistor device, display device and method of manufacturing the same |
| JP2010230781A (en) * | 2009-03-26 | 2010-10-14 | Sony Corp | Liquid crystal display device and method for manufacturing the same |
| CN107146818A (en) * | 2017-06-27 | 2017-09-08 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT), its preparation method, array base palte and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100507344B1 (en) * | 2003-04-17 | 2005-08-08 | 삼성에스디아이 주식회사 | Thin film transistor and method of fabricating the same |
| CN103137708B (en) * | 2012-04-13 | 2015-09-02 | 友达光电股份有限公司 | Active element and manufacturing method thereof |
| CN109742091B (en) * | 2019-01-10 | 2021-08-31 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
| CN110223990B (en) * | 2019-06-18 | 2022-03-08 | 京东方科技集团股份有限公司 | Top gate structure, preparation method thereof, array substrate and display device |
-
2021
- 2021-01-19 CN CN202110068843.5A patent/CN112909019B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1048668A (en) * | 1996-08-02 | 1998-02-20 | Sharp Corp | Liquid crystal display device and its production |
| JP2009099824A (en) * | 2007-10-18 | 2009-05-07 | Mitsubishi Electric Corp | Thin-film transistor device, display device and method of manufacturing the same |
| JP2010230781A (en) * | 2009-03-26 | 2010-10-14 | Sony Corp | Liquid crystal display device and method for manufacturing the same |
| CN107146818A (en) * | 2017-06-27 | 2017-09-08 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT), its preparation method, array base palte and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112909019A (en) | 2021-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111816691B (en) | Display substrate, manufacturing method thereof and display device | |
| US10254876B2 (en) | Array substrate, fabricating method thereof and display device | |
| JP4833799B2 (en) | Method for manufacturing pixel array substrate | |
| US11374074B2 (en) | Display panel, display apparatus, and method of fabricating the display panel | |
| WO2016179940A1 (en) | Oled pixel unit, transparent display apparatus and manufacturing method, and display device | |
| TWI415268B (en) | Thin film transistor device and pixel structure and driving circuit of display panel | |
| US8373836B2 (en) | Gate driver-on-array and method of making the same | |
| US11665940B2 (en) | Display substrate for avoiding breaks and preparation method thereof, bonding method of display panel and display apparatus | |
| US7196746B2 (en) | Pixel structure and manufacturing method thereof | |
| WO2020015493A1 (en) | Electrostatic protection circuit, array substrate and display device | |
| US11901375B2 (en) | Array substrate and method for manufacturing the same, and display apparatus | |
| JP2009036947A (en) | Method for manufacturing liquid crystal device, and liquid crystal device | |
| CN112909019B (en) | Array substrate, preparation method of array substrate and display device | |
| WO2024017060A1 (en) | Display substrate and display device | |
| US11900875B2 (en) | Display substrate and preparation method thereof, and display device | |
| US20230354655A1 (en) | Display Substrate, Preparation Method Thereof, and Display Apparatus | |
| CN110783368B (en) | Display panel, manufacturing method thereof and display terminal | |
| CN107393831B (en) | Thin film transistor, manufacturing method thereof and display panel | |
| WO2012005198A1 (en) | Method for manufacturing an active matrix substrate | |
| CN101976655B (en) | Thin film transistor substrate of liquid crystal display panel and manufacturing method thereof | |
| EP4297550A1 (en) | Display substrate and display apparatus | |
| US20240121997A1 (en) | Display Substrate, Preparation Method Thereof, and Display Apparatus | |
| JP2001183992A (en) | Active matrix substrate, its manufacturing method, electrooptical device and electronic instrument | |
| US20220317524A1 (en) | Array Substrate and Manufacturing Method Thereof, and Display Apparatus | |
| US20210313409A1 (en) | Display panel and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |