CN112908952B - Surrounding grid field effect transistor and preparation method thereof - Google Patents

Surrounding grid field effect transistor and preparation method thereof Download PDF

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CN112908952B
CN112908952B CN202110086420.6A CN202110086420A CN112908952B CN 112908952 B CN112908952 B CN 112908952B CN 202110086420 A CN202110086420 A CN 202110086420A CN 112908952 B CN112908952 B CN 112908952B
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nanowire
field effect
effect transistor
semiconductor substrate
heat dissipation
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CN112908952A (en
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刘新科
杨嘉颖
利健
宋利军
贺威
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Red And Blue Microelectronics Shanghai Co ltd
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Shenzhen University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731—Ceramic materials or glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3732—Diamonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides a surrounding grid field effect transistor and a preparation method thereof, wherein the surrounding grid field effect transistor comprises: a semiconductor substrate; the nanowire is positioned on the semiconductor substrate, a heat dissipation hole is formed in the nanowire, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nanowire; the heat dissipation piece is positioned in the heat dissipation hole. The heat generated by the surrounding grid field effect transistor can be effectively dissipated through the heat dissipation piece, so that the adverse effects of the rising of the internal temperature of the channel, the source region and the drain region of the surrounding grid field effect transistor on the performance and the service life of the device are avoided, and the device can keep normal operation for a long time.

Description

Surrounding grid field effect transistor and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gate-surrounding field effect transistor and a preparation method thereof.
Background
The Field Effect Transistor changes the width of a channel by using an electric Field Effect generated by an external voltage applied to a gate electrode and a source electrode, thereby controlling the magnitude of current between a drain electrode and the source electrode, namely, an important factor determining the efficiency of the Field Effect Transistor is the control capability of the gate electrode to the channel.
However, the Gate-All-Around Vertical Nanowire Metal-Oxide Semiconductor Field Effect Transistor (GAA VNWMOSFET) has attracted great attention and is widely applied due to its excellent Gate controllability. The existing GAA VNWMOSFET has the outstanding characteristics that: the control capability of the grid electrode on the channel is excellent, so that faster driving current can be generated; the width of the channel is allowed to be further reduced, so that the integration level is higher, low driving voltage, low threshold voltage, high switching current ratio, high current density and high power density can be realized, and the method is suitable for low power consumption application.
However, the conventional surrounding gate field effect transistor has a narrow channel width, which results in a high current density in the channel and thus generates high heat; however, the channel does not dissipate heat effectively, which causes the temperature inside the channel to be high, thereby adversely affecting the performance and lifetime of the device.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defect that the performance and the lifetime of the device are affected due to the difficulty in effective heat dissipation of the conventional surrounding gate field effect transistor, thereby providing a surrounding gate field effect transistor and a manufacturing method thereof.
The invention provides a gate-wrap field effect transistor, comprising: a semiconductor substrate; the nano wire is positioned on the semiconductor substrate and is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nano wire; and the heat dissipation piece is positioned in the heat dissipation hole.
Optionally, the thermal conductivity of the heat sink is greater than or equal to 300W/(m × K).
Optionally, the heat sink is an insulating heat sink.
Optionally, the material of the heat sink comprises diamond or aluminum nitride ceramic.
Optionally, the ratio of the diameter of the heat dissipation hole to the diameter of the nanowire is 0.33 to 0.75.
Optionally, the diameter of the nanowire is 80nm to 180nm; the diameter of the heat dissipation hole is 60nm-100nm.
Optionally, the nanowire is in a ring structure; the heat dissipation hole penetrates through the nanowire along the extension direction of the nanowire.
Optionally, the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor, and the nanowire is perpendicular to the surface of the semiconductor substrate; or, the surrounding gate field effect transistor is a horizontal surrounding gate field effect transistor, and the nanowire is parallel to the surface of the semiconductor substrate.
Optionally, the semiconductor substrate includes a SiC-based semiconductor substrate, a GaN-based semiconductor substrate, or a silicon-based semiconductor substrate.
The invention also discloses a preparation method of the gate-surrounding field effect transistor, which comprises the following steps: providing a semiconductor substrate; forming a nanowire on the semiconductor substrate, wherein the nanowire is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nanowire; and forming a heat dissipation part in the heat dissipation hole.
Optionally, the preparation method of the nanowire comprises: forming an initial nanowire on the semiconductor substrate; etching the initial nanowire so that the initial nanowire forms the nanowire.
Optionally, before etching the initial nanowire, the method further includes: forming a barrier layer on the sidewalls and a portion of the top surface of the initial nanowire, the barrier layer having an opening therein that exposes a portion of the top surface of the initial nanowire; etching the initial nanowire by taking the barrier layer as a mask; and removing the barrier layer after etching the initial nanowire by taking the barrier layer as a mask.
Optionally, the process of etching the initial nanowire by using the barrier layer as a mask includes an anisotropic etching process.
Optionally, the parameters of the anisotropic etching process include: the etching gas used includes Cl 2 And SiCl 4 。
Optionally, the process for forming the heat dissipation member in the heat dissipation hole includes: a metal organic compound chemical vapor deposition process.
The technical scheme of the invention has the following advantages:
1. the gate-surrounding field effect transistor comprises a semiconductor substrate, a nanowire positioned on the semiconductor substrate and a radiating piece positioned in a radiating hole of the nanowire, wherein heat generated by the gate-surrounding field effect transistor can be effectively radiated through the radiating piece, so that adverse effects on the performance and the service life of a device caused by the increase of the internal temperature of a channel, a source region and a drain region of the gate-surrounding field effect transistor are avoided, and the device can keep normal operation for a long time. Secondly, most of current generated when the surrounding grid field effect transistor is switched on is suitable for being transmitted in a region near the surface of the outer side wall of the nanowire, and the extending direction of the heat radiating hole is parallel to the extending direction of the nanowire, so that the heat radiating piece in the heat radiating hole cannot block the current transmission on the nanowire, and the normal work of the surrounding grid field effect transistor is ensured.
2. According to the field effect transistor surrounding the grid electrode, the heat dissipation piece is an insulating heat dissipation piece. By arranging the heat dissipation member in the nanowire and limiting the heat dissipation member to be an insulating heat dissipation member, the region near the central axis of the nanowire cannot be subjected to current circulation, so that all current is concentrated in the region near the surface of the outer side wall of the nanowire, and the output current density is improved.
3. According to the field effect transistor with the surrounding grid electrode, the ratio of the diameter of the heat dissipation hole to the diameter of the nanowire is limited to be 0.33-0.75, so that on one hand, the heat dissipation capability of a heat dissipation piece located in the heat dissipation hole is guaranteed, on the other hand, the field effect transistor with the surrounding grid electrode has high output current density, and the performance of the field effect transistor with the surrounding grid electrode is improved.
4. According to the preparation method of the gate-surrounding field effect transistor, the nanowire is formed on the semiconductor substrate, the nanowire is provided with the heat dissipation hole, and the heat dissipation part is formed in the heat dissipation hole, so that heat generated by the gate-surrounding field effect transistor can be effectively dissipated through the heat dissipation part, adverse effects on the performance and the service life of a device caused by the increase of the internal temperature of the channel, the source region and the drain region of the gate-surrounding field effect transistor are avoided, and the device can keep long-time normal operation. Secondly, most of current generated when the surrounding grid field effect transistor is switched on is suitable for being transmitted in a region near the surface of the outer side wall of the nanowire, and the extending direction of the heat radiating hole is parallel to the extending direction of the nanowire, so that the heat radiating piece in the heat radiating hole cannot block the current transmission on the nanowire, and the normal work of the surrounding grid field effect transistor is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a surrounding gate field effect transistor according to embodiment 1 of the present invention;
fig. 2 is a process flow diagram of a method for fabricating a surrounding gate field effect transistor provided in embodiment 2;
fig. 3-14 are schematic structural diagrams in the process of manufacturing the surrounding gate field effect transistor provided in embodiment 2;
fig. 15 is an output characteristic curve of the surrounding gate field effect transistors provided in example 1 and comparative example 1;
description of reference numerals:
1-a semiconductor substrate; 2-a nanowire; 21-a drain region; 22-a channel region; a 23-source region; 3-a heat sink; 4-a gate dielectric layer; 5-gate electrode layer; 6-an electrical isolation layer; 7-a source electrode layer; 8-a drain electrode layer; 9-initial nanowire.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "inside", "outside", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1
Referring to fig. 1, the present embodiment provides a gate-all-around field effect transistor, including: a semiconductor substrate 1; a nanowire 2 positioned on the semiconductor substrate 1, wherein the nanowire 2 is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nanowire 2; and the heat dissipation piece 3 is positioned in the heat dissipation hole.
The heat generated by the surrounding grid field effect transistor can be effectively radiated through the radiating piece 3, so that the adverse effects on the performance and the service life of the device caused by the rise of the internal temperature of the surrounding grid field effect transistor are avoided, and the device can keep normal operation for a long time; meanwhile, the current generated when the surrounding grid field effect transistor is conducted is suitable for being transmitted along the nanowire 2, and the extending direction of the heat dissipation hole is parallel to the extending direction of the nanowire 2, so that the heat dissipation piece 3 in the heat dissipation hole cannot obstruct the current transmission on the nanowire 2, and the normal work of the surrounding grid field effect transistor is ensured.
In the present embodiment, the semiconductor substrate 1 includes, but is not limited to, a SiC-based semiconductor substrate, a GaN-based semiconductor substrate, or a silicon-based semiconductor substrate; specifically, the thickness of the semiconductor substrate 1 is 250 μm to 350 μm. Preferably, the semiconductor substrate 1 is a GaN-based semiconductor substrate.
Further, the semiconductor substrate 1 is an N-type semiconductor substrate. Specifically, when the semiconductor substrate 1 is a GaN-based semiconductor substrate, the dopant in the semiconductor substrate 1 includes, but is not limited to, silicon; when the semiconductor substrate 1 is a SiC-based semiconductor substrate or a silicon-based semiconductor substrate, the dopant species in the semiconductor substrate 1 includes, but is not limited to, phosphorus; further, the doping concentration of the doping substance in the semiconductor substrate 1 is 3 × 10 18 cm -3 -8×10 18 cm -3 。
In the present embodiment, the thermal conductivity of the heat sink 3 is greater than or equal to 300W/(m × K). Further, the heat sink is an insulating heat sink. When the field effect transistor is turned on, usually most of current flows through the region near the surface of the outer side wall of the nanowire 2, and a small part of current flows through the region near the central axis of the nanowire 2, and the heat dissipation member 3 is arranged in the nanowire 2, and the material of the heat dissipation member 3 is limited to be an insulating material, so that the region near the central axis of the nanowire 2 cannot be subjected to current circulation, all current is concentrated in the region near the surface of the outer side wall of the nanowire 2, and the output current density is improved. Specifically, the material of the heat sink 3 includes, but is not limited to, diamond or aluminum nitride ceramic. In one embodiment, the material of the heat spreader 3 is diamond.
In this embodiment, the ratio of the diameter of the heat dissipation hole to the diameter of the nanowire 2 is 0.33 to 0.75. By limiting the ratio of the diameter of the heat dissipation hole to the diameter of the nanowire 2, on one hand, the heat dissipation capability of the heat dissipation piece located in the heat dissipation hole is guaranteed, on the other hand, the heat dissipation piece has high output current density, and the performance of the field effect transistor surrounding the grid electrode is improved.
Specifically, the diameter of the nanowire 2 is 80nm-180nm; the diameter of the heat dissipation hole is 60nm-100nm. Illustratively, the nanowires 2 have a diameter of 80nm, 100nm, 120nm, 140nm, 160nm, 180nm; the diameters of the heat dissipation holes are 60nm, 70nm, 80nm, 90nm and 100nm. Preferably, the diameter of the nanowire 2 is 120nm, and the diameter of the heat dissipation hole is 80nm.
In this embodiment, the material of the nanowire 2 is an N-type semiconductor material. Further, the material of the nanowire 2 includes but is not limited to gallium nitride, and the doped material includes but is not limited to silicon; preferably, when the semiconductor substrate 1 is a GaN-based semiconductor substrate, the nanowire 2 is made of gallium nitride, so that the semiconductor substrate is more compatible with the nanowire 2, and the doped material of the nanowire 2 is silicon.
Referring to fig. 1, in this embodiment, the nanowire 2 includes a channel region and a source region and a drain region respectively located at two sides of the channel region, and the drain region, the channel region, and the source region are arranged along an extending direction of the nanowire 2. Further, the doping concentration of the channel region 22 is less than that of the drain region 21, and the doping concentration of the channel region 22 is less than that of the source region 23; in one embodiment, the doping concentration of the drain region 21 is equal to the doping concentration of the source region 23. Specifically, the doping concentration of the drain region 21 is 1 × 10 18 cm -3 -4x10 18 cm -3 The doping concentration of the channel region 22 is 1x10 15 cm -3 -8x10 15 cm -3 The doping concentration of the source region 23 is 1x10 18 cm -3 -4x10 18 cm -3 . Preferably, the doping concentration of the drain region 21 is 2 × 10 18 cm -3 The doping concentration of the channel region 22 is 5x10 15 cm -3 The doping concentration of the source region 23 is 2x10 18 cm -3 。
Further, along the extension direction of the nanowire 2, the size of the channel region 22 is larger than that of the drain region 21, and the size of the channel region 22 is equal to that of the source region 23; in an embodiment, the size of the drain region 21 is equal to the size of the source region 23 along the extension direction of the nanowire. Specifically, along the extension direction of the nanowire, the size of the drain region 21 is 0.2 μm to 0.5 μm, the size of the channel region 22 is 0.3 μm to 0.6 μm, and the size of the source region 23 is 0.2 μm to 0.5 μm. Preferably, along the extension direction of the nanowire, the size of the drain region 21 is 0.3 μm, the size of the channel region 22 is 0.4 μm, and the size of the source region 23 is 0.3 μm.
In the present embodiment, the nanowire 2 has a ring structure; the radiating holes penetrate through the nanowires 2 along the extending direction of the nanowires 2, both ends of the radiating pieces 3 can radiate heat, and the heat in the nanowires 2 is transmitted out by the radiating pieces 3, so that the radiating speed of the surrounding grid field effect transistor is improved.
Further, in one embodiment, referring to fig. 1, the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor, and the nanowire 2 is perpendicular to the surface of the semiconductor substrate 1. In this case, the bottom surface of the nanowire 2 is in contact with the surface of the semiconductor substrate 1. When the heat dissipation hole penetrates through the nanowire 2 along the extending direction of the nanowire 2, the heat dissipation member 3 is also in contact with the surface of the semiconductor substrate 1, so that one end of the heat dissipation member 3 can transmit heat to the semiconductor substrate 1 and the heat is transmitted out from the semiconductor substrate 1, and the other end of the heat dissipation member 3 can transmit the heat to the outside, thereby improving the heat dissipation speed of the surrounding gate field effect transistor.
In another embodiment, the surrounding gate field effect transistor is a horizontal surrounding gate field effect transistor, and the nanowire 2 is parallel to the surface of the semiconductor substrate 1. The heat generated at different positions in the nano wire 2 can be transmitted to the heat dissipation member 3 at a higher speed, and the heat dissipation member 3 transmits the heat out, so that the heat dissipation speed of the surrounding grid field effect transistor is improved.
Referring to fig. 1, in the present embodiment, the surrounding gate field effect transistor further includes: and the gate structure is positioned on the semiconductor substrate 1 and surrounds the channel region 22. The gate structure includes: a gate dielectric layer surrounding the channel region4; and the gate electrode layer 5 surrounds the channel region 22 and is positioned outside the gate dielectric layer 4. Specifically, the material of the gate dielectric layer 4 includes, but is not limited to, al 2 O 3 Or SiO 2 The material of the gate electrode layer 5 includes, but is not limited to, chromium. In this embodiment, when the surrounding gate fet is a vertical surrounding gate fet, the gate dielectric layer 4 surrounds the channel region 22 and extends to the surface of the semiconductor substrate 1, so that the gate dielectric layer 4 is "L" shaped.
Referring to fig. 1, in the present embodiment, the surrounding gate field effect transistor further includes: and the source electrode layer 7 and the drain electrode layer 8 are positioned on two sides of the gate structure, the source electrode layer 7 is electrically connected with the source region 23, and the drain electrode layer 8 is electrically connected with the drain region 21.
Specifically, when the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor, the source electrode layer 7 is located on the side of the gate structure away from the semiconductor substrate 1, and the drain electrode layer 8 is located on the side of the semiconductor substrate 1 away from the gate structure; further, an electrical isolation layer 6 is disposed between the gate structure and the source electrode layer 7.
Further, the material of the electrical isolation layer 6 includes, but is not limited to, silicon dioxide; the source electrode layer 7 comprises a first titanium layer, a first aluminum layer, a first nickel layer and a first gold layer which are sequentially stacked, the first titanium layer is in contact with the electric isolation layer 6, the arrangement direction of the first titanium layer, the first aluminum layer, the first nickel layer and the first gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the first titanium layer is 20nm-30nm, the thickness of the first aluminum layer is 70nm-80nm, the thickness of the first nickel layer is 0nm-30nm, and the thickness of the first gold layer is 70nm-80nm; or, the material of the source electrode layer 7 is gold, and the thickness of the source electrode layer 7 is 150nm-250nm; by defining the source electrode layer 7 as the above material, a good ohmic contact between the source electrode layer 7 and the source region is ensured, and it is understood that the material of the source electrode layer 7 includes, but is not limited to, the above materials; the drain electrode layer 8 comprises a second titanium layer, a second aluminum layer, a second nickel layer and a second gold layer which are sequentially stacked, the second titanium layer is in contact with the semiconductor substrate 1, the arrangement direction of the second titanium layer, the second aluminum layer, the second nickel layer and the second gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the second titanium layer is 20nm-30nm, the thickness of the second aluminum layer is 70nm-80nm, the thickness of the second nickel layer is 0nm-30nm, and the thickness of the second gold layer is 70nm-80nm; or the drain electrode layer 8 is made of gold, and the thickness of the drain electrode layer 8 is 150nm-250nm; by defining the drain electrode layer 8 as a material as described above, a good ohmic contact between the drain electrode layer 8 and the drain region is ensured, and it is to be understood that the material of the drain electrode layer 8 includes, but is not limited to, the above materials.
Example 2
Referring to fig. 2, the present embodiment provides a method for manufacturing a gate-all-around field effect transistor, including the following steps:
s1, providing a semiconductor substrate 1;
s2, forming a nanowire 2 on the semiconductor substrate 1, wherein the nanowire 2 is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nanowire 2;
and S3, forming a heat dissipation piece 3 in the heat dissipation hole.
According to the preparation method of the gate-surrounding field effect transistor, the nanowire 2 is formed on the semiconductor substrate 1, the nanowire 2 is provided with the heat dissipation hole, and the heat dissipation part 3 is formed in the heat dissipation hole, so that heat generated by the gate-surrounding field effect transistor can be effectively dissipated through the heat dissipation part, adverse effects on the performance and the service life of a device caused by the increase of the internal temperature of the channel, the source region and the drain region of the gate-surrounding field effect transistor are avoided, and the device can keep long-time normal work. Secondly, most of the current generated when the surrounding gate field effect transistor is conducted is suitable for being transmitted in the area near the surface of the outer side wall of the nanowire, and the extending direction of the heat dissipation hole is parallel to the extending direction of the nanowire, so that the heat dissipation piece in the heat dissipation hole cannot obstruct the current transmission on the nanowire, and the normal work of the surrounding gate field effect transistor is ensured.
The technical solution of the present invention will be clearly and completely described with reference to fig. 3-14.
Referring to fig. 3, in step S1, a semiconductor substrate 1 is provided.
Specifically, the semiconductor substrate 1 includes, but is not limited to, a SiC-based semiconductor substrate, a GaN-based semiconductor substrate, or a silicon-based semiconductor substrate; specifically, the thickness of the semiconductor substrate 1 is 250 μm to 350 μm. Preferably, the semiconductor substrate 1 is a GaN-based semiconductor substrate.
Further, the semiconductor substrate 1 is an N-type semiconductor substrate. Specifically, when the semiconductor substrate 1 is a GaN-based semiconductor substrate, the dopant in the semiconductor substrate 1 includes, but is not limited to, silicon; when the semiconductor substrate 1 is a SiC-based semiconductor substrate or a silicon-based semiconductor substrate, the dopant species in the semiconductor substrate 1 includes, but is not limited to, phosphorus; further, the doping concentration of the doping substance in the semiconductor substrate 1 is 3 × 10 18 cm -3 -8×10 18 cm -3 。
Referring to fig. 4-8, in step S2, a nanowire 2 is formed on the semiconductor substrate 1, and the nanowire 2 has a thermal via therein, and an extending direction of the thermal via is parallel to an extending direction of the nanowire 2.
Specifically, the preparation method of the nanowire 2 comprises the following steps: forming an initial nanowire 9 on the semiconductor substrate 1; the initial nanowire 9 is etched such that the initial nanowire forms the nanowire 2.
Wherein the step of forming the initial nanowire 9 comprises: referring to fig. 4, a first semiconductor film is formed on the surface of the semiconductor substrate 1; referring to fig. 5, a second semiconductor film is formed on a surface of the first semiconductor film; referring to fig. 6, a third semiconductor film is formed on a surface of the second semiconductor film; referring to fig. 7, a third semiconductor film, a second semiconductor film and the first semiconductor film are patterned to form a cylindrical initial nanowire 9, the initial nanowire 9 includes a channel region 22 and a source region 23 and a drain region 21 respectively located at both sides of the channel region, the drain region 21, the channel region 22 and the source region 23 are arranged along an extending direction of the nanowire 2, the drain region 21 is formed by the patterned first semiconductor film, the channel region 22 is formed by the patterned second semiconductor film, and the source region 23 is formed by the patterned third semiconductor film.
Further, the method of forming the first semiconductor film, the second semiconductor film, and the third semiconductor film on the surface of the semiconductor substrate 1 is a Metal Organic Chemical Vapor Deposition (MOCVD) process; obtaining an initial nanowire 9 by sequentially performing dry etching and wet etching on the third semiconductor film, the second semiconductor film and the first semiconductor film 3, wherein a gas used for the dry etching includes Cl 2 And SiCl 4 The solution used for wet etching includes a tetramethylammonium hydroxide (TMAH) solution.
In this embodiment, the material of the nanowire 2 is an N-type semiconductor material. Further, the material of the nanowire 2 includes, but is not limited to, gallium nitride, and the doped material includes, but is not limited to, silicon; preferably, when the semiconductor substrate 1 is a GaN-based semiconductor substrate, the nanowire 2 is made of gallium nitride, so that the semiconductor substrate is more compatible with the nanowire 2, and at this time, the doped material of the nanowire 2 is silicon.
Further, the doping concentration of the channel region 22 is less than that of the drain region 21, and the doping concentration of the channel region 22 is less than that of the source region 23; in one embodiment, the doping concentration of the drain region 21 is equal to the doping concentration of the source region 23. Specifically, the doping concentration of the drain region 21 is 1 × 10 18 cm -3 -4x10 18 cm -3 The doping concentration of the channel region 22 is 1x10 15 cm -3 -8x10 15 cm -3 The doping concentration of the source region 23 is 1x10 18 cm -3 -4x10 18 cm -3 . Preferably, the doping concentration of the drain region 21 is 2 × 10 18 cm -3 The doping concentration of the channel region 22 is 5x10 15 cm -3 The doping concentration of the source region 23 is 2x10 18 cm -3 。
Further, along the extension direction of the nanowire 2, the size of the channel region 22 is larger than that of the drain region 21, and the size of the channel region 22 is equal to that of the source region 23; in an embodiment, the size of the drain region 21 is equal to the size of the source region 23 along the extension direction of the nanowire. Specifically, along the extension direction of the nanowire, the size of the drain region 21 is 0.2 μm to 0.5 μm, the size of the channel region 22 is 0.3 μm to 0.6 μm, and the size of the source region 23 is 0.2 μm to 0.5 μm. Preferably, along the extension direction of the nanowire, the size of the drain region 21 is 0.3 μm, the size of the channel region 22 is 0.4 μm, and the size of the source region 23 is 0.3 μm.
Further, the diameter of the nanowire 2 is 80nm-180nm; illustratively, the nanowires 2 have a diameter of 80nm, 100nm, 120nm, 140nm, 160nm, 180nm; preferably, the diameter of the nanowire 2 is 120nm.
Referring to fig. 8, in step S2, the step of etching the initial nanowire 9 includes: forming a barrier layer on the sidewalls and a portion of the top surface of the initial nanowire 9, the barrier layer having an opening therein that exposes a portion of the top surface of the initial nanowire 9; etching the initial nanowire 9 by using the barrier layer as a mask; and removing the barrier layer after etching the initial nanowire by taking the barrier layer as a mask.
Specifically, the process for etching the initial nanowire by using the barrier layer as a mask comprises an anisotropic etching process, wherein the anisotropic etching process comprises dry etching, and the adopted etching gas comprises Cl 2 And SiCl 4 (ii) a The material of the barrier layer includes but is not limited to phenolic resin; the diameter of the heat dissipation hole is 60nm-100nm. Illustratively, the diameter of the thermal via is 60nm, 70nm, 80nm, 90nm, 100nm; preferably, the diameter of the thermal via is 80nm.
In the present embodiment, the nanowire 2 has a ring structure; the heat dissipation hole penetrates the nanowire 2 along the extension direction of the nanowire 2.
Referring to fig. 9, in step S3, a heat sink 3 is formed within the heat radiating hole.
Specifically, the material of the heat sink 3 includes, but is not limited to, diamond or aluminum nitride ceramic. The process for forming the heat sink 3 in the heat dissipation hole includes: metal Organic Chemical Vapor Deposition (MOCVD) processes.
Referring to fig. 10 to 14, in the present embodiment, the method for manufacturing the gate-around field effect transistor further includes the following steps: forming a gate structure on the semiconductor substrate 1, wherein the gate structure surrounds the channel region; and forming a source electrode layer 7 and a drain electrode layer 8 on two sides of the gate structure, wherein the source electrode layer 7 is electrically connected with the source region 23, and the drain electrode layer 8 is electrically connected with the drain region 21.
The preparation of the grid structure comprises the following steps: forming a gate dielectric layer 4 surrounding the channel region; and forming a gate electrode layer 5 which surrounds the channel region 22 and is positioned outside the gate dielectric layer 4. Specifically, the material of the gate dielectric layer 4 includes, but is not limited to, al 2 O 3 Or SiO 2 The material of the gate electrode layer 5 includes, but is not limited to, chromium. In one embodiment, the gate dielectric layer 4 completely covers the outer surface of the channel region 22 and exposes the source region 23. In this embodiment, when the surrounding gate fet is a vertical surrounding gate fet, the gate dielectric layer 4 surrounds the channel region 22 and extends to the surface of the semiconductor substrate 1, so that the gate dielectric layer 4 is "L" shaped.
Specifically, when the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor, the source electrode layer 7 is formed on the side of the gate structure away from the semiconductor substrate 1, and the drain electrode layer 8 is formed on the side of the semiconductor substrate 1 away from the gate structure; further, before forming the source electrode layer 7, forming an electrical isolation layer 6 on a side of the gate structure facing away from the semiconductor substrate 1, wherein after forming the source electrode layer 7, the electrical isolation layer 6 is located between the gate structure and the source electrode layer 7.
It is to be understood that, as shown in fig. 10-14, after the nanowire 2 is formed, the gate dielectric layer 4 is formed, the drain electrode layer 8 is formed, and then the gate electrode layer 5, the electrical isolation layer 6 and the source electrode layer 7 are sequentially formed; after the nanowire 2 is formed, the gate dielectric layer 4, the gate electrode layer 5, the electrical isolation layer 6 and the source electrode layer 7 may be formed in sequence, and then the drain electrode layer 8 may be formed. The formation sequence of the gate dielectric layer 4, the gate electrode layer 5, the drain electrode layer 8, the electrical isolation layer 6 and the source electrode layer 7 can be adjusted as required.
Specifically, the material of the electrical isolation layer 6 includes, but is not limited to, silicon dioxide; the source electrode layer 7 comprises a first titanium layer, a first aluminum layer, a first nickel layer and a first gold layer which are sequentially stacked, the first titanium layer is in contact with the electric isolation layer 6, the arrangement direction of the first titanium layer, the first aluminum layer, the first nickel layer and the first gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the first titanium layer is 20nm-30nm, the thickness of the first aluminum layer is 70nm-80nm, the thickness of the first nickel layer is 0nm-30nm, and the thickness of the first gold layer is 70nm-80nm; or, the material of the source electrode layer 7 is gold, and the thickness of the source electrode layer 7 is 150nm-250nm; by defining the source electrode layer 7 to be the above material, good ohmic contact between the source electrode layer 7 and the source region is ensured, and it is understood that the material of the source electrode layer 7 includes but is not limited to the above material; the drain electrode layer 8 comprises a second titanium layer, a second aluminum layer, a second nickel layer and a second gold layer which are sequentially stacked, the second titanium layer is in contact with the semiconductor substrate 1, the arrangement direction of the second titanium layer, the second aluminum layer, the second nickel layer and the second gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the second titanium layer is 20nm-30nm, the thickness of the second aluminum layer is 70nm-80nm, the thickness of the second nickel layer is 0nm-30nm, and the thickness of the second gold layer is 70nm-80nm; or the drain electrode layer 8 is made of gold, and the thickness of the drain electrode layer 8 is 150nm-250nm; by defining the drain electrode layer 8 as a material as described above, a good ohmic contact between the drain electrode layer 8 and the drain region is ensured, and it is to be understood that the material of the drain electrode layer 8 includes, but is not limited to, the above materials. .
In this embodiment, adoptForming the gate dielectric layer 4 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or an Atomic Layer Deposition (ALD) method; forming a metal film by thermal evaporation, magnetron sputtering or electron beam evaporation, and depositing the metal film on the N 2 Annealing at 600-700 ℃ under the environment to obtain the gate electrode layer 5; forming the electrical isolation layer 6 using a Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atomic Layer Deposition (ALD) method; forming a metal film by thermal evaporation, magnetron sputtering or electron beam evaporation, and depositing the metal film on the N 2 Annealing is carried out at 600-700 ℃ under the environment to obtain the drain electrode layer 8.
Comparative example 1
This comparative example provides a surrounding gate field effect transistor which differs from the surrounding gate field effect transistor provided in example 1 in that: the nanowires do not have thermal holes.
Test examples
Simulation was performed on the gate-around field effect transistor provided in example 1 and the gate-around field effect transistor provided in comparative example 1 by using simulation software, in which the voltage of the gate electrode layer was 2V, and the material of the heat sink in the gate-around field effect transistor provided in example 1 was diamond. The results are shown in FIG. 15. In the figure, the horizontal axis represents the drain voltage, the unit of which is V; the vertical axis represents the drain-source output current density, which has a unit of MA/cm 2 . As can be seen from fig. 15, the output characteristic curve of the surrounding gate field effect transistor provided in comparative example 1 starts to decrease after a voltage of 2V (i.e., point a) as the drain voltage increases, because the device performance deteriorates due to the temperature rise in the surrounding gate field effect transistor; with the increase of the drain voltage, the output characteristic curve of the surrounding gate field effect transistor provided in embodiment 1 does not decrease in the drain-source output current density after the voltage 2V (i.e., point a), but remains in a steady state, because the heat in the surrounding gate field effect transistor is transferred by the heat sink and the internal temperature thereof is within a normal range, the device can normally operate. In addition, it is to be noted that embodiment 1 provides a drain-source output current of a surrounding gate field effect transistorThe density gradually increases.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (14)

1. A wrap gate field effect transistor, comprising:
a semiconductor substrate;
the nano wire is positioned on the semiconductor substrate and is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nano wire;
and the heat dissipation piece is positioned in the heat dissipation hole, and the thermal conductivity of the heat dissipation piece is more than or equal to 300W/(m & ltK).
2. The surround gate field effect transistor of claim 1, wherein the heat sink is an insulating heat sink.
3. A surrounding gate field effect transistor according to claim 1 or 2, wherein the material of the heat spreader comprises diamond or aluminium nitride ceramic.
4. The wrap gate field effect transistor of claim 1, wherein a ratio of a diameter of the thermal via to a diameter of the nanowire is between 0.33 and 0.75.
5. The wrap gate field effect transistor of claim 4, wherein the nanowires have a diameter of 80nm to 180nm; the diameter of the heat dissipation hole is 60nm-100nm.
6. The wrap gate field effect transistor of claim 1, wherein the nanowire is in a ring structure; the heat dissipation hole penetrates through the nanowire along the extension direction of the nanowire.
7. The surround-gate field effect transistor of claim 1, wherein the surround-gate field effect transistor is a vertical surround-gate field effect transistor, the nanowire being perpendicular to a surface of the semiconductor substrate;
or, the surrounding gate field effect transistor is a horizontal surrounding gate field effect transistor, and the nanowire is parallel to the surface of the semiconductor substrate.
8. The wrap gate field effect transistor of claim 1, wherein the semiconductor substrate comprises a SiC-based semiconductor substrate, a GaN-based semiconductor substrate, or a silicon-based semiconductor substrate.
9. A method of fabricating a surrounding gate field effect transistor according to any of claims 1 to 8, comprising the steps of:
providing a semiconductor substrate;
forming a nanowire on the semiconductor substrate, wherein the nanowire is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nanowire;
and forming a heat dissipation part in the heat dissipation hole.
10. The method of fabricating a surrounding gate field effect transistor according to claim 9, wherein the method of fabricating the nanowire comprises: forming an initial nanowire on the semiconductor substrate; etching the initial nanowire so that the initial nanowire forms the nanowire.
11. The method of claim 10, further comprising, prior to etching the initial nanowire: forming a barrier layer on the sidewalls and a portion of the top surface of the initial nanowire, the barrier layer having an opening therein that exposes a portion of the top surface of the initial nanowire; etching the initial nanowire by taking the barrier layer as a mask; and removing the barrier layer after etching the initial nanowire by taking the barrier layer as a mask.
12. The method of claim 11, wherein the etching of the initial nanowire with the barrier layer as a mask comprises an anisotropic etching process.
13. The method of claim 12, wherein the parameters of the anisotropic etching process comprise: the etching gas used includes Cl 2 And SiCl 4 。
14. The method of claim 9, wherein the step of forming a heat sink within the heat dissipation hole comprises: a metal organic compound chemical vapor deposition process.
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