CN112908952A - Surrounding grid field effect transistor and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title abstract description 10
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 239000002070 nanowire Substances 0.000 claims abstract description 147
- 239000004065 semiconductor Substances 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 99
- 230000017525 heat dissipation Effects 0.000 claims abstract description 90
- 230000005669 field effect Effects 0.000 claims abstract description 84
- 239000000463 material Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 229910003460 diamond Inorganic materials 0.000 claims description 6
- 239000010432 diamond Substances 0.000 claims description 6
- 229910003910 SiCl4 Inorganic materials 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 claims description 3
- 150000002902 organometallic compounds Chemical class 0.000 claims description 2
- 229910017083 AlN Inorganic materials 0.000 claims 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims 1
- 230000002411 adverse Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 230000000630 rising effect Effects 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 24
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 16
- 239000010931 gold Substances 0.000 description 16
- 229910052737 gold Inorganic materials 0.000 description 16
- 239000010936 titanium Substances 0.000 description 16
- 229910052719 titanium Inorganic materials 0.000 description 16
- 229910002601 GaN Inorganic materials 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 238000002955 isolation Methods 0.000 description 12
- 229910052759 nickel Inorganic materials 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3731—Ceramic materials or glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a surrounding grid field effect transistor and a preparation method thereof, wherein the surrounding grid field effect transistor comprises: a semiconductor substrate; the nanowire is positioned on the semiconductor substrate, a heat dissipation hole is formed in the nanowire, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nanowire; the heat dissipation piece is positioned in the heat dissipation hole. The heat generated by the surrounding grid field effect transistor can be effectively dissipated through the heat dissipation piece, so that the adverse effects of the rising of the internal temperature of the channel, the source region and the drain region of the surrounding grid field effect transistor on the performance and the service life of the device are avoided, and the device can keep normal operation for a long time.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a surrounding grid field effect transistor and a preparation method thereof.
Background
The Field Effect Transistor changes the width of a channel by using an electric Field Effect generated by external voltage applied to a gate electrode and a source electrode, so as to control the size of current between a drain electrode and the source electrode, namely, an important factor determining the efficiency of the Field Effect Transistor is the control capability of the gate electrode to the channel.
However, the Gate-All-Around Vertical Nanowire Metal-Oxide Semiconductor Field Effect Transistor (GAA VNWMOSFET) has attracted great attention and is widely applied due to its excellent Gate controllability. The existing GAA VNWMOSFET has the outstanding characteristics that: the control capability of the grid electrode on the channel is excellent, so that faster driving current can be generated; the width of the channel is allowed to be further reduced, so that the integration level is higher, low driving voltage, low threshold voltage, high switching current ratio, high current density and high power density can be realized, and the method is suitable for low power consumption application.
However, the conventional surrounding gate field effect transistor has a narrow channel width, which results in a high current density in the channel and thus generates high heat; however, the channel does not dissipate heat effectively, which causes the temperature inside the channel to be high, thereby adversely affecting the performance and lifetime of the device.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defect that the performance and the lifetime of the device are affected due to the difficulty in effective heat dissipation of the conventional surrounding gate field effect transistor, thereby providing a surrounding gate field effect transistor and a manufacturing method thereof.
The invention provides a gate-wrap field effect transistor, comprising: a semiconductor substrate; the nano wire is positioned on the semiconductor substrate and is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nano wire; and the heat dissipation piece is positioned in the heat dissipation hole.
Optionally, the thermal conductivity of the heat sink is greater than or equal to 300W/(m × K).
Optionally, the heat sink is an insulating heat sink.
Optionally, the material of the heat sink comprises diamond or aluminum nitride ceramic.
Optionally, the ratio of the diameter of the heat dissipation hole to the diameter of the nanowire is 0.33-0.75.
Optionally, the diameter of the nanowire is 80nm to 180 nm; the diameter of the heat dissipation hole is 60nm-100 nm.
Optionally, the nanowire is in a ring structure; the heat dissipation hole penetrates through the nanowire along the extension direction of the nanowire.
Optionally, the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor, and the nanowire is perpendicular to the surface of the semiconductor substrate; or, the surrounding gate field effect transistor is a horizontal surrounding gate field effect transistor, and the nanowire is parallel to the surface of the semiconductor substrate.
Optionally, the semiconductor substrate includes a SiC-based semiconductor substrate, a GaN-based semiconductor substrate, or a silicon-based semiconductor substrate.
The invention also discloses a preparation method of the gate-surrounding field effect transistor, which comprises the following steps: providing a semiconductor substrate; forming a nanowire on the semiconductor substrate, wherein the nanowire is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nanowire; and forming a heat dissipation part in the heat dissipation hole.
Optionally, the preparation method of the nanowire comprises: forming an initial nanowire on the semiconductor substrate; etching the initial nanowire so that the initial nanowire forms the nanowire.
Optionally, before etching the initial nanowire, the method further includes: forming a barrier layer on the sidewalls and a portion of the top surface of the initial nanowire, the barrier layer having an opening therein that exposes a portion of the top surface of the initial nanowire; etching the initial nanowire by taking the barrier layer as a mask; and removing the barrier layer after etching the initial nanowire by taking the barrier layer as a mask.
Optionally, the process of etching the initial nanowire by using the barrier layer as a mask includes an anisotropic etching process.
Optionally, the parameters of the anisotropic etching process include: the etching gas used includes Cl2And SiCl4。
Optionally, the process for forming the heat dissipation member in the heat dissipation hole includes: a metal organic compound chemical vapor deposition process.
The technical scheme of the invention has the following advantages:
1. the gate-surrounding field effect transistor comprises a semiconductor substrate, a nanowire positioned on the semiconductor substrate and a radiating piece positioned in a radiating hole of the nanowire, wherein heat generated by the gate-surrounding field effect transistor can be effectively radiated through the radiating piece, so that adverse effects on the performance and the service life of a device caused by the increase of the internal temperature of a channel, a source region and a drain region of the gate-surrounding field effect transistor are avoided, and the device can keep normal operation for a long time. Secondly, most of the current generated when the surrounding gate field effect transistor is conducted is suitable for being transmitted in the area near the surface of the outer side wall of the nanowire, and the extending direction of the heat dissipation hole is parallel to the extending direction of the nanowire, so that the heat dissipation piece in the heat dissipation hole cannot obstruct the current transmission on the nanowire, and the normal work of the surrounding gate field effect transistor is ensured.
2. According to the field effect transistor with the surrounding grid electrode, the heat dissipation piece is an insulating heat dissipation piece. By arranging the heat dissipation member in the nanowire and limiting the heat dissipation member to be an insulating heat dissipation member, the region near the central axis of the nanowire cannot be subjected to current circulation, so that all current is concentrated in the region near the surface of the outer side wall of the nanowire, and the output current density is improved.
3. According to the surrounding gate field effect transistor, the ratio of the diameter of the heat dissipation hole to the diameter of the nanowire is limited to be 0.33-0.75, so that on one hand, the heat dissipation capability of a heat dissipation piece located in the heat dissipation hole is guaranteed, on the other hand, the surrounding gate field effect transistor has high output current density, and the performance of the surrounding gate field effect transistor is improved.
4. According to the preparation method of the gate-surrounding field effect transistor, the nanowire is formed on the semiconductor substrate, the nanowire is provided with the heat dissipation hole, and the heat dissipation part is formed in the heat dissipation hole, so that heat generated by the gate-surrounding field effect transistor can be effectively dissipated through the heat dissipation part, adverse effects on the performance and the service life of a device caused by the increase of the internal temperature of the channel, the source region and the drain region of the gate-surrounding field effect transistor are avoided, and the device can keep long-time normal operation. Secondly, most of the current generated when the surrounding gate field effect transistor is conducted is suitable for being transmitted in the area near the surface of the outer side wall of the nanowire, and the extending direction of the heat dissipation hole is parallel to the extending direction of the nanowire, so that the heat dissipation piece in the heat dissipation hole cannot obstruct the current transmission on the nanowire, and the normal work of the surrounding gate field effect transistor is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a surrounding gate field effect transistor according to embodiment 1 of the present invention;
fig. 2 is a process flow diagram of a method for fabricating a surrounding gate field effect transistor according to embodiment 2;
fig. 3-14 are schematic structural diagrams in the process of manufacturing the surrounding gate field effect transistor provided in embodiment 2;
fig. 15 is an output characteristic curve of the surrounding gate field effect transistors provided in example 1 and comparative example 1;
description of reference numerals:
1-a semiconductor substrate; 2-a nanowire; 21-a drain region; 22-a channel region; 23-a source region; 3-a heat sink; 4-a gate dielectric layer; 5-gate electrode layer; 6-an electrical isolation layer; 7-a source electrode layer; 8-a drain electrode layer; 9-initial nanowire.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "inside", "outside", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1
Referring to fig. 1, the present embodiment provides a gate-all-around field effect transistor, including: a semiconductor substrate 1; a nanowire 2 positioned on the semiconductor substrate 1, wherein the nanowire 2 is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nanowire 2; and the heat dissipation piece 3 is positioned in the heat dissipation hole.
The heat generated by the surrounding grid field effect transistor can be effectively dissipated through the heat dissipation part 3, so that the adverse effects of the rise of the internal temperature of the surrounding grid field effect transistor on the performance and the service life of the device are avoided, and the device can keep normal operation for a long time; meanwhile, the current generated when the surrounding grid field effect transistor is conducted is suitable for being transmitted along the nanowire 2, and the extending direction of the heat dissipation hole is parallel to the extending direction of the nanowire 2, so that the heat dissipation piece 3 in the heat dissipation hole cannot obstruct the current transmission on the nanowire 2, and the normal work of the surrounding grid field effect transistor is ensured.
In the present embodiment, the semiconductor substrate 1 includes, but is not limited to, a SiC-based semiconductor substrate, a GaN-based semiconductor substrate, or a silicon-based semiconductor substrate; specifically, the thickness of the semiconductor substrate 1 is 250 μm to 350 μm. Preferably, the semiconductor substrate 1 is a GaN-based semiconductor substrate.
Further, the semiconductor substrate 1 is an N-type semiconductor substrate. Specifically, when the semiconductor substrate 1 is a GaN-based semiconductor substrate, the dopant in the semiconductor substrate 1 includes, but is not limited to, silicon; when the semiconductor substrate 1 is a SiC-based semiconductor substrate or a silicon-based semiconductor substrate, the dopant species in the semiconductor substrate 1 includes, but is not limited to, phosphorus; further, the doping concentration of the doping substance in the semiconductor substrate 1 is 3 × 1018cm-3-8×1018cm-3。
In the present embodiment, the thermal conductivity of the heat sink 3 is greater than or equal to 300W/(m × K). Further, the heat sink is an insulating heat sink. When the field effect transistor is turned on, usually most of current flows through the region near the surface of the outer side wall of the nanowire 2, and a small part of current flows through the region near the central axis of the nanowire 2, and the heat dissipation member 3 is arranged in the nanowire 2, and the material of the heat dissipation member 3 is limited to be an insulating material, so that the region near the central axis of the nanowire 2 cannot flow current, all current is concentrated in the region near the surface of the outer side wall of the nanowire 2, and the output current density is improved. Specifically, the material of the heat sink 3 includes, but is not limited to, diamond or aluminum nitride ceramic. In one embodiment, the material of the heat spreader 3 is diamond.
In the embodiment, the ratio of the diameter of the heat dissipation hole to the diameter of the nanowire 2 is 0.33-0.75. By limiting the ratio of the diameter of the heat dissipation hole to the diameter of the nanowire 2, on one hand, the heat dissipation capability of the heat dissipation piece located in the heat dissipation hole is guaranteed, on the other hand, the heat dissipation piece has high output current density, and the performance of the field effect transistor surrounding the grid electrode is improved.
Specifically, the diameter of the nanowire 2 is 80nm-180 nm; the diameter of the heat dissipation hole is 60nm-100 nm. Illustratively, the nanowires 2 have a diameter of 80nm, 100nm, 120nm, 140nm, 160nm, 180 nm; the diameters of the heat dissipation holes are 60nm, 70nm, 80nm, 90nm and 100 nm. Preferably, the diameter of the nanowire 2 is 120nm, and the diameter of the heat dissipation hole is 80 nm.
In this embodiment, the material of the nanowire 2 is an N-type semiconductor material. Further, the material of the nanowire 2 includes but is not limited to gallium nitride, and the doped material includes but is not limited to silicon; preferably, when the semiconductor substrate 1 is a GaN-based semiconductor substrate, the nanowire 2 is made of gallium nitride, so that the semiconductor substrate is more compatible with the nanowire 2, and at this time, the doped material of the nanowire 2 is silicon.
Referring to fig. 1, in this embodiment, the nanowire 2 includes a channel region and a source region and a drain region respectively located at two sides of the channel region, and the drain region, the channel region and the source region are arranged along an extending direction of the nanowire 2. Further, theThe doping concentration of the channel region 22 is less than that of the drain region 21, and the doping concentration of the channel region 22 is less than that of the source region 23; in one embodiment, the doping concentration of the drain region 21 is equal to the doping concentration of the source region 23. Specifically, the doping concentration of the drain region 21 is 1 × 1018cm-3-4x1018cm-3The doping concentration of the channel region 22 is 1x1015cm-3-8x1015cm-3The doping concentration of the source region 23 is 1x1018cm-3-4x1018cm-3. Preferably, the doping concentration of the drain region 21 is 2 × 1018cm-3The doping concentration of the channel region 22 is 5x1015cm-3The doping concentration of the source region 23 is 2x1018cm-3。
Further, along the extension direction of the nanowire 2, the size of the channel region 22 is larger than that of the drain region 21, and the size of the channel region 22 is equal to that of the source region 23; in an embodiment, the size of the drain region 21 is equal to the size of the source region 23 along the extension direction of the nanowire. Specifically, along the extension direction of the nanowire, the size of the drain region 21 is 0.2 μm to 0.5 μm, the size of the channel region 22 is 0.3 μm to 0.6 μm, and the size of the source region 23 is 0.2 μm to 0.5 μm. Preferably, along the extension direction of the nanowire, the size of the drain region 21 is 0.3 μm, the size of the channel region 22 is 0.4 μm, and the size of the source region 23 is 0.3 μm.
In the present embodiment, the nanowire 2 has a ring structure; the radiating holes penetrate through the nanowires 2 along the extending direction of the nanowires 2, both ends of the radiating piece 3 can be used for radiating, and heat in the nanowires 2 is transmitted out through the radiating piece 3, so that the radiating speed of the surrounding grid field effect transistor is improved.
Further, in one embodiment, referring to fig. 1, the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor, and the nanowire 2 is perpendicular to the surface of the semiconductor substrate 1. In this case, the bottom surface of the nanowire 2 is in contact with the surface of the semiconductor substrate 1. When the heat dissipation hole penetrates through the nanowire 2 along the extending direction of the nanowire 2, the heat dissipation member 3 is also in contact with the surface of the semiconductor substrate 1, so that one end of the heat dissipation member 3 can transmit heat to the semiconductor substrate 1 and the heat is transmitted out from the semiconductor substrate 1, and the other end of the heat dissipation member 3 can transmit the heat to the outside, thereby improving the heat dissipation speed of the surrounding gate field effect transistor.
In another embodiment, the surrounding gate field effect transistor is a horizontal surrounding gate field effect transistor, and the nanowire 2 is parallel to the surface of the semiconductor substrate 1. The heat generated at different positions in the nanowire 2 can be transmitted to the heat dissipation member 3 at a higher speed, and the heat is transmitted out by the heat dissipation member 3, so that the heat dissipation speed of the surrounding gate field effect transistor is improved.
Referring to fig. 1, in the present embodiment, the surrounding gate field effect transistor further includes: and the gate structure is positioned on the semiconductor substrate 1 and surrounds the channel region 22. The gate structure includes: a gate dielectric layer 4 surrounding the channel region; and the gate electrode layer 5 surrounds the channel region 22 and is positioned outside the gate dielectric layer 4. Specifically, the material of the gate dielectric layer 4 includes, but is not limited to, Al2O3Or SiO2The material of the gate electrode layer 5 includes, but is not limited to, chromium. In this embodiment, when the surrounding gate fet is a vertical surrounding gate fet, the gate dielectric layer 4 surrounds the channel region 22 and extends to the surface of the semiconductor substrate 1, so that the gate dielectric layer 4 is "L" shaped.
Referring to fig. 1, in the present embodiment, the surrounding gate field effect transistor further includes: and the source electrode layer 7 and the drain electrode layer 8 are positioned at two sides of the gate structure, the source electrode layer 7 is electrically connected with the source region 23, and the drain electrode layer 8 is electrically connected with the drain region 21.
Specifically, when the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor, the source electrode layer 7 is located on the side of the gate structure away from the semiconductor substrate 1, and the drain electrode layer 8 is located on the side of the semiconductor substrate 1 away from the gate structure; further, an electrical isolation layer 6 is disposed between the gate structure and the source electrode layer 7.
Further, the material of the electrical isolation layer 6 includes, but is not limited to, silicon dioxide; the source electrode layer 7 comprises a first titanium layer, a first aluminum layer, a first nickel layer and a first gold layer which are sequentially stacked, the first titanium layer is in contact with the electric isolation layer 6, the arrangement direction of the first titanium layer, the first aluminum layer, the first nickel layer and the first gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the first titanium layer is 20nm-30nm, the thickness of the first aluminum layer is 70nm-80nm, the thickness of the first nickel layer is 0nm-30nm, and the thickness of the first gold layer is 70nm-80 nm; or, the material of the source electrode layer 7 is gold, and the thickness of the source electrode layer 7 is 150nm-250 nm; by defining the source electrode layer 7 as the above material, a good ohmic contact between the source electrode layer 7 and the source region is ensured, and it is understood that the material of the source electrode layer 7 includes, but is not limited to, the above materials; the drain electrode layer 8 comprises a second titanium layer, a second aluminum layer, a second nickel layer and a second gold layer which are sequentially stacked, the second titanium layer is in contact with the semiconductor substrate 1, the arrangement direction of the second titanium layer, the second aluminum layer, the second nickel layer and the second gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the second titanium layer is 20nm-30nm, the thickness of the second aluminum layer is 70nm-80nm, the thickness of the second nickel layer is 0nm-30nm, and the thickness of the second gold layer is 70nm-80 nm; or the drain electrode layer 8 is made of gold, and the thickness of the drain electrode layer 8 is 150nm-250 nm; by defining the drain electrode layer 8 as a material as described above, a good ohmic contact between the drain electrode layer 8 and the drain region is ensured, and it is to be understood that the material of the drain electrode layer 8 includes, but is not limited to, the above materials.
Example 2
Referring to fig. 2, the present embodiment provides a method for manufacturing a gate-all-around field effect transistor, including the following steps:
s1, providing a semiconductor substrate 1;
s2, forming a nanowire 2 on the semiconductor substrate 1, wherein the nanowire 2 is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nanowire 2;
and S3, forming the heat sink 3 in the heat dissipation hole.
According to the preparation method of the gate-surrounding field effect transistor, the nanowire 2 is formed on the semiconductor substrate 1, the nanowire 2 is provided with the heat dissipation hole, and the heat dissipation part 3 is formed in the heat dissipation hole, so that heat generated by the gate-surrounding field effect transistor can be effectively dissipated through the heat dissipation part, adverse effects on the performance and the service life of a device caused by the increase of the internal temperature of the channel, the source region and the drain region of the gate-surrounding field effect transistor are avoided, and the device can keep long-time normal work. Secondly, most of the current generated when the surrounding gate field effect transistor is conducted is suitable for being transmitted in the area near the surface of the outer side wall of the nanowire, and the extending direction of the heat dissipation hole is parallel to the extending direction of the nanowire, so that the heat dissipation piece in the heat dissipation hole cannot obstruct the current transmission on the nanowire, and the normal work of the surrounding gate field effect transistor is ensured.
The technical solution of the present invention will be clearly and completely described with reference to fig. 3-14.
Referring to fig. 3, in step S1, a semiconductor substrate 1 is provided.
Specifically, the semiconductor substrate 1 includes, but is not limited to, a SiC-based semiconductor substrate, a GaN-based semiconductor substrate, or a silicon-based semiconductor substrate; specifically, the thickness of the semiconductor substrate 1 is 250 μm to 350 μm. Preferably, the semiconductor substrate 1 is a GaN-based semiconductor substrate.
Further, the semiconductor substrate 1 is an N-type semiconductor substrate. Specifically, when the semiconductor substrate 1 is a GaN-based semiconductor substrate, the dopant in the semiconductor substrate 1 includes, but is not limited to, silicon; when the semiconductor substrate 1 is a SiC-based semiconductor substrate or a silicon-based semiconductor substrate, the dopant species in the semiconductor substrate 1 includes, but is not limited to, phosphorus; further, the doping concentration of the doping substance in the semiconductor substrate 1 is 3 × 1018cm-3-8×1018cm-3。
Referring to fig. 4-8, in step S2, a nanowire 2 is formed on the semiconductor substrate 1, and the nanowire 2 has a thermal via therein, and the extending direction of the thermal via is parallel to the extending direction of the nanowire 2.
Specifically, the preparation method of the nanowire 2 comprises the following steps: forming an initial nanowire 9 on the semiconductor substrate 1; the initial nanowire 9 is etched such that the initial nanowire forms the nanowire 2.
Wherein the step of forming the initial nanowire 9 comprises: referring to fig. 4, a first semiconductor film is formed on the surface of the semiconductor substrate 1; referring to fig. 5, a second semiconductor film is formed on a surface of the first semiconductor film; referring to fig. 6, a third semiconductor film is formed on a surface of the second semiconductor film; referring to fig. 7, a third semiconductor film, a second semiconductor film and the first semiconductor film are patterned to form a cylindrical initial nanowire 9, the initial nanowire 9 includes a channel region 22 and a source region 23 and a drain region 21 respectively located at two sides of the channel region, the drain region 21, the channel region 22 and the source region 23 are arranged along the extending direction of the nanowire 2, the drain region 21 is formed by the patterned first semiconductor film, the channel region 22 is formed by the patterned second semiconductor film, and the source region 23 is formed by the patterned third semiconductor film.
Further, the method for forming the first semiconductor film, the second semiconductor film and the third semiconductor film on the surface of the semiconductor substrate 1 is a Metal Organic Chemical Vapor Deposition (MOCVD) process; obtaining an initial nanowire 9 by sequentially performing dry etching and wet etching on the third semiconductor film, the second semiconductor film and the first semiconductor film 3, wherein a gas used for the dry etching includes Cl2And SiCl4The solution used for wet etching includes a tetramethylammonium hydroxide (TMAH) solution.
In this embodiment, the material of the nanowire 2 is an N-type semiconductor material. Further, the material of the nanowire 2 includes but is not limited to gallium nitride, and the doped material includes but is not limited to silicon; preferably, when the semiconductor substrate 1 is a GaN-based semiconductor substrate, the nanowire 2 is made of gallium nitride, so that the semiconductor substrate is more compatible with the nanowire 2, and at this time, the doped material of the nanowire 2 is silicon.
Further, the doping concentration of the channel region 22 is less than that of the drain region 21, and the doping concentration of the channel region 22 is less than that of the source region 23; in one embodiment, the doping concentration of the drain region 21 is equal to the doping concentration of the source region 23. Specifically, the doping concentration of the drain region 21 is 1 × 1018cm-3-4x1018cm-3The doping concentration of the channel region 22 is 1x1015cm-3-8x1015cm-3The doping concentration of the source region 23 is 1x1018cm-3-4x1018cm-3. Preferably, the doping concentration of the drain region 21 is 2 × 1018cm-3The doping concentration of the channel region 22 is 5x1015cm-3The doping concentration of the source region 23 is 2x1018cm-3。
Further, along the extension direction of the nanowire 2, the size of the channel region 22 is larger than that of the drain region 21, and the size of the channel region 22 is equal to that of the source region 23; in an embodiment, the size of the drain region 21 is equal to the size of the source region 23 along the extension direction of the nanowire. Specifically, along the extension direction of the nanowire, the size of the drain region 21 is 0.2 μm to 0.5 μm, the size of the channel region 22 is 0.3 μm to 0.6 μm, and the size of the source region 23 is 0.2 μm to 0.5 μm. Preferably, along the extension direction of the nanowire, the size of the drain region 21 is 0.3 μm, the size of the channel region 22 is 0.4 μm, and the size of the source region 23 is 0.3 μm.
Further, the diameter of the nanowire 2 is 80nm-180 nm; illustratively, the nanowires 2 have a diameter of 80nm, 100nm, 120nm, 140nm, 160nm, 180 nm; preferably, the diameter of the nanowire 2 is 120 nm.
Referring to fig. 8, in step S2, the step of etching the initial nanowire 9 includes: forming a barrier layer on the sidewalls and a portion of the top surface of the initial nanowire 9, the barrier layer having an opening therein that exposes a portion of the top surface of the initial nanowire 9; etching the initial nanowire 9 by using the barrier layer as a mask; and removing the barrier layer after etching the initial nanowire by taking the barrier layer as a mask.
Specifically, the process for etching the initial nanowire by using the barrier layer as a mask comprises an anisotropic etching process, wherein the anisotropic etching process comprises dry etching, and the adopted etching gas comprises Cl2And SiCl4(ii) a The material of the barrier layer includes but is not limited to phenolic resin; the diameter of the heat dissipation hole is 60nm-100 nm. Illustratively, the diameter of the thermal via is 60nm, 70nm, 80nm, 90nm, 100 nm; preferably, the diameter of the thermal via is 80 nm.
In the present embodiment, the nanowire 2 has a ring structure; the heat dissipation hole penetrates the nanowire 2 along the extension direction of the nanowire 2.
Referring to fig. 9, in step S3, the heat sink 3 is formed within the heat dissipation hole.
Specifically, the material of the heat sink 3 includes, but is not limited to, diamond or aluminum nitride ceramic. The process for forming the heat sink 3 in the heat dissipation hole includes: metal Organic Chemical Vapor Deposition (MOCVD) processes.
Referring to fig. 10 to 14, in the present embodiment, the method for manufacturing the gate-around field effect transistor further includes the following steps: forming a gate structure on the semiconductor substrate 1, wherein the gate structure surrounds the channel region; and forming a source electrode layer 7 and a drain electrode layer 8 on two sides of the gate structure, wherein the source electrode layer 7 is electrically connected with the source region 23, and the drain electrode layer 8 is electrically connected with the drain region 21.
The preparation of the grid structure comprises the following steps: forming a gate dielectric layer 4 surrounding the channel region; and forming a gate electrode layer 5 which surrounds the channel region 22 and is positioned outside the gate dielectric layer 4. Specifically, the material of the gate dielectric layer 4 includes, but is not limited to, Al2O3Or SiO2The material of the gate electrode layer 5 includes, but is not limited to, chromium. In one embodiment, the gate dielectric layer 4 completely covers the outer surface of the channel region 22 and exposes the source region 23. In this embodiment, when the surrounding gate fet is a vertical surrounding gate fet, the gate dielectric layer 4 surrounds the channel region 22 and extends to the surface of the semiconductor substrate 1, so that the gate dielectric layer 4 is "L" shaped.
Specifically, when the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor, the source electrode layer 7 is formed on the side of the gate structure away from the semiconductor substrate 1, and the drain electrode layer 8 is formed on the side of the semiconductor substrate 1 away from the gate structure; further, before forming the source electrode layer 7, forming an electrical isolation layer 6 on a side of the gate structure facing away from the semiconductor substrate 1, wherein after forming the source electrode layer 7, the electrical isolation layer 6 is located between the gate structure and the source electrode layer 7.
It is to be understood that, as shown in fig. 10-14, after the nanowire 2 is formed, the gate dielectric layer 4 is formed, the drain electrode layer 8 is formed, and then the gate electrode layer 5, the electrical isolation layer 6 and the source electrode layer 7 are sequentially formed; after the nanowire 2 is formed, the gate dielectric layer 4, the gate electrode layer 5, the electrical isolation layer 6 and the source electrode layer 7 may be sequentially formed, and then the drain electrode layer 8 may be formed. The formation sequence of the gate dielectric layer 4, the gate electrode layer 5, the drain electrode layer 8, the electrical isolation layer 6 and the source electrode layer 7 can be adjusted as required.
Specifically, the material of the electrical isolation layer 6 includes, but is not limited to, silicon dioxide; the source electrode layer 7 comprises a first titanium layer, a first aluminum layer, a first nickel layer and a first gold layer which are sequentially stacked, the first titanium layer is in contact with the electric isolation layer 6, the arrangement direction of the first titanium layer, the first aluminum layer, the first nickel layer and the first gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the first titanium layer is 20nm-30nm, the thickness of the first aluminum layer is 70nm-80nm, the thickness of the first nickel layer is 0nm-30nm, and the thickness of the first gold layer is 70nm-80 nm; or, the material of the source electrode layer 7 is gold, and the thickness of the source electrode layer 7 is 150nm-250 nm; by defining the source electrode layer 7 as the above material, a good ohmic contact between the source electrode layer 7 and the source region is ensured, and it is understood that the material of the source electrode layer 7 includes, but is not limited to, the above materials; the drain electrode layer 8 comprises a second titanium layer, a second aluminum layer, a second nickel layer and a second gold layer which are sequentially stacked, the second titanium layer is in contact with the semiconductor substrate 1, the arrangement direction of the second titanium layer, the second aluminum layer, the second nickel layer and the second gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the second titanium layer is 20nm-30nm, the thickness of the second aluminum layer is 70nm-80nm, the thickness of the second nickel layer is 0nm-30nm, and the thickness of the second gold layer is 70nm-80 nm; or the drain electrode layer 8 is made of gold, and the thickness of the drain electrode layer 8 is 150nm-250 nm; by defining the drain electrode layer 8 as a material as described above, a good ohmic contact between the drain electrode layer 8 and the drain region is ensured, and it is to be understood that the material of the drain electrode layer 8 includes, but is not limited to, the above materials. .
In the present embodiment, the gate dielectric layer 4 is formed by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atomic Layer Deposition (ALD) method; forming a metal film by thermal evaporation, magnetron sputtering or electron beam evaporation, and depositing the metal film on the N2Annealing at 600-700 ℃ under the environment to obtain the gate electrode layer 5; forming the electrical isolation layer 6 using a Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atomic Layer Deposition (ALD) method; forming a metal film by thermal evaporation, magnetron sputtering or electron beam evaporation, and depositing the metal film on the N2Annealing is carried out at 600-700 ℃ under the environment to obtain the drain electrode layer 8.
Comparative example 1
This comparative example provides a surrounding gate field effect transistor which differs from the surrounding gate field effect transistor provided in example 1 in that: the nanowires do not have thermal holes.
Test examples
The surrounding gate field effect transistor provided in example 1 and the surrounding gate field effect transistor provided in comparative example 1 were subjected to simulation softwareSimulation was performed, in which the voltage of the gate electrode layer was 2V, and the material surrounding the heat sink in the gate field effect transistor provided in example 1 was diamond. The results are shown in FIG. 15. In the figure, the horizontal axis represents the drain voltage, the unit of which is V; the vertical axis represents the drain-source output current density, which has a unit of MA/cm2. As can be seen from fig. 15, the output characteristic curve of the surrounding gate field effect transistor provided in comparative example 1 starts to decrease after a voltage of 2V (i.e., point a) as the drain voltage increases, because the device performance deteriorates due to the temperature rise in the surrounding gate field effect transistor; as the drain voltage increases, the output characteristic curve of the gate-around fet provided in embodiment 1 does not decrease in the drain-source output current density after the voltage of 2V (i.e., point a), but remains in a steady state, because the heat in the gate-around fet is transferred away by the heat sink and the internal temperature of the gate-around fet is within a normal range, the device can operate normally. In addition, it is to be noted that the drain-source output current density of the surrounding gate field effect transistor provided in embodiment 1 gradually increases.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A wrap gate field effect transistor, comprising:
a semiconductor substrate;
the nano wire is positioned on the semiconductor substrate and is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nano wire;
and the heat dissipation piece is positioned in the heat dissipation hole.
2. A surrounding gate field effect transistor according to claim 1, wherein the thermal conductivity of the heat sink is greater than or equal to 300W/(m x K).
3. The surround gate field effect transistor of claim 1, wherein the heat sink is an insulating heat sink.
4. A surrounding gate field effect transistor according to any of claims 1 to 3, wherein the material of the heat spreader comprises diamond or aluminium nitride ceramic.
5. The gate-around field effect transistor of claim 1, wherein the ratio of the diameter of the thermal via to the diameter of the nanowire is 0.33-0.75;
preferably, the diameter of the nanowire is 80nm-180 nm; the diameter of the heat dissipation hole is 60nm-100 nm.
6. The wrap gate field effect transistor of claim 1, wherein the nanowire is in a ring structure; the heat dissipation hole penetrates through the nanowire along the extension direction of the nanowire.
7. The surround-gate field effect transistor of claim 1, wherein the surround-gate field effect transistor is a vertical surround-gate field effect transistor, the nanowire being perpendicular to a surface of the semiconductor substrate;
or, the surrounding gate field effect transistor is a horizontal surrounding gate field effect transistor, and the nanowire is parallel to the surface of the semiconductor substrate.
8. The wrap gate field effect transistor of claim 1, wherein the semiconductor substrate comprises a SiC-based semiconductor substrate, a GaN-based semiconductor substrate, or a silicon-based semiconductor substrate.
9. A method of fabricating a surrounding gate field effect transistor as claimed in any one of claims 1 to 8, comprising the steps of:
providing a semiconductor substrate;
forming a nanowire on the semiconductor substrate, wherein the nanowire is provided with a heat dissipation hole, and the extension direction of the heat dissipation hole is parallel to the extension direction of the nanowire;
and forming a heat dissipation part in the heat dissipation hole.
10. The method of fabricating a surrounding gate field effect transistor according to claim 9, wherein the method of fabricating the nanowire comprises: forming an initial nanowire on the semiconductor substrate; etching the initial nanowire to form the nanowire;
preferably, before etching the initial nanowire, the method further comprises: forming a barrier layer on the sidewalls and a portion of the top surface of the initial nanowire, the barrier layer having an opening therein that exposes a portion of the top surface of the initial nanowire; etching the initial nanowire by taking the barrier layer as a mask; removing the barrier layer after etching the initial nanowire by taking the barrier layer as a mask;
preferably, the process for etching the initial nanowire by using the barrier layer as a mask comprises an anisotropic etching process; preferably, the parameters of the anisotropic etching process include: the etching gas used includes Cl2And SiCl4；
Preferably, the process of forming a heat sink within the heat dissipation hole includes: a metal organic compound chemical vapor deposition process.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060255452A1 (en) * | 2005-05-10 | 2006-11-16 | Shih-Yuan Wang | Cooling devices that use nanowires |
| CN101399207A (en) * | 2007-09-24 | 2009-04-01 | 国际商业机器公司 | Manufacturing method for vertical nano-wire fet device and fet device manufactured thereby |
| US20110169012A1 (en) * | 2007-10-04 | 2011-07-14 | Hersee Stephen D | NANOWIRE AND LARGER GaN BASED HEMTS |
| US20120223288A1 (en) * | 2011-03-04 | 2012-09-06 | Samsung Electronics Co., Ltd. | Semiconductor device, method of manufacturing the same, and electronic device including the semiconductor device |
| CN104157686A (en) * | 2014-08-11 | 2014-11-19 | 北京大学 | Surrounding-gate field effect transistor and fabrication method thereof |
| CN104201205A (en) * | 2014-08-27 | 2014-12-10 | 北京大学 | Core-shell field effect transistor and preparation method thereof |
-
2021
- 2021-01-21 CN CN202110086420.6A patent/CN112908952B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060255452A1 (en) * | 2005-05-10 | 2006-11-16 | Shih-Yuan Wang | Cooling devices that use nanowires |
| CN101399207A (en) * | 2007-09-24 | 2009-04-01 | 国际商业机器公司 | Manufacturing method for vertical nano-wire fet device and fet device manufactured thereby |
| US20110169012A1 (en) * | 2007-10-04 | 2011-07-14 | Hersee Stephen D | NANOWIRE AND LARGER GaN BASED HEMTS |
| US20120223288A1 (en) * | 2011-03-04 | 2012-09-06 | Samsung Electronics Co., Ltd. | Semiconductor device, method of manufacturing the same, and electronic device including the semiconductor device |
| CN104157686A (en) * | 2014-08-11 | 2014-11-19 | 北京大学 | Surrounding-gate field effect transistor and fabrication method thereof |
| CN104201205A (en) * | 2014-08-27 | 2014-12-10 | 北京大学 | Core-shell field effect transistor and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420657A (en) * | 2022-03-30 | 2022-04-29 | 深圳市时代速信科技有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| CN114420657B (en) * | 2022-03-30 | 2022-06-24 | 深圳市时代速信科技有限公司 | Semiconductor device and method for manufacturing semiconductor device |
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