CN112886701A - Power-down data storage power management circuit - Google Patents
Power-down data storage power management circuit Download PDFInfo
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- CN112886701A CN112886701A CN202110144240.9A CN202110144240A CN112886701A CN 112886701 A CN112886701 A CN 112886701A CN 202110144240 A CN202110144240 A CN 202110144240A CN 112886701 A CN112886701 A CN 112886701A
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- 238000007726 management method Methods 0.000 title abstract description 19
- 238000013500 data storage Methods 0.000 title abstract description 15
- 239000003990 capacitor Substances 0.000 claims abstract description 62
- 208000037408 Device failure Diseases 0.000 abstract description 3
- 230000009977 dual effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000010485 coping Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
- H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
- H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
- H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads
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- Business, Economics & Management (AREA)
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Stand-By Power Supply Arrangements (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The invention relates to a power-down storage power management circuit which comprises a first double diode, a second double diode, a third double diode, a triode, a second resistor, a third resistor, a fourth resistor, a second capacitor, a super capacitor, a battery and a memory. The triode is not conducted when in normal work and is conducted when in power failure, so that the super capacitor provides power for the memory. The power-down data storage power supply management circuit can enable the intelligent meter to have enough power supply for data storage operation after detecting a power-down signal according to the difference of voltages of all parts during power-down, provides power supply support for power-down data storage, and simultaneously reduces the risk of device failure to the maximum extent.
Description
Technical Field
The invention relates to the field of power supplies, in particular to a power-down data storage power supply management circuit.
Background
With the development of the power industry, the intelligent electric energy meter is rapidly replacing the traditional mechanical and electronic electric energy meters, the functions of the intelligent electric energy meter are more and more, the data to be stored are increased successively, the data related to the electric energy are required to be stored when the electric energy meter is powered down, but the storage time is prolonged due to the increase of the data, and the normal storage time can be ensured only by ensuring sufficient power supply time in the power down process.
At present smart meter of using, what the storage is mainly the relevant data of ammeter electric quantity, according to the development of present electric energy meter, the electric energy meter is more to loss, load on the power line, steal the electricity etc. and record, and the data volume is more and more, if the deposit number is incomplete, probably leads to the electric quantity to lose, electric quantity data mismatch, the record loses the scheduling problem, can cause the loss for the power company. Therefore, a power-down storage power management circuit is necessary in the practical application of the intelligent electric energy meter. The conventional power-down stored data power management circuit has short voltage time for supporting stored data after power failure, is used under the condition of small stored data volume of an electric energy meter of an old product, has more stored data volume according to the development condition of the electric energy meter, cannot support the storage work of all data volume by the original power management circuit, and needs a power-down stored data power management circuit for coping with the development of an intelligent meter.
Disclosure of Invention
Objects of the invention
The invention aims to provide a power-fail data storage power supply management circuit which is applied to an intelligent electric energy meter, can provide power supply support during power failure and has enough power supply for data storage operation.
(II) technical scheme
One aspect of the invention protects a power-down storage power management circuit, which comprises a first double diode, a second double diode, a third double diode, a triode, a second resistor, a third resistor, a fourth resistor, a second capacitor, a super capacitor, a battery and a memory; the collector electrode of the triode is connected with the super capacitor through a second resistor and a second double diode, the emitter electrode of the triode is connected with a system working power supply and the power supply end of the memory, and the base electrode of the triode is grounded through a fourth resistor and a fourth capacitor which are connected in series; the third double diode is connected between the battery and the control power supply through a third resistor, and a connecting point of a fourth resistor and a fourth capacitor is connected with the third double diode; the first double diode is connected among the system working power supply, the control power supply and the system rectification power supply, so that the voltages of the system working power supply and the control power supply are the same; the third double diode is connected with the power supply output end of the battery, and the second double diode is connected with the power supply output end of the super capacitor.
According to one aspect of the invention, the two diodes of the first double diode are connected in parallel to form three end portions, the connection point of the anodes of the two diodes is the third end portion, and the cathodes of the two diodes are the first end portion and the second end portion respectively.
According to one aspect of the invention, the first end of the first double diode is connected to a system operating power supply, the second end is connected to a control power supply, and the third end is connected to a system rectifying power supply.
According to one aspect of the invention, the two diodes of the second double diode are connected in series to form three terminals, the junction of the cathode of one diode and the anode of the other diode being the second terminal, the anode of one diode being the first terminal, and the cathode of the other diode being the third terminal.
According to one aspect of the invention, the power-down storage power management circuit further comprises a first resistor and a first capacitor, a first end of the second double diode is connected to a system rectification power supply through the first resistor, a third end of the second double diode is a super capacitor power output end, a second end of the second double diode is connected to an anode of a super capacitor, a cathode of the super capacitor is grounded, and the first capacitor is connected between the system rectification power supply and the ground.
According to one aspect of the invention, the two diodes of the third double diode are connected in parallel to form three end portions, the cathodes of the two diodes are connected to form the third end portion, and the anodes of the two diodes are the first end portion and the second end portion respectively.
According to one aspect of the invention, the third end point of the third double diode is connected with a connection point of the fourth resistor and the fourth capacitor, the first end point is connected with the power supply output end of the battery, the anode of the battery is connected through the third resistor, the cathode of the battery is grounded, and the second end point of the third double diode is connected with the control power supply.
According to one aspect of the invention, a diode is connected between the battery power supply output end and the super capacitor power supply output end, the battery power supply output end is connected with the anode of the diode, and the super capacitor power supply output end is connected with the cathode of the diode.
According to one aspect of the invention, the memory is a chip and the power supply terminal is a pin.
(III) advantageous effects
The invention provides a power-down data storage power supply management circuit for an intelligent electric energy meter, which can enable the intelligent meter to have enough power supply for data storage operation after detecting a power-down signal according to the difference of voltages of all parts during power-down, and has the following beneficial technical effects:
1. the power supply support is provided for the power-down storage number, and the support time is long.
2. The response speed is high, the power supply switching is not delayed, the continuous power supply can be ensured, and the storage operation is supported.
3. The condition that all parts of the device fail completely or partially is fully considered, and the risk of failure in storage caused by device failure is reduced to the maximum extent.
Drawings
FIG. 1 is a schematic diagram of a power down storage power management circuit according to one embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
Fig. 1 shows a schematic diagram of a power down storage power management circuit. In fig. 1, VDD is a rectified power source of the system and is generated by an external input power source, VCC is a system operating power source, VCM is a control power source, VCAP is a super capacitor power output, and VBATT is a battery power output. The power-down storage power management circuit comprises double diodes Q1, Q2, Q3, a triode Q4, resistors R1, R2, R3 and R4, capacitors C1 and C4, a super capacitor CD1, a battery B1 and a diode D1.
The double diode Q1 has three ends, 11, 12 and 13 respectively, two diodes of the double diode Q1 are connected in parallel, the anodes of the two diodes are connected to form the end 13, the cathode of one diode is the end 11, and the cathode of the other diode is the end 12. The double diode Q1 is one-way in and two-way out, and the direction is irreversible.
The double diode Q2 has three terminals 21, 22 and 23, respectively, and the two diodes of the double diode Q1 are connected in series, i.e. the cathode of one diode is connected to the anode of the other diode, the connection point of the two diodes is terminal 22, the anode of one diode is terminal 21, and the cathode of the other diode is terminal 23. The dual diode Q2 includes two modes of operation. First, when the left pin is powered, both the bottom and right pins can output. Second, when the left pin is not powered, the lower pin can supply power to the right pin, and the lower pin is a channel for charging and discharging the super capacitor CD 1.
The double diode Q3 has three terminals 31, 32 and 33 respectively, two diodes of the double diode Q3 are connected in parallel, the cathodes of the two diodes are connected to form terminal 33, the anode of one diode is terminal 31 and the anode of the other diode is terminal 32. The double diode Q3 double-in and single-out compares the voltage of VBATT and VCM, and takes high voltage as input.
Transistor Q4 includes a collector C, a base B, and an emitter E. Transistor Q4 is non-conductive when powered up and conductive when powered down.
Super capacitor CD1 is charged by VDD when powered up; when power is lost, transistor Q4 is driven to operate to provide power to memory U2.
Memory U2 is a chip with 8 pins, powered by VCC, for data storage.
As can be seen from fig. 1, the double diode Q1 has terminal 1 connected to VCC, terminal 2 connected to VCM, and terminal 3 connected to VDD. When both diodes of the dual diode Q1 conduct, the voltage of VCC and VCM is the same. A diode D1 is connected between VBATT and VCAP, VBATT is connected with the anode of a diode D1, and VCAP is connected with the cathode of a diode D1. An end 21 of the double diode Q2 is connected with VDD through a resistor R1, an end 23 is connected with VCAP, an end 22 is connected with the anode of a super capacitor CD1, the cathode of the super capacitor CD1 is grounded GND, and a capacitor C1 is connected between VDD and GND. The collector C of the transistor Q4 is connected to the terminal 23 of the dual diode Q2 through a resistor R2. Emitter E of transistor Q4 is connected to VCC. The base B of the transistor Q4 is connected to the ground GND through a resistor R4 and a capacitor C4 which are connected in series. The base B of the triode Q4 is connected with one end of the resistor R4, the other end of the resistor R4 is connected with one end of the capacitor C4 in series, and the other end of the capacitor C4 is grounded GND. A terminal 33 of the double diode Q3 is connected to a connection point of the resistor R4 and the capacitor C4, a terminal 31 of the double diode Q3 is connected to VBATT, the positive electrode of the battery B1 is connected through the resistor R3, the negative electrode of the battery B1 is grounded to GND, and a terminal 32 of the double diode Q3 is connected to VCM. Pin 4 of memory U2 is connected to ground GND, and pin 8 is connected to emitter E of transistor Q4.
The working process of the power-down data storage power management circuit is as follows:
when the power is on, two diodes of the double diode Q1 are conducted, and due to the action of the double diode Q1, the voltage of the VCM is the same as that of the VCC, so that the triode Q4 is in a non-conduction state, and therefore, the system working power supply VCC supplies power to the memory U2. VDD charges the super capacitor CD1 through resistor R1 and a double diode Q2, and VCM charges the capacitor C4 through a double diode Q3.
When power is lost, the voltage of VDD becomes zero, and the voltages of VCC and VCM also become zero. Under the action of a power supply B1, a double diode Q3 is conducted, VBATT drives a base B of a triode Q4 through a double diode Q3 and a resistor R4, so that a collector C and an emitter E of a triode Q4 are conducted, VCAP supplies power to a VCC end of a memory U2 through a resistor R2, and the use of the memory is supported.
In consideration of the influence of the service life of the super capacitor, when the super capacitor CD1 fails, VBATT can also provide power for VCAP through the diode D1, so as to support the use of power down, and the diode D1 can also prevent the super capacitor CD1 from reversely charging the battery B1.
In consideration of the battery life and passivation effects, capacitor C4 may also drive transistor Q4 to allow VCAP to supply VCC when battery B1 fails.
The intelligent electric energy meter requires the battery to be replaceable, so the main function of the super capacitor is to support the replacement of the battery when the battery is not charged, and the consumption is relatively small due to the fact that the super capacitor is used for supporting the storage number, and therefore the selection of the super capacitor mainly takes the time requirement for replacing the battery as reference. The resistors R1, R2, R3 and R4, the capacitors C1 and C4 and the triode Q4 are subjected to calculation and post-selection according to different requirements. The storage U2 is selected according to the total data content required to be stored by the electric energy meter. For example, in a specific embodiment, the electric energy meter system is powered by a 5V power supply, that is, the system power supply VDD is 5V, the voltage of VCC and VCM is 4.7V, and the parameters of the various elements of the other circuits are set as: 51 omega is used as the resistor R1, 10 omega is used as the resistors R2 and R3, 10k omega is used as the resistor R4, 10 muF is used as the capacitor C1, 47 muF is used as the capacitor C4, 1.5F is used as the super capacitor, the voltage of the battery B1 is 3.6V, BAT54A is used as the double diode Q1, BAT54S is used as the double diode Q2, BAT54C is used as the double diode Q3, and LMBT2222ALT1G is used as the triode Q4.
According to the important point data such as forward and reverse reactive total electric quantity and each time-sharing electric quantity stored in the power failure, the software processing time is evaluated, the electric level needs to be maintained for more than 70ms, and the requirement is easily met under the normal working condition.
When the power grid is in a low-voltage condition, after a power failure signal is detected, the time for maintaining the level can be shortened, data is easy to lose, and the circuit can effectively prolong the time for maintaining the level and ensure the storage.
In summary, the present invention provides a power-down storage power management circuit, which includes a first dual diode, a second dual diode, a third dual diode, a triode, a second resistor, a third resistor, a fourth resistor, a second capacitor, a super capacitor, a battery and a memory; the collector electrode of the triode is connected with the super capacitor through a second resistor and a second double diode, the emitter electrode of the triode is connected with a system working power supply and the power supply end of the memory, and the base electrode of the triode is grounded through a fourth resistor and a fourth capacitor which are connected in series; the third double diode is connected between the battery and the control power supply through a third resistor, and a connecting point of a fourth resistor and a fourth capacitor is connected with the third double diode; the first double diode is connected among the system working power supply, the control power supply and the system rectification power supply, so that the voltages of the system working power supply and the control power supply are the same; the third double diode is connected with the power supply output end of the battery, and the second double diode is connected with the power supply output end of the super capacitor. The power-down data storage power supply management circuit can enable the intelligent meter to have enough power supply for data storage operation after detecting a power-down signal according to the difference of voltages of all parts during power-down, provides power supply support for power-down data storage, and simultaneously reduces the risk of device failure to the maximum extent.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (9)
1. A power-down storage power management circuit comprises a first double diode (Q1), a second double diode (Q2), a third double diode (Q3), a triode (Q4), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a second capacitor (C4), a super capacitor (CD1), a battery (B1) and a memory (U2);
the collector of the triode (Q4) is connected with the super capacitor (CD1) through a second resistor (R2) and a second double diode (Q2), the emitter of the triode (Q4) is connected with a system working power supply (VCC) and the power supply end of the memory (U2), and the base of the triode (Q4) is Grounded (GND) through a fourth resistor (R4) and a fourth capacitor (C4) which are connected in series; a third double diode (Q3) is connected between the battery (B1) and the control power supply (VCM) through a third resistor (R3), and a connection point of a fourth resistor (R4) and a fourth capacitor C4 is connected with a third double diode (Q3); the first double diode (Q1) is connected among the system working power supply (VCC), the control power supply (VCM) and the system rectification power supply (VDD) to ensure that the voltages of the system working power supply (VCC) and the control power supply (VCM) are the same; the third double diode (Q3) is connected with a battery power supply output end (VBATT), and the second double diode (Q2) is connected with a super capacitor power supply output end (VCAP).
2. The power down storage power management circuit according to claim 1, wherein two diodes of the first double diode (Q1) are connected in parallel to form three ends, the connection point of the anodes of the two diodes is the third end (13), and the cathodes of the two diodes are the first end (11) and the second end (12), respectively.
3. The power down storage power management circuit according to claim 2, wherein the first end (11) of the first double diode (Q1) is connected to a system operating power supply (VCC), the second end (12) is connected to a control power supply (VCM), and the third end (13) is connected to a system rectified power supply (VDD).
4. The power down memory power management circuit according to claim 1, wherein two diodes of a second double diode (Q2) are connected in series to form three terminals, the junction of the cathode of one diode and the anode of the other diode being the second terminal (22), the anode of one diode being the first terminal (21), and the cathode of the other diode being the third terminal (23).
5. The power down storage power management circuit according to claim 4, further comprising a first resistor (R1) and a first capacitor (C1), wherein the first end (21) of the second double diode (Q2) is connected to the system rectified power (VDD) through the first resistor (R1), the third end (23) is a super capacitor power output (VCAP), the second end (22) is connected to the anode of the super capacitor (CD1), the cathode of the super capacitor (CD1) is connected to the Ground (GND), and the first capacitor (C1) is connected between the system rectified power (VDD) and the Ground (GND).
6. The power down storage power management circuit according to claim 1, wherein two diodes of the third double diode (Q3) are connected in parallel to form three ends, cathodes of the two diodes are connected to form the third end (33), and anodes of the two diodes are respectively the first end (31) and the second end (32).
7. The power down memory power management circuit according to claim 6, wherein the third terminal (33) of the third double diode (Q3) is connected to a connection point of a fourth resistor (R4) and a fourth capacitor (C4), the first terminal (31) is connected to a battery power supply output terminal (VBATT), the anode of the battery (B1) is connected through the third resistor (R3), the cathode of the battery (B1) is connected to the Ground (GND), and the second terminal (32) of the third double diode (Q3) is connected to the control power supply (VCM).
8. The circuit for managing power supply with lost memory according to claim 1, characterized in that a diode (D1) is connected between said battery supply output (VBATT) and said super capacitor power supply output (VCAP), the battery supply output (VBATT) is connected to the anode of the diode (D1), and the super capacitor power supply output (VCAP) is connected to the cathode of the diode (D1).
9. The power down memory power management circuit of claim 1, wherein the memory (U2) is a chip and the power supply terminal is a pin.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110144240.9A CN112886701B (en) | 2021-02-02 | 2021-02-02 | Power-down storage power management circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110144240.9A CN112886701B (en) | 2021-02-02 | 2021-02-02 | Power-down storage power management circuit |
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| CN112886701B CN112886701B (en) | 2024-06-21 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103730953A (en) * | 2014-01-24 | 2014-04-16 | 深圳市思达仪表有限公司 | IC (Integrated Circuit) card intelligent water meter, and power supply managing circuit and method of IC card intelligent water meter |
| CN204886393U (en) * | 2015-05-22 | 2015-12-16 | 成都前锋电子仪器有限责任公司 | A power control system for intelligent gas meter |
| CN108429332A (en) * | 2018-05-18 | 2018-08-21 | 扬州万泰电子科技有限公司 | A kind of super capacitor application circuit of battery changeable type intelligent electric energy meter power supply |
| CN109932563A (en) * | 2019-01-30 | 2019-06-25 | 国网浙江省电力有限公司衢州供电公司 | A kind of intelligent electric energy meter that power down reports automatically |
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2021
- 2021-02-02 CN CN202110144240.9A patent/CN112886701B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730953A (en) * | 2014-01-24 | 2014-04-16 | 深圳市思达仪表有限公司 | IC (Integrated Circuit) card intelligent water meter, and power supply managing circuit and method of IC card intelligent water meter |
| CN204886393U (en) * | 2015-05-22 | 2015-12-16 | 成都前锋电子仪器有限责任公司 | A power control system for intelligent gas meter |
| CN108429332A (en) * | 2018-05-18 | 2018-08-21 | 扬州万泰电子科技有限公司 | A kind of super capacitor application circuit of battery changeable type intelligent electric energy meter power supply |
| CN109932563A (en) * | 2019-01-30 | 2019-06-25 | 国网浙江省电力有限公司衢州供电公司 | A kind of intelligent electric energy meter that power down reports automatically |
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