CN112866837A

CN112866837A - Network port radiation suppression circuit for OLT equipment and design method

Info

Publication number: CN112866837A
Application number: CN202011638300.4A
Authority: CN
Inventors: 麦海翔; 徐培根
Original assignee: Guangzhou V Solution Telecommunication Technology Co ltd
Current assignee: Guangzhou V Solution Telecommunication Technology Co ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-05-28
Anticipated expiration: 2040-12-31
Also published as: CN112866837B

Abstract

The invention relates to a network port radiation suppression circuit for OLT equipment and a design method thereof. The scheme comprises an oscillating circuit, a CPLD circuit, a divider resistor, a C1 capacitor, a C2 capacitor, a network transformer, a BOB-smith circuit and a processor; the oscillating circuit is used for outputting a single-ended clock to the CPLD circuit; the output of the CPLD circuit is connected with the divider resistor in parallel; the C1 capacitor comprises a C1 capacitor first terminal and a C1 capacitor second terminal; the C2 capacitor comprises a C2 capacitor first terminal and a C2 capacitor second terminal; the C1 capacitor and the C2 capacitor are connected with the output of the CPLD circuit; the second terminal of the C1 capacitor and the second terminal of the C2 capacitor are connected with the input of the processor; the processor is connected with the BOB-smith circuit through at least one network transformer. According to the scheme, interference is eliminated by reducing amplitude of a differential clock generated by a CPLD on OLT equipment, selecting a tap capacitor and a BOB-Smith circuit of a network port transformer, and the network port radiation of the OLT equipment is improved.

Description

Network port radiation suppression circuit for OLT equipment and design method

Technical Field

The invention relates to the field of electrical and electronic equipment, in particular to a network port radiation suppression circuit for OLT equipment and a design method.

Background

The (Optical Line Terminal, OLT) Optical Line Terminal equipment is a metal shell, and when a radiation test is performed, a network port of the OLT equipment is connected with a (Personal Computer, PC) Personal Computer through a network cable. The internal interference source of the OLT device is mainly concentrated in a plurality of groups of differential clocks supplied to a Passive Optical Network (PON) chip and a Central Processing Unit (CPU) chip, the clocks are used as a waveform with fixed frequency, and according to fourier transform, energy is concentrated, and radiation exceeding standards is easy to occur.

At present, the method in the prior art adopts a better shielding network cable, so that the shielding effect is as good as possible, a good shielding environment is kept as much as possible, and a small capacitor of 4.7PF/8.2PF is added on the IC side of the network port cable to filter high-frequency interference. But in the actual use environment, users generally do not use the shielding network cable, which leads to over-high radiation test. Therefore, the problem of network port radiation suppression when a shielding network cable is not used needs to be solved, and then the radiation test can be passed.

Disclosure of Invention

In order to overcome the problems in the related art, the invention provides a network port radiation suppression circuit for OLT equipment and a design method thereof, thereby solving the defect of overhigh network port radiation when a shielding network cable is not used.

According to a first aspect of the embodiments of the present invention, there is provided a network port radiation suppression circuit for an OLT apparatus, the circuit including: the circuit comprises an oscillating circuit, a CPLD circuit, a voltage dividing resistor, a C1 capacitor, a C2 capacitor, a network transformer and a BOB-smith circuit; the oscillating circuit is used for outputting a single-ended clock to the CPLD circuit; the CPLD circuit comprises 1 input, specifically a first CPLD input; the CPLD circuit comprises two outputs, namely a first CPLD output and a second CPLD output; the voltage division resistor is connected between the first CPLD output and the second CPLD output in parallel; the C1 capacitor comprises a C1 capacitor first terminal and a C1 capacitor second terminal; the C2 capacitor comprises a C2 capacitor first terminal and a C2 capacitor second terminal; the first end of the C1 capacitor is connected with the output of the first CPLD; the first end of the C2 capacitor is connected with the output of the second CPLD; the second terminal of the C1 capacitor and the second terminal of the C2 capacitor are connected with the input of the processor; the processor is connected with at least one network transformer, and the output of the network transformer is connected with the BOB-smith circuit.

In one or more embodiments, preferably, the voltage dividing resistor is a fixed resistor with a resistance of 5.1 ohms.

In one or more embodiments, the CPLD circuit preferably outputs a voltage with a level of 3.3V.

In one or more embodiments, preferably, the network transformer includes 6 inputs, including a network transformer first input, a network transformer second input, a network transformer third input, a network transformer fourth input, a network transformer fifth input, a network transformer sixth input;

the network transformer comprises 6 outputs including a first output of the network transformer, a second output of the network transformer, a third output of the network transformer, a fourth output of the network transformer, a fifth output of the network transformer and a sixth output of the network transformer;

the network transformer first input, the network transformer third input, the network transformer fourth input, and the network transformer sixth input are all grounded to a 4.7pF capacitor;

and the second input of the network transformer and the fifth input of the network transformer are connected with a capacitor C5 for filtering common-mode interference signals of the processor.

In one or more embodiments, preferably, the BOB-smith circuit includes a resistor R1, and the resistor R1 has a resistance of 50 ohms;

the resistor R1 is connected to the network transformer second output and the network transformer fifth output.

In one or more embodiments, preferably, the BOB-smith circuit includes a current surge dumping circuit, the current surge dumping circuit includes 1 bidirectional protection diode D1, and the bidirectional protection diode D1 is used for current surge dumping;

and the current surge discharging circuit is connected with the second output of the network transformer and the fifth output of the network transformer.

In one or more embodiments, preferably, the BOB-smith circuit includes a capacitor C6, the capacitor C6 is a ceramic capacitor, and the capacitor C6 has a capacitance value of 1 uF;

the capacitor C6 is connected with the resistor R1 in series and then is grounded;

the capacitor C6 is connected in series with the resistor R1 and then connected in parallel with the current surge discharging circuit.

According to a second aspect of the embodiments of the present invention, there is provided a design method for a network port radiation suppression circuit of an OLT apparatus, where the design method includes:

configuring an input single-ended clock into at least one pair of output differential clocks by writing logic code;

configuring the output differential clock to be 20% of the amplitude of the original input single-ended clock;

the processor provides a data signal to at least one network transformer according to the output differential clock;

grounding a tap connection capacitor of the network transformer according to the internal structure of the network transformer, and filtering a common mode interference signal of the processor;

according to the capacitance frequency characteristic curve, when the capacitance resonance frequency is the lowest capacitance impedance value, filtering an interference signal according to a first calculation formula;

designing resistance and capacitance parameters of the BOB-Smith circuit, and filtering interference signals;

the first calculation formula:

wherein ESR is the equivalent resistance of the ceramic capacitor in series, Tan delta is the loss tangent of the ceramic capacitor, and f₀Is the resonant frequency point of the ceramic capacitor.

In one or more embodiments, preferably, the configuring the output differential clock to be 20% of the amplitude of the original input single-ended clock specifically includes:

setting the pin function in the CPLD circuit, selecting the output level type as a voltage signal of 3.3V, automatically setting a corresponding pin as a differential P pin by the CPLD circuit, and automatically allocating an N pin to a differential pin corresponding to the P pin;

the differential signal output by the CPLD circuit is approximate to a square wave, wherein the amplitude of the square wave is E, and Fourier series expansion of the square wave is obtained according to a second calculation formula and a third calculation formula;

according to the fact that the input of a processor is CML level, a C1 capacitor and a C2 capacitor are added between the output clock of the CPLD circuit and the processor to carry out AC coupling;

according to the internal pin structure of the CPLD circuit, a resistor is added between PN and forms a voltage division loop with a pull-up current-limiting resistor, the input voltage of the CPLD circuit is divided, and the voltage division is carried out to obtain an output voltage of 0.6V;

according to the first formula analysis, determining that the energy is reduced to 20% of the original energy;

the second calculation formula is:

wherein f (T) is a square wave function, E is the amplitude, T is time, and T is a period;

the third calculation formula is:

wherein g (t) is a Fourier transform function of a square wave function, E is the amplitude, t is time, n is an integer, and ω is₀Is the fundamental angular velocity.

In one or more embodiments, preferably, the designing of the resistance and capacitance parameters of the BOB-Smith circuit and the filtering of the interference signal specifically include:

selecting the interference frequency as a resonance frequency, and obtaining a capacitor of the interference frequency as a tap capacitor according to the relation between the resonance frequency and the capacitance value, ESR and loss tangent value of the ceramic capacitor;

according to the function requirement of the BOB-Smith circuit, each path of surge protection tubes is connected in parallel and is a surge discharge path, so that the capacitor C6 of the BOB-Smith circuit does not play a protection role;

the differential impedance is controlled to be 100 ohms when a PCB is manufactured, and each tap resistor of the BOB-Smith circuit is selected to be half of the differential impedance and is set to be 50 ohms;

selecting a capacitance value C6 of the BOB-Smith circuit to filter interference signals;

all taps of the network transformer are connected together, and only 1 path of interference signal is reserved for filtering.

The technical scheme provided by the embodiment of the invention can have the following beneficial effects:

1. the invention can output multi-path differential clock signals by directly using one logic chip through the scheme, and solves the problem that only a plurality of paths of differential outputs can be provided by 1 differential clock buffer chip in the prior art.

2. The invention adjusts the amplitude by connecting the resistor between the logic output differential clock lines, has simple circuit, can reduce the clock radiation intensity and can simultaneously meet the requirement of the load on the input signal level.

3. The invention does not increase a great amount of components, does not occupy the space of a PCB, has little change, can ensure that the selection of the capacitance of the BOB-Smith circuit is not limited, is suitable for the field of radiation rectification for filtering signal wires by the capacitance without radiation loss and using shielding wires, can also be used for metal packaging equipment, equipment with a network cable or other metal wires leading out of a shell, and can also play a role in radiation inhibition for equipment separated due to surge test.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a block diagram of a network port emission suppression circuit for an OLT apparatus according to an embodiment of the present invention.

Fig. 2 is a schematic output diagram of a CPLD circuit for an OLT device port radiation suppression circuit according to an embodiment of the present invention.

Fig. 3 is a connection diagram of an external electrical structure of a CPLD circuit in a gait collection display device used in a gateway radiation suppression circuit of an OLT device according to an embodiment of the present invention.

Fig. 4 is an internal electrical structure diagram of a CPLD circuit in a gait acquisition and display device used in a portal radiation suppression circuit of an OLT apparatus according to an embodiment of the present invention.

Fig. 5 is a diagram of an internal structure of a network transformer used in a network port radiation suppression circuit of an OLT apparatus according to an embodiment of the present invention.

Fig. 6 is an external structural diagram of a network transformer used in an OLT equipment port radiation suppression circuit according to an embodiment of the present invention.

Fig. 7 is a flowchart of a design method for an OLT equipment port emission suppression circuit according to an embodiment of the present invention.

Fig. 8 is a flowchart of the method for designing an OLT device port emission suppression circuit according to an embodiment of the present invention, where the output differential clock is configured to be 20% of the amplitude of the original input single-ended clock.

Fig. 9 is a flowchart of a method for designing a BOB-Smith circuit according to an embodiment of the present invention, where the method is used in a design method of a network port radiation suppression circuit of an OLT device to filter interference signals.

Fig. 10 is a graph of capacitance-frequency characteristics in a design method for an OLT equipment port radiation suppression circuit according to an embodiment of the present invention.

Fig. 11 is a diagram illustrating an effect of a network port radiation suppression circuit for an OLT apparatus according to an embodiment of the present invention before implementation.

Fig. 12 is a diagram illustrating an effect of an implementation of a network port radiation suppression circuit for an OLT apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.

In some of the flows described in the present specification and claims and in the above figures, a number of operations are included that occur in a particular order, but it should be clearly understood that these operations may be performed out of order or in parallel as they occur herein, with the order of the operations being indicated as 101, 102, etc. merely to distinguish between the various operations, and the order of the operations by themselves does not represent any order of performance. Additionally, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel. It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Before the technology of the invention, the method in the prior art adopts a better shielding network wire, so that the shielding effect is as good as possible, the good shielding environment is kept as much as possible, and a small capacitor of 4.7PF/8.2PF is added at one side of the network port wire close to an Integrated circuit chip (IC) chip, so as to filter high-frequency interference. But in the actual use environment, users generally do not use the shielding network cable, which leads to over-high radiation test. In addition, in the prior art, a tap on the network interface side of the network transformer is connected with a small capacitor to the ground through a 75-ohm resistor in series, but a certain small current passes through the resistor, so that noise is generated to radiate outwards, and the radiation test of the OLT equipment exceeds the standard and cannot pass through the OLT equipment. Therefore, it is necessary to solve the problem of the radiation suppression of the net opening when the shielding net wire is not used, so as to pass the radiation test.

The invention considers to construct a network port radiation suppression circuit for OLT equipment and a design method thereof, and eliminates interference by reducing amplitude of a differential clock generated by a CPLD on the OLT equipment, selecting a tap capacitor and selecting a BOB-Smith circuit of a network port transformer, thereby improving the network port radiation of the OLT equipment.

In one or more embodiments, as shown in fig. 1, preferably, the network port radiation suppression circuit for OLT equipment includes: the circuit comprises an oscillating circuit 101, a CPLD circuit 102, a voltage dividing resistor 103, a C1 capacitor 104, a C2 capacitor 105, a network transformer 106, a BOB-smith circuit 107 and a processor 108; the oscillating circuit 101 is used for outputting a single-ended clock to the CPLD circuit 102; the CPLD circuit 102 includes 1 input, specifically a first CPLD input; the CPLD circuit 102 includes two outputs, namely a first CPLD output and a second CPLD output; the voltage dividing resistor 103 is connected in parallel between the first CPLD output and the second CPLD output; the C1 capacitor 104 includes a C1 capacitor first terminal and a C1 capacitor second terminal; the C2 capacitor 105 comprises a C2 capacitor first terminal and a C2 capacitor second terminal; the first end of the C1 capacitor is connected with the output of the first CPLD; the first end of the C2 capacitor is connected with the output of the second CPLD; the second terminal of the C1 capacitor and the second terminal of the C2 capacitor are connected to the input of the processor 108; the processor 108 is connected to at least one of the network transformers 106, and an output of the network transformer 106 is connected to the BOB-smith circuit 107.

Specifically, (Complex Programmable Logic Device, CPLD) is a Logic element which is more Complex than PLD, and CPLD is a digital integrated circuit which users can construct Logic functions according to their needs.

The working principle is as follows: the oscillation circuit firstly operates to obtain a single clock signal, the clock signal is divided into a plurality of clock signals through the CPLD circuit, voltage reduction is further carried out through the voltage dividing resistor, AC coupling is carried out through the C1 capacitor and the C2 capacitor, and finally, tasks such as surge discharge are completed through the BOB-smith circuit.

In the embodiment of the present invention, a circuit architecture for the network port radiation suppression of the OLT device is provided, in which the voltage dividing resistor pulls down the output voltage of the CPLD circuit 102 from a level of 3.3V, but at the same time, it can ensure that the output voltage level is sufficient to support the subsequent network transformer operation.

Fig. 2 is a schematic output diagram of the CPLD circuit 102 for the OLT device port radiation suppression circuit according to an embodiment of the present invention. In the embodiment of the invention, in the writing of logic codes, the input single-ended clock is configured to output a differential clock, so that a pair of differential clocks can be output, and a plurality of pairs of differential clocks can also be output. And then in the pin setting of the logic chip, the output level type is selected to be the level of 3.3V, the CPLD circuit automatically sets the pin as a differential P pin and automatically allocates an N pin to the corresponding pin of the differential pair, and the differential signal output by the CPLD circuit is approximate to a square wave, wherein E represents the amplitude of the square wave.

Fig. 3 is a connection diagram of an external electrical structure of a CPLD circuit 102 in a gait collection display device used in a portal radiation suppression circuit of an OLT apparatus according to an embodiment of the present invention. Fig. 4 is an internal electrical structural diagram of a CPLD circuit 102 used in a gait acquisition and display device in a portal radiation suppression circuit of an OLT apparatus according to an embodiment of the present invention. In one or more embodiments, as shown in fig. 3, the voltage dividing resistor 103 is preferably a fixed resistor with a resistance of 5.1 ohms. As shown in fig. 4, in one or more embodiments, the CPLD circuit 102 preferably outputs a voltage with a level of 3.3V.

In the embodiment of the invention, because the level of the pull-up resistor in the circuit is 3.3V, when the circuit adopts a resistor with the resistance value of 5.1 ohm for voltage division, the voltage division resistor is added between PN, and the voltage division resistor and the pull-up current limiting resistor form a voltage division circuit for voltage division of 3.3V VCC to obtain a 0.6V voltage, finally the square wave amplitude of the voltage is 1/5, and the finally generated energy is 20% of the original energy.

Fig. 5 is a diagram of an internal structure of a network transformer used in a network port radiation suppression circuit of an OLT apparatus according to an embodiment of the present invention. Fig. 6 is a schematic diagram of an external structure of a network transformer used in a network port radiation suppression circuit of an OLT apparatus according to an embodiment of the present invention.

In one or more embodiments, the network transformer 106 preferably includes 6 inputs, including a network transformer first input 501, a network transformer second input 502, a network transformer third input 503, a network transformer fourth input 504, a network transformer fifth input 505, a network transformer sixth input 506;

the network transformer 106 comprises 6 outputs including a network transformer first output 507, a network transformer second output 508, a network transformer third output 509, a network transformer fourth output 510, a network transformer fifth output 511, a network transformer sixth output 512;

the network transformer first input 501, the network transformer third input 503, the network transformer fourth input 504, and the network transformer sixth input 506 are all grounded to a 4.7pF capacitor;

the network transformer second input 502 and the network transformer fifth input 505 are connected to a capacitor C5 for filtering out common mode interference signals of the processor 108.

In one or more embodiments, preferably, the BOB-smith circuit 107 includes a resistor R1, and the resistor R1 has a resistance of 50 ohms;

the resistor R1 is connected to the network transformer second output 508 and the network transformer fifth output 511.

In one or more embodiments, preferably, the BOB-smith circuit 107 comprises a current surge dumping circuit, the current surge dumping circuit comprises 1 bidirectional protection diode D1, and the bidirectional protection diode D1 is used for current surge dumping.

The current surge dumping circuit is connected with the network transformer second output 508 and the network transformer fifth output 511.

The BOB-smith circuit comprises a capacitor C6, the capacitor C6 is a ceramic capacitor, and the capacitance value of the capacitor C6 is 1 uF;

Specifically, in the BOB-Smith circuit, because the tap has a selective anti-detonator protection design, the network port lightning protection is mainly carried out by the anti-detonator, the 1nF high-voltage ceramic capacitor of the tap does not need a very high withstand voltage value, a large-capacitance value and a low withstand voltage ceramic capacitor can be selected, the conventional 1nF is changed into 1uF, and the power frequency interference of the network port measuring tap is ensured to be very low. Therefore, the problem can be solved only by one 1uF, and when a single capacitor cannot solve the problem or is not sensitive to cost, a cascade method can be used, and a cascade mode of 1uF and 100nF is adopted, so that the low-frequency component of the network cable relative to the ground is reduced, and the radiation propagation distance is reduced. Therefore, as an aid, a capacitance to ground of 4.7pF is added to the signal line near the CPLD side.

In the embodiment of the invention, a common mode interference signal of the network transformer can be filtered through the side tap, according to the function of the BOB-Smith circuit, the capacitor C6 can be used as a protective capacitor when surge impact occurs, and a high-voltage capacitor is needed, so that the selection limit of the capacitor is large and the selectable range is small, but each path of the BOB-Smith circuit is connected with a surge protection path in parallel, the bidirectional protection diode D1 is used as a surge discharge path, and the capacitor C6 of the BOB-Smith circuit does not play a protection role, only the EMC function is considered, and the selection range is larger. In addition, because the differential impedance needs to be 100 ohms according to the requirements of the plate making, the tap resistance of each path of the BOB-Smith circuit is selected to be half of the differential impedance, and R1 is 50 ohms, so that the impedance continuity is maintained, and signal reflection cannot be generated when interference signals are filtered.

As shown in fig. 7, in one or more embodiments, preferably, a second aspect of the embodiments of the present invention provides a design method for an OLT device port emission suppression circuit, where the design method includes:

s701, programming by using logic codes to configure an input single-ended clock into at least one pair of output differential clocks;

s702, configuring the output differential clock to be 20% of the amplitude of the original input single-ended clock;

s703, the processor provides data signals to at least one network transformer according to the output differential clock;

s704, grounding a tap of the network transformer with a capacitor according to the internal structure of the network transformer, and filtering a common mode interference signal of the processor;

s705, filtering interference signals according to a first calculation formula when the capacitance resonance frequency is the lowest capacitance impedance value according to the capacitance frequency characteristic curve;

s706, designing resistance and capacitance parameters of the BOB-Smith circuit, and filtering interference signals;

the first calculation formula:

In the embodiment of the invention, firstly, a logic code is designed in a CPLD according to requirements to further obtain a multi-path differential clock, under the condition, the multi-path differential clock signal can be directly output by using one logic chip, and the problem that only a plurality of paths of differential outputs can be provided by 1 differential clock buffer provided by a differential clock buffer chip in the prior art is solved; on the basis, a radiation suppression circuit is designed, and interference signals are filtered through parameter selection.

As shown in fig. 8, in one or more embodiments, preferably, the configuring the output differential clock to be 20% of the amplitude of the original input single-ended clock specifically includes:

s801, setting pin functions in the CPLD circuit, selecting the output level type as a voltage signal of 3.3V, automatically setting corresponding pins as differential P pins by the CPLD circuit, and automatically allocating N pins to the differential pins corresponding to the P pins;

s802, the differential signal output by the CPLD circuit is approximate to a square wave, wherein the amplitude of the square wave is E, and Fourier series expansion of the square wave is obtained according to a second calculation formula and a third calculation formula;

s803, according to the CML level of the processor input, a C1 capacitor 104 and a C2 capacitor 105 are added between the CPLD circuit output clock and the processor for AC coupling;

specifically, the CML is Current Mode Logic, specifically Current Mode Logic, and the CML circuit is mainly driven by Current and is a signal transmission Mode with low power consumption;

s804, adding a resistor between PN according to the internal pin structure of the CPLD circuit, forming a voltage division loop with a pull-up current-limiting resistor, and dividing the input voltage of the CPLD circuit to obtain an output voltage of 0.6V;

s805, analyzing according to the first formula, and determining that the energy is reduced to 20% of the original energy;

the second calculation formula is:

the third calculation formula is:

In the embodiment of the invention, according to the scheme, the first task is to reduce the radiation intensity of the clock source, so that the amplitude of the differential clock is reduced as much as possible on the premise of meeting the requirements of a chip, a 5.1R resistor is connected in parallel between PN pins of the differential clock at the CPLD end, and the signal amplitude is reduced to about 0.6V. The source radiation intensity is reduced to 20% of the original.

As shown in fig. 9, in one or more embodiments, preferably, the designing the resistance and capacitance parameters of the BOB-Smith circuit to filter the interference signal specifically includes:

s901, selecting interference frequency as resonance frequency, and obtaining a capacitor of the interference frequency as a tap capacitor according to the relation between the resonance frequency and the capacitance value, ESR and loss tangent value of the ceramic capacitor;

s902, according to the function requirements of the BOB-Smith circuit, connecting a surge protection tube in parallel to each path, wherein the surge protection tube is a surge discharge path, and the capacitor C6 of the BOB-Smith circuit does not play a protection role;

s903, controlling the differential impedance to be 100 ohms when a PCB is manufactured, wherein the tap resistance of each path of the BOB-Smith circuit is selected to be half of the differential impedance and is set to be 50 ohms;

s904, selecting a capacitance value C6 of the BOB-Smith circuit to filter interference signals;

and S905, connecting all taps of the network transformer together, and only 1 path of interference signal is required to be filtered.

In the embodiment of the invention, the resistance and the capacitance of the BOB-Smith are calculated, so that two purposes are mainly realized, the first is to filter the interference signal by utilizing C6 without limiting the selection range of the capacitance value, and the second is to select the tap resistance as 50 ohms to keep the continuity of impedance, so that the purpose that the signal reflection is not generated when the interference signal is filtered, and the extra radiation is generated.

Fig. 10 is a graph of capacitance-frequency characteristics in a design method for an OLT equipment port radiation suppression circuit according to an embodiment of the present invention. As shown in fig. 10, in the embodiment of the present invention, the capacitance having the resonant frequency closest to the interference frequency is selected to have the best filtering effect, and according to the relationship between the resonant frequency and the capacitance value, the ESR, and the loss tangent of the ceramic capacitor, the capacitance having the resonant frequency closest to the interference frequency can be obtained as the tap capacitance by using the first calculation formula, where the capacitance manufacturers provide the ESR and loss tangent.

Fig. 11 is a diagram illustrating an effect of a network port radiation suppression circuit for an OLT apparatus according to an embodiment of the present invention before implementation. Fig. 12 is a diagram illustrating an effect of an implementation of a network port radiation suppression circuit for an OLT apparatus according to an embodiment of the present invention. As shown in fig. 11 and 12, the results of the 3m radiation test before and after the rectification are compared: the superscript point of the frequency multiplication of 25MHz such as 175MHz, 225MHz, 250MHz, 475MHz, 525MHz, 625MHz, etc. has at least 4 dB margin after the adjustment.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. An OLT equipment port emission suppression circuit, comprising: the circuit comprises an oscillating circuit, a CPLD circuit, a voltage dividing resistor, a C1 capacitor, a C2 capacitor, a network transformer, a BOB-smith circuit and a processor; the oscillating circuit is used for outputting a single-ended clock to the CPLD circuit; the CPLD circuit comprises 1 input, specifically a first CPLD input; the CPLD circuit comprises two outputs, namely a first CPLD output and a second CPLD output; the voltage division resistor is connected between the first CPLD output and the second CPLD output in parallel; the C1 capacitor comprises a C1 capacitor first terminal and a C1 capacitor second terminal; the C2 capacitor comprises a C2 capacitor first terminal and a C2 capacitor second terminal; the first end of the C1 capacitor is connected with the output of the first CPLD; the first end of the C2 capacitor is connected with the output of the second CPLD; the second terminal of the C1 capacitor and the second terminal of the C2 capacitor are connected with the input of the processor; the processor is connected with at least one network transformer, and the output of the network transformer is connected with the BOB-smith circuit.

2. The network port radiation suppression circuit for the OLT equipment of claim 1, wherein the voltage dividing resistor is a constant resistor with a resistance of 5.1 ohms.

3. The OLT equipment port radiation suppression circuit of claim 1, wherein the CPLD circuit outputs a voltage at a level of 3.3V.

4. The OLT equipment port radiation suppression circuit of claim 1, wherein the network transformer comprises 6 inputs, the 6 inputs comprising a network transformer first input, a network transformer second input, a network transformer third input, a network transformer fourth input, a network transformer fifth input, a network transformer sixth input;

the network transformer comprises 6 outputs, wherein the 6 outputs comprise a first output of the network transformer, a second output of the network transformer, a third output of the network transformer, a fourth output of the network transformer, a fifth output of the network transformer and a sixth output of the network transformer;

5. The net port radiation suppression circuit for OLT equipment of claim 4, wherein said BOB-smith circuit comprises a resistor R1, said resistor R1 has a resistance of 50 ohms;

6. The OLT equipment portal radiation suppression circuit of claim 5, wherein the BOB-smith circuit comprises a current surge dump circuit comprising 1 bidirectional protection diode D1;

7. The OLT apparatus net port radiation suppression circuit of claim 6, wherein the BOB-smith circuit comprises a capacitor C6, the capacitor C6 is a ceramic capacitor, and the capacitor C6 has a capacitance value of 1 uF;

8. A design method for an OLT equipment network port radiation suppression circuit is characterized by comprising the following steps:

the first calculation formula:

wherein ESR is equivalent series capacitance of ceramic capacitorTan delta is the ceramic capacitance loss tangent, f₀Is the resonant frequency point of the ceramic capacitor.

9. The design method of claim 8, wherein the configuring the output differential clock to be 20% of the amplitude of the original input single-ended clock comprises:

setting the pin function in a CPLD circuit, selecting the output level type as a voltage signal of 3.3V, automatically setting a corresponding pin as a differential P pin by the CPLD circuit, and automatically allocating an N pin to a differential pin corresponding to the P pin;

the second calculation formula is:

the third calculation formula is:

wherein g is: (t) is a Fourier transform function of a square wave function, E is the amplitude, t is time, n is an integer, omega₀Is the fundamental angular velocity.

10. The method according to claim 8, wherein the designing of the parameters of resistance and capacitance of the BOB-Smith circuit to filter the interference signal includes: