CN104935286A - Method for implementing impedance matching optimization of high-speed digital circuit - Google Patents
Method for implementing impedance matching optimization of high-speed digital circuit Download PDFInfo
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- CN104935286A CN104935286A CN201510330292.XA CN201510330292A CN104935286A CN 104935286 A CN104935286 A CN 104935286A CN 201510330292 A CN201510330292 A CN 201510330292A CN 104935286 A CN104935286 A CN 104935286A
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Abstract
The invention discloses a method for implementing impedance matching optimization of a high-speed digital circuit. The method comprises the following steps: building a model for a signal to be matched, and adding a transmission line model according to a transmission line theory; measuring a signal source end to be matched and a load end signal waveform respectively through an oscilloscope, and determining the waveform distortion situation of the signal transmitted through a transmission line at a load end under the situation that no impedance matching network is added; accessing the impedance matching network, configuring the impedance matching network according to a matched signal level, and determining which matching modes are more suitable through dial-up of the impedance matching network; and determining a most suitable matching way according the quantity, prices and power consumption of devices. The influence of impedance mismatching on the signal quality is lowered or eliminated through selection of suitable impedance matching at the load end. Meanwhile, noise, electromagnetic interference and radio-frequency interference can be lowered; the interference on other signals inside an electronic system and the interference of other external electronic equipment are lowered; and the equipment stability is enhanced.
Description
Technical field
The present invention relates to digital circuit impedance match technique field, be specifically related to one and realize the optimized method of high-speed digital circuit impedance matching.
Background technology
Along with the rapid raising of data transmission bauds in electronic system and system clock frequency, and the continuous steepening of signal elevating time, frequency also rises to number GHz of today from the MHz in past, and even higher frequency development, speed has become of paramount importance factor in system.In the past in low frequency system design, signal transmission path is very short relative to wavelength, does not need to consider fluctuation effect, as long as baseband signal couples together just can ensure that equipment normally works; But high-speed product design in, its operating frequency at 100MHz or several GHz, signal wavelength and length of transmission line comparable time, reflected signal is superimposed upon the shape that original signal will change original signal, can have a strong impact on signal quality.
Impedance matching is the key factor that High Speed System design must be considered, impedance mismatch can cause ring to affect signal voltage and sequential, and has a strong impact on signal quality, can aggravate electromagnetic interference simultaneously.
In high-speed digital system, not mating and causing signal reflex appears in transmission line impedance, occur that reflection can have a strong impact on the quality of signal at signal receiving end, more even can affect the accuracy receiving data, occur that in fields such as industry control, space flight, medical treatment this situation can serious threat life security.
Summary of the invention
The technical problem to be solved in the present invention is: the present invention is directed to above problem, provides one to realize the optimized method of high-speed digital circuit impedance matching.
The technical solution adopted in the present invention is:
One realizes the optimized method of high-speed digital circuit impedance matching, described method is by carrying out model buildings to the signal that will mate, transmission line model is added according to transmission line theory, then the signal source and load end signal waveform that will mate is measured respectively by oscilloscope, determine when the not adding impedance matching network signal wave distortion situation at load end after transmission line transmits, then termination matching network, according to institute's matched signal level configure impedance matching network, determine which is planted match pattern and is more suitable for by the dial-up of impedance matching network, last according to number of devices, price, power consumption determines a kind of most suitable matching way.
Signal impedance coupling can realize in source or load, as long as ensure source reflection coefficient or load reflection coefficient, one of them is zero, can both eliminate reflection.From system design view, impedance matching should be carried out by first-selected load end, because eliminated reflection at load end before source is returned in signal reflex, thus eliminate primary event, can noise decrease, electromagnetic interference and radio frequency interference; And carry out impedance matching in source and need to eliminate the signal that reflected by load end, eliminate secondary reflection, when there is level transfer, source there will be half waveform, so the main pin of the present invention carries out matching way design at signal load end.
Described method concrete operation step is as follows:
First source (Source) adds signal generator, in order to adjust signal frequency, amplitude and rise time, sets fixing signal frequency, amplitude and after going up the time, and signal, through the transmission of PCB cabling, arrives impedance matching network;
According to the signal frequency set in advance, amplitude, rise time, parameter adjustment is carried out to the matching way in impedance matching network, guarantee that impedance matching network and institute's signal transmission are arranged in pairs or groups;
By oscilloscope, the waveform that often kind of matching way is measured is contrasted, choose optimization matching mode, and comprehensive consideration number of devices used and price factor.
The integrated load end matching way of described matching network comprises:
Matching way 1: single resistor coupled in parallel termination;
Matching way 2: Dai Weining parallel end connection;
Matching way 3: initiatively parallel end connection;
Matching way 4: AC termination in parallel;
Matching way 5: Schottky diode termination.
Matching way in impedance matching network carries out parameter tuning process: first verify with matching way 1, and with oscilloscope measurement source and load end waveform, checks wave distortion degree, and finely tunes matching way 1 Verification; Test matching way 2,3,4,5 successively, finely tune matching way to optimization,
Described signal lead length is suitable with institute's transmitted signal wavelengths, avoids cabling much smaller than wavelength.
Beneficial effect of the present invention is: the present invention, by selecting suitable impedance matching methods at load end, reduces or eliminates the impact of impedance mismatch on signal quality; Simultaneously can noise decrease, electromagnetic interference and radio frequency interference, reduce the interference to other signals of electronic system inside and other electronic equipments outside, improve stabilization of equipment performance.
Accompanying drawing explanation
Fig. 1 is the method operation principle schematic diagram of validation signal impedance matching mode of the present invention.
Embodiment
With reference to the accompanying drawings, by embodiment, the present invention is further described:
Embodiment 1:
One realizes the optimized method of high-speed digital circuit impedance matching, described method is by carrying out model buildings to the signal that will mate, transmission line model is added according to transmission line theory, then the signal source and load end signal waveform that will mate is measured respectively by oscilloscope, determine when the not adding impedance matching network signal wave distortion situation at load end after transmission line transmits, then termination matching network, according to institute's matched signal level configure impedance matching network, determine which is planted match pattern and is more suitable for by the dial-up of impedance matching network, last according to number of devices, price, power consumption determines a kind of most suitable matching way.
Signal impedance coupling can realize in source or load, as long as ensure source reflection coefficient or load reflection coefficient, one of them is zero, can both eliminate reflection.From system design view, impedance matching should be carried out by first-selected load end, because eliminated reflection at load end before source is returned in signal reflex, thus eliminate primary event, can noise decrease, electromagnetic interference and radio frequency interference; And carry out impedance matching in source and need to eliminate the signal that reflected by load end, eliminate secondary reflection, when there is level transfer, source there will be half waveform, so the main pin of the present invention carries out matching way design at signal load end.
Embodiment 2:
As shown in Figure 1, on the basis of embodiment 1, described in the present embodiment, method concrete operation step is as follows:
First source (Source) adds signal generator, in order to adjust signal frequency, amplitude and rise time, sets fixing signal frequency, amplitude and after going up the time, and signal, through the transmission of PCB cabling, arrives impedance matching network;
According to the signal frequency set in advance, amplitude, rise time, parameter adjustment is carried out to the matching way in impedance matching network, guarantee that impedance matching network and institute's signal transmission are arranged in pairs or groups;
By oscilloscope, the waveform that often kind of matching way is measured is contrasted, choose optimization matching mode, and comprehensive consideration number of devices used and price factor.
Embodiment 3:
On the basis of embodiment 2, the integrated load end matching way of matching network described in the present embodiment comprises:
Matching way 1: single resistor coupled in parallel termination;
Matching way 2: Dai Weining parallel end connection;
Matching way 3: initiatively parallel end connection;
Matching way 4: AC termination in parallel;
Matching way 5: Schottky diode termination.
Embodiment 4:
On the basis of embodiment 3, matching way in the present embodiment impedance matching network carries out parameter tuning process: first verify with matching way 1, and with oscilloscope measurement source and load end waveform, check wave distortion degree, and finely tune matching way 1 Verification; Test matching way 2,3,4,5 successively, finely tune matching way to optimization,
Embodiment 5:
On the basis of embodiment 1,2,3 or 4, signal lead length described in the present embodiment is suitable with institute's transmitted signal wavelengths, avoids cabling much smaller than wavelength.
Above execution mode is only for illustration of the present invention; and be not limitation of the present invention; the those of ordinary skill of relevant technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (5)
1. one kind realizes the optimized method of high-speed digital circuit impedance matching, it is characterized in that: described method is by carrying out model buildings to the signal that will mate, transmission line model is added according to transmission line theory, then the signal source and load end signal waveform that will mate is measured respectively by oscilloscope, determine when the not adding impedance matching network signal wave distortion situation at load end after transmission line transmits, then termination matching network, according to institute's matched signal level configure impedance matching network, determine which is planted match pattern and is more suitable for by the dial-up of impedance matching network, last according to number of devices, price, power consumption determines a kind of most suitable matching way.
2. one according to claim 1 realizes the optimized method of high-speed digital circuit impedance matching, it is characterized in that, described method concrete operation step is as follows:
First source adds signal generator, in order to adjust signal frequency, amplitude and rise time, sets fixing signal frequency, amplitude and after going up the time, and signal, through the transmission of PCB cabling, arrives impedance matching network;
According to the signal frequency set in advance, amplitude, rise time, parameter adjustment is carried out to the matching way in impedance matching network, guarantee that impedance matching network and institute's signal transmission are arranged in pairs or groups;
By oscilloscope, the waveform that often kind of matching way is measured is contrasted, choose optimization matching mode, and comprehensive consideration number of devices used and price factor.
3. one according to claim 2 realizes the optimized method of high-speed digital circuit impedance matching, it is characterized in that, the integrated load end matching way of described matching network comprises:
Matching way 1: single resistor coupled in parallel termination;
Matching way 2: Dai Weining parallel end connection;
Matching way 3: initiatively parallel end connection;
Matching way 4: AC termination in parallel;
Matching way 5: Schottky diode termination.
4. one according to claim 3 realizes the optimized method of high-speed digital circuit impedance matching, it is characterized in that, matching way in impedance matching network carries out parameter tuning process: first verify with matching way 1, and with oscilloscope measurement source and load end waveform, check wave distortion degree, and finely tune matching way 1 Verification; Test matching way 2,3,4,5 successively, fine setting matching way is to optimization.
5. realize the optimized method of high-speed digital circuit impedance matching according to the arbitrary described one of claim 1,2,3 or 4, it is characterized in that: described signal lead length is suitable with institute's transmitted signal wavelengths, avoids cabling much smaller than wavelength.
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| CN201510330292.XA CN104935286A (en) | 2015-06-16 | 2015-06-16 | Method for implementing impedance matching optimization of high-speed digital circuit |
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| CN201510330292.XA CN104935286A (en) | 2015-06-16 | 2015-06-16 | Method for implementing impedance matching optimization of high-speed digital circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110765494A (en) * | 2018-11-22 | 2020-02-07 | 哈尔滨安天科技集团股份有限公司 | Pin terminal matching circuit for reducing side channel information leakage |
| CN112327030A (en) * | 2020-11-06 | 2021-02-05 | 苏州浪潮智能科技有限公司 | Link impedance matching debugging method and device |
| CN117061271A (en) * | 2023-09-06 | 2023-11-14 | 蚌埠依爱消防电子有限责任公司 | Bus communication automatic regulating method for fire-fighting product |
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| US20060250158A1 (en) * | 2003-06-24 | 2006-11-09 | Yoshitaka Yaguchi | Device and method for matching output impedance in signal transmission system |
| CN1874148A (en) * | 2005-06-02 | 2006-12-06 | 华为技术有限公司 | Negative feedback circuit, as well as method and device for implementing impedance match of transmission line in chip by using the circuit |
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2015
- 2015-06-16 CN CN201510330292.XA patent/CN104935286A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060250158A1 (en) * | 2003-06-24 | 2006-11-09 | Yoshitaka Yaguchi | Device and method for matching output impedance in signal transmission system |
| CN1874148A (en) * | 2005-06-02 | 2006-12-06 | 华为技术有限公司 | Negative feedback circuit, as well as method and device for implementing impedance match of transmission line in chip by using the circuit |
Non-Patent Citations (1)
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| 郭宏科: "工业互连电缆信号完整性及其抗干扰技术研究", 《中国优秀硕士学位论文全文数据库》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110765494A (en) * | 2018-11-22 | 2020-02-07 | 哈尔滨安天科技集团股份有限公司 | Pin terminal matching circuit for reducing side channel information leakage |
| CN112327030A (en) * | 2020-11-06 | 2021-02-05 | 苏州浪潮智能科技有限公司 | Link impedance matching debugging method and device |
| CN112327030B (en) * | 2020-11-06 | 2022-12-16 | 苏州浪潮智能科技有限公司 | Link impedance matching debugging method and device |
| CN117061271A (en) * | 2023-09-06 | 2023-11-14 | 蚌埠依爱消防电子有限责任公司 | Bus communication automatic regulating method for fire-fighting product |
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Application publication date: 20150923 |
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