CN112838059B - Array substrate and manufacturing method thereof - Google Patents
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- 238000005530 etching Methods 0.000 claims description 29
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
The invention discloses an array substrate and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: forming a pattern of a plurality of pixel electrodes, a plurality of data lines, a plurality of common voltage lines, and connection portions on a substrate, each common voltage line being electrically connected to adjacent pixel electrodes through the connection portions; after loading test signals on each data line, receiving and comparing the test signals transmitted by each data line, determining that short-circuit residues exist between at least one data line and the pixel electrode when the test signals transmitted by at least one data line are different from the test signals transmitted by other data lines, and removing the short-circuit residues; the number of the at least one data line is smaller than the number of the other data lines; the connection portion is etched to insulate the common voltage line from the pixel electrode. By electrically connecting the common voltage line to each of the adjacent pixel electrodes, a dot defect between the data line and the pixel electrode due to the short-circuit residue is converted into a line defect, thereby facilitating detection of the short-circuit residue.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a manufacturing method thereof.
Background
In the related art, a Dual Gate (Dual Gate) High aperture ratio-advanced super-dimensional field switch (High-Adwanced Dimension Switch, HADS) design structure is currently adopted for a vehicle-mounted product, as shown in fig. 1. The method specifically comprises the following steps: a pixel electrode 101, a data line 102, a common voltage line 103, a gate line 104, and a transistor 105 arranged in an array; wherein, mutual insulation is realized between the pixel electrode 101 and the data line 102 through a gap. The source and drain metal residues (SD Remain) formed during the process of fabricating the data line 102 or the indium tin oxide residues (ITO Remain) formed during the process of fabricating the pixel electrode 101, and these Short residues r easily cause a Short circuit (SD-PXL Short) between the data line 102 and the pixel electrode 101, thereby causing a rear-end lamp bright spot type defect.
Disclosure of Invention
In view of the above, an embodiment of the present invention provides an array substrate and a method for manufacturing the same, which are used for detecting a short-circuit residue such as a source/drain metal residue or an indium tin oxide residue that causes a short-circuit between a data line and a pixel electrode.
Therefore, the manufacturing method of the array substrate provided by the embodiment of the invention comprises the following steps:
Providing a substrate base plate;
Forming a pattern of a plurality of pixel electrodes, a plurality of data lines, a plurality of common voltage lines, and connection portions on the substrate, wherein each of the common voltage lines is electrically connected to adjacent ones of the pixel electrodes through the connection portions;
After loading test signals on each data line, receiving and comparing the test signals transmitted by each data line, determining whether a short-circuit residue exists between at least one data line and the pixel electrode when the test signals transmitted by at least one data line are different from the test signals transmitted by other data lines, and removing the short-circuit residue when the short-circuit residue exists; wherein the number of the at least one data line is smaller than the number of the other data lines;
And etching the connection part to insulate the common voltage lines from the pixel electrodes.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, when forming patterns of a plurality of pixel electrodes on the substrate, the method further includes:
a connection portion connecting each of the common voltage lines with the adjacent pixel electrode is formed.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, patterns of each of the data lines and each of the common voltage lines are formed in the same film layer;
Forming patterns of a plurality of data lines and a plurality of common voltage lines on the substrate base plate, further includes:
a connection portion connecting each of the common voltage lines with the adjacent pixel electrode is formed.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, each pixel electrode is electrically connected to an adjacent common voltage line through at least one corresponding connection portion; or each column of the pixel electrodes is electrically connected with the adjacent common voltage line through a corresponding connection part.
In one possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, a pattern of a plurality of pixel electrodes, a plurality of data lines, and a plurality of common voltage lines is formed on the substrate, and specifically includes:
Forming the pixel electrodes arranged in an array on the substrate;
The data lines and the common voltage lines are alternately formed at column gaps of the pixel electrodes.
In one possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, a pattern of a plurality of pixel electrodes, a plurality of data lines, and a plurality of common voltage lines is formed on the substrate, and specifically includes:
Forming the data lines and the common electrode lines alternately arranged on the substrate base plate;
And forming the pixel electrodes arranged in an array in a region between the data line and the common electrode line.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, after removing the short-circuit residue and before etching the connection portion, the method further includes:
an insulating layer having a via hole formed in a region corresponding to the connection portion;
And forming a common electrode layer on the insulating layer.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, etching the connection portion specifically includes:
and etching the common electrode layer corresponding to the connecting part and the via hole by adopting one-time etching process.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, after forming the common electrode layer on the insulating layer and before etching the connection portion, the method further includes:
And etching the public electrode layer corresponding to the via hole.
In a possible implementation manner, in the above manufacturing method provided by the embodiment of the present invention, after etching the connection portion, the method further includes:
An insulating layer and a common electrode layer are sequentially formed on the substrate.
Based on the same inventive concept, the embodiment of the invention also provides an array substrate, which is prepared by adopting the manufacturing method.
The invention has the following beneficial effects:
The embodiment of the invention provides an array substrate and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate base plate; forming a pattern of a plurality of pixel electrodes, a plurality of data lines, a plurality of common voltage lines, and connection parts on a substrate, wherein each common voltage line is electrically connected to adjacent pixel electrodes through the connection parts; after loading test signals on each data line, receiving and comparing the test signals transmitted by each data line, determining that short-circuit residues exist between at least one data line and the pixel electrode when the test signals transmitted by at least one data line are different from the test signals transmitted by other data lines, and removing the short-circuit residues when the short-circuit residues are determined to exist; wherein the number of the at least one data line is smaller than the number of the other data lines; the connection portions are etched to insulate the common voltage lines from the pixel electrodes. By electrically connecting the common voltage line to each of the adjacent pixel electrodes, a dot defect between the data line and the pixel electrode due to the short-circuit residue can be converted into a line defect, thereby facilitating detection of the short-circuit residue such as the source-drain metal residue or the indium tin oxide residue.
Drawings
FIG. 1 is a schematic diagram of a related art method for detecting short-circuit residues;
FIG. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;
Fig. 3 to fig. 6 are schematic structural diagrams of an array substrate according to an embodiment of the present invention;
fig. 7 to 10 are schematic structural diagrams of the array substrate along II' corresponding to each step in the process of preparing the array substrate by using the manufacturing method shown in fig. 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. "inner", "outer", "upper", "lower", etc. are used merely to denote relative positional relationships, which may also change accordingly when the absolute position of the object to be described changes.
In the related art, a short failure between the data line 102 and the pixel electrode 101 is detected by an Open Short (OS) test apparatus, as shown in fig. 1. The OS test device loads the OS signal on the data line 102 at the transmitting end (i.e., the a end in fig. 1), receives the OS signal transmitted through the data line 102 at the receiving end (i.e., the B end in fig. 1), and performs a corresponding algorithm process on the received OS signal to find out the line with the failure. However, since the pixel electrodes 101 are independent of each other, even if there is a short failure between the data line 102 and the pixel electrode 101 due to a short residue r such as a source-drain metal residue or an indium tin oxide residue, the short failure does not affect the OS signal, and cannot be detected by the OS test device. So that the bright spot defect is detected when the array substrate is detected (ARRAY TEST, AT) later. However, due to the smaller size of the vehicle-mounted product, the pixel electrode 101 is correspondingly smaller, the omission phenomenon is easy to occur, and once the short-circuit residue r is not detected in the AT detection stage, bright spots are formed AT the rear end, so that the user experience is affected. Even if the bright spot defect caused by the short-circuit residue r is detected in the AT detection stage, the defect cannot be maintained because the uppermost layer of the array substrate is the common electrode layer, and even if the laser is used for cutting through the film layer above the data line 102 and the pixel electrode 101, the short-circuit residue r is cut off, and the laser dissolves the common electrode layer to cause a short circuit (DCS) between the data line 102 and the common electrode layer, so that a new defect is caused.
In order to solve the above problems in the related art, an embodiment of the present invention provides an array substrate and a method for manufacturing the same.
The following describes in detail specific embodiments of an array substrate and a method for manufacturing the same according to an embodiment of the present invention with reference to the accompanying drawings. The thickness and shape of the various layers in the drawings are not to scale, and are intended to illustrate the invention.
The method for manufacturing the array substrate provided by the embodiment of the invention, as shown in fig. 2, comprises the following steps:
S201, providing a substrate base plate;
s202, forming a pattern of a plurality of pixel electrodes, a plurality of data lines, a plurality of common voltage lines and connecting parts on a substrate, wherein each common voltage line is electrically connected with each adjacent pixel electrode through the connecting parts;
S203, after loading test signals on each data line, receiving and comparing the test signals transmitted by each data line, determining that short-circuit residues exist between at least one data line and the pixel electrode when the test signals transmitted by at least one data line are different from the test signals transmitted by other data lines, and removing the short-circuit residues when the short-circuit residues are determined to exist; wherein the number of the at least one data line is smaller than the number of the other data lines;
and S204, etching the connection part to insulate each common voltage line and each pixel electrode.
In the above manufacturing method according to the embodiment of the present invention, as shown in fig. 3 to 5, the common voltage line 103 electrically connected to each adjacent pixel electrode 101 is formed in step S202, so that when the short-circuit residue r exists, the test signal (i.e., the OS signal) loaded on the data line 102 in step S203 will be greatly attenuated when reaching the receiving end (i.e., the end B in fig. 3 to 5). The OS test apparatus can easily identify that a few data lines 102 are defective and that a large part of data lines 102 are normal by comparing magnitudes of test signals transmitted by the data lines 102. That is, in the present invention, the short-circuit residue r such as the source/drain metal residue or the indium tin oxide residue is relatively easily detected by converting the dot defect between the data line 102 and the pixel electrode 101 due to the short-circuit residue r into the line defect.
After detecting the existence of the short-circuit residue r, an Automatic Optical Inspection (AOI) device is further adopted to find out specific bad points, so that the short-circuit residue r is positioned, and then laser cutting or other possible modes are adopted to remove the short-circuit residue r. Subsequently, in step S204, the connection portion 106 is etched away to insulate the pixel electrode 101 and the common voltage line 103 from each other, so that the function of the final product is not affected, as shown in fig. 6.
Optionally, in the above manufacturing method provided by the embodiment of the present invention, in order to simplify the manufacturing process and save raw material costs, the following steps may be performed while forming the patterns of the plurality of pixel electrodes on the substrate in step S202:
a connection portion connecting each common voltage line with an adjacent pixel electrode is formed.
That is, the pixel electrode 101 and the connection portion 106 are formed of the same conductive material layer (e.g., ITO), which saves cost and simplifies the process.
Optionally, in the above manufacturing method provided by the embodiment of the present invention, in order to simplify the manufacturing process and save the raw material cost, the patterns of the plurality of data lines 102 and the plurality of common voltage lines 103 are formed on the same film layer;
while the patterning of the plurality of data lines and the plurality of common voltage lines on the substrate base in step S202 is performed, the following steps may be performed:
a connection portion connecting each common voltage line with an adjacent pixel electrode is formed.
That is, the data line 102, the common voltage line 103, and the connection portion 106 are formed using the same conductive material layer (e.g., a metal layer), saving costs and simplifying processes.
It is understood that, in the above-mentioned manufacturing method provided in the embodiment of the present invention, the connection portion 106 may be separately manufactured to achieve the electrical connection between the common voltage line 103 and the adjacent pixel electrode 101.
Alternatively, in the above manufacturing method provided by the embodiment of the present invention, the connection portion 106 may be designed in various manners, for example, each pixel electrode 101 is electrically connected to the adjacent common voltage line 103 through at least one corresponding connection portion 106, as shown in fig. 3 and fig. 4; as another example, each column of pixel electrodes 101 is electrically connected to an adjacent common voltage line 103 through a corresponding connection portion 106, respectively, as shown in fig. 5. In the case where each pixel electrode 101 is electrically connected to the adjacent common voltage line 103 through a corresponding connection portion 106, as shown in fig. 3, each connection portion 106 may be provided so as to achieve the effect of electrically connecting the common voltage line 103 to the adjacent two pixel electrodes 101, and the connection portion 106 may be designed in size according to the actual product, for example, the connection portion 106 may have a length of 12.5 μm in the extending direction of the gate line 104 and a width of 3.5 μm in the extending direction of the common voltage line 103.
Alternatively, in the above manufacturing method provided by the embodiment of the present invention, step S202 forms patterns of a plurality of pixel electrodes, a plurality of data lines, and a plurality of common voltage lines on a substrate, which may be specifically implemented by the following two ways:
After forming pixel electrodes arranged in an array on a substrate, data lines and common voltage lines are alternately formed at column gaps of the respective pixel electrodes.
Or after forming the data lines and the common electrode lines alternately arranged on the substrate, forming pixel electrodes arranged in an array in a region between the data lines and the common electrode lines.
Generally, after step S204 in the above-mentioned manufacturing method provided by the embodiment of the present invention is performed, the structure of the obtained array substrate is shown in fig. 6. The transistor 105 may be a top gate transistor or a bottom gate transistor, and includes an active layer, a gate insulating layer 107 (shown in fig. 6), a gate electrode, an interlayer dielectric layer, and a source/drain electrode on the substrate 100 (shown in fig. 6).
Alternatively, in the above-mentioned manufacturing method provided by the embodiment of the present invention, in the case where the connection portion 106 and the pixel electrode 101 are manufactured using the same conductive layer 101' (as shown in fig. 7 to 10), after performing step S203 to remove the short-circuit residue, and before performing step S204 to etch the connection portion, the following steps may be further performed:
coating an insulating layer 108 on the array substrate obtained in step S203, as shown in fig. 7;
Forming a via hole in the insulating layer 108 in a region corresponding to the connection portion 106, as shown in fig. 8;
A common electrode layer 109 is formed on the insulating layer 108 as shown in fig. 9.
Accordingly, the step S204 of etching the connection portion may specifically include:
And etching the common electrode layer corresponding to the connecting part and the via hole by adopting a one-time etching process.
That is, in the case where the material of the connection portion 106 is the same as that of the common electrode layer 109, in order to simplify the process flow, a single etching process may be used to etch the common electrode layer 109 corresponding to the connection portion 106 and the via hole, as shown in fig. 10.
Alternatively, in the above manufacturing method provided by the embodiment of the present invention, in the case where the connection portion 106, the data line 102, and the common voltage line 103 are manufactured by using the same film layer, after the step of forming the common electrode layer on the insulating layer is performed, and before the step of etching the connection portion is performed in step S204, the method may further include:
and etching the public electrode layer corresponding to the via hole.
That is, when the material of the connection portion 106 is different from that of the common electrode layer 109, for example, the material of the connection portion 106 is metal, the material of the common electrode layer 109 is a transparent conductive material such as ITO, and a first etching process is required to etch the common electrode layer 109 corresponding to the via hole so as to expose the connection portion 106; then, the connection portion 106 is etched by a second etching process to insulate the common voltage line 103 from the pixel electrode 101.
It is to be understood that in the above manufacturing method provided in the embodiment of the present invention, the shape of the via hole formed after etching the connection portion 106 may have any regular or irregular pattern, such as a circle, an ellipse, a triangle, a square, a rectangle, a diamond, a trapezoid, a pentagonal star, a regular polygon, etc., which is not limited herein. The via size is sufficient that the connection portion 106 along the common voltage line 103 can be entirely etched to achieve a blocking effect, for example, the width of the via between one pixel electrode 101 and the common voltage line 103 in the extending direction of the gate line 104 is 4 μm and the length in the extending direction of the common voltage line 103 is 5.5 μm.
Optionally, in the above manufacturing method provided by the embodiment of the present invention, after performing step S204 to etch the connection portion, the following steps may be further performed:
An insulating layer and a common electrode layer are sequentially formed on a substrate.
As can be seen from the above description, in the above-mentioned manufacturing method provided by the embodiment of the present invention, after the short-circuit residue r is detected and removed, the insulating layer 108 and the common electrode layer 109 having the via hole in the region corresponding to the connection portion 106 may be manufactured first, and then the connection portion 106 is etched to realize the insulation between the data line 102 and the pixel electrode 101; the wiring 106 may be etched to insulate the data line 102 from the pixel electrode 101, and then the insulating layer 108 and the common electrode layer 109 may be prepared by using a conventional manufacturing process.
In the above manufacturing method provided by the embodiment of the present invention, the patterning process involved in forming each layer of structure may include not only a part or all of the process procedures of deposition, photoresist coating, mask masking, exposure, development, etching, photoresist stripping, and the like, but also other process procedures, specifically, the process of forming a pattern of a desired pattern in an actual manufacturing process is not limited herein. For example, a post bake process may also be included after development and before etching.
The deposition process may be a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or a physical vapor deposition method, which is not limited herein; the Mask used in the Mask process may be a Half Tone Mask (Half Tone Mask), a single slit diffraction Mask (SINGLE SLIT MASK) or a Gray Tone Mask (Gray Tone Mask), which are not limited herein; the etching may be dry etching or wet etching, and is not limited herein.
Based on the same inventive concept, the embodiment of the invention also provides an array substrate, which is prepared by adopting the manufacturing method. Because the principle of solving the problem of the array substrate is similar to that of the above-mentioned manufacturing method, the implementation of the array substrate provided by the embodiment of the present invention can refer to the implementation of the above-mentioned manufacturing method provided by the embodiment of the present invention, and the repetition is omitted.
In the array substrate and the manufacturing method thereof provided by the embodiment of the invention, by forming the common voltage line electrically connected with each adjacent pixel electrode, when short-circuit residues exist, a test signal (i.e. an OS signal) loaded on a data line can be greatly attenuated when reaching a receiving end, namely, point defects between the data line and the pixel electrode caused by the short-circuit residues are converted into line defects, so that the short-circuit residues such as source-drain metal residues or indium tin oxide residues are relatively easy to detect.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (9)
1. The manufacturing method of the array substrate is characterized by comprising the following steps of:
Providing a substrate base plate;
Forming a pattern of a plurality of pixel electrodes, a plurality of data lines, a plurality of common voltage lines, and connection portions on the substrate, wherein each of the common voltage lines is electrically connected to adjacent ones of the pixel electrodes through the connection portions;
After loading test signals on each data line, receiving and comparing the test signals transmitted by each data line, determining that a short-circuit residue exists between at least one data line and the pixel electrode when the test signals transmitted by at least one data line are different from the test signals transmitted by other data lines, and removing the short-circuit residue when the short-circuit residue is determined to exist; wherein the number of the at least one data line is smaller than the number of the other data lines;
Etching the connection part to insulate the common voltage lines from the pixel electrodes;
forming patterns of a plurality of pixel electrodes on the substrate base plate, and simultaneously, further comprising: forming the connection part connecting each of the common voltage lines with the adjacent pixel electrode;
Or the patterns of each data line and each common voltage line are formed in the same film layer; forming patterns of a plurality of data lines and a plurality of common voltage lines on the substrate base plate, further includes: the connection portion connecting each of the common voltage lines with the adjacent pixel electrode is formed.
2. The method of manufacturing as set forth in claim 1, wherein each of the pixel electrodes is electrically connected to the adjacent common voltage line through at least one corresponding connection portion, respectively; or each column of the pixel electrodes is electrically connected with the adjacent common voltage line through a corresponding connection part.
3. The method of manufacturing of claim 1, wherein forming a pattern of a plurality of pixel electrodes, a plurality of data lines, and a plurality of common voltage lines on the substrate base plate, specifically comprises:
Forming the pixel electrodes arranged in an array on the substrate;
The data lines and the common voltage lines are alternately formed at column gaps of the pixel electrodes.
4. The method of manufacturing of claim 1, wherein forming a pattern of a plurality of pixel electrodes, a plurality of data lines, and a plurality of common voltage lines on the substrate base plate, specifically comprises:
Forming the data lines and the common electrode lines alternately arranged on the substrate base plate;
And forming the pixel electrodes arranged in an array in a region between the data line and the common electrode line.
5. The method of manufacturing of claim 1, further comprising, after removing the short residue and before etching the connection portion:
an insulating layer having a via hole formed in a region corresponding to the connection portion;
And forming a common electrode layer on the insulating layer.
6. The method of manufacturing as claimed in claim 5, wherein etching the connection portion specifically includes:
and etching the common electrode layer corresponding to the connecting part and the via hole by adopting one-time etching process.
7. The method of manufacturing of claim 5, further comprising, after forming a common electrode layer on the insulating layer and before etching the connection portion:
And etching the public electrode layer corresponding to the via hole.
8. The method of manufacturing of claim 1, further comprising, after etching the connection portion:
An insulating layer and a common electrode layer are sequentially formed on the substrate.
9. An array substrate, wherein the array substrate is prepared by the manufacturing method according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911158931.3A CN112838059B (en) | 2019-11-22 | 2019-11-22 | Array substrate and manufacturing method thereof |
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| CN109036236B (en) * | 2018-09-14 | 2021-10-26 | 京东方科技集团股份有限公司 | Array substrate detection method and detection device |
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| CN205282049U (en) * | 2016-01-04 | 2016-06-01 | 京东方科技集团股份有限公司 | Array substrate and display device |
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