CN112838019A - 用于晶圆键合的对准检测方法 - Google Patents
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- 238000012360 testing method Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 6
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- 238000003384 imaging method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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- H01L27/144—Devices controlled by radiation
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
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Abstract
本发明提供一种用于晶圆键合的对准检测方法,通过分别将每片晶圆的光掩膜检测数据转换为图形数据流数据,将键合后的晶圆的图形数据流数据进行层叠,观察待检测位置的图形数据流数据是否有不一致的地方,从而判断晶圆能否对准,提高了光掩膜检测数据对准检测的效率和准确性。
Description
技术领域
本发明涉及一种用于晶圆键合的对准检测方法。
背景技术
随着半导体技术的不断发展,3D-IC(三维集成电路)技术得到了广泛的应用,其是利用晶圆级封装技术将不同的晶圆堆叠键合在一起,该技术具有高性能、低成本且高集成度的优点。
3D堆叠技术正成为高端应用和成像应用的新标准,例如3维堆栈式CMOS图像传感器(3D-StackCIS)被开发出来,以支持对更高质量影像的需求。具体而言,3D-Stack CIS可以对逻辑晶圆以及像素晶圆分别进行制作,进而将所述逻辑晶圆的正面以及所述像素晶圆的正面键合,由于像素部分和逻辑电路部分相互独立,因此可针对高画质的需求对像素部分进行优化,针对高性能的需求对逻辑电路部分进行优化。
然而,在晶圆键合过程中,两片晶圆的互连需要精确对准,若出现对准的偏移,会导致键合后器件连接的偏移,进而影响产品的良率及性能。因此,生产过程中,需要对两片晶圆进行对准检测。由于用于键合的两片晶圆可能出自不同集成电路生产厂商(fab),它们制造过程中的光掩膜检测数据(JDV,Job Deck View)无法层叠在一起做数据检查,只能通过分别观察两片晶圆上的JDV数据进行对比,耗费大量的人力和时间成本,导致对准检测的效率和准确性都较低。
发明内容
本发明的目的在于提供一种用于晶圆键合的对准检测方法,提高对准检测的效率和准确性。
基于以上考虑,本发明提供一种用于晶圆键合的对准检测方法,分别将每片晶圆的光掩膜检测数据转换为图形数据流数据;将键合后的晶圆的图形数据流数据进行层叠,观察待检测位置的图形数据流数据是否有不一致的地方,从而判断晶圆能否对准。
优选的,所述待检测位置包括主芯片,划片槽测试结构,对准标记。
优选的,所述晶圆对准的最小精度为0.1μm。
优选的,所述晶圆通过混合键合技术进行键合。
优选的,所述晶圆正面相对进行键合。
优选的,所述晶圆以及光掩膜检测数据由不同的集成电路生产厂商提供。
本发明的用于晶圆键合的对准检测方法,通过分别将每片晶圆的光掩膜检测数据转换为图形数据流数据,将键合后的晶圆的图形数据流数据进行层叠,观察待检测位置的图形数据流数据是否有不一致的地方,从而判断晶圆能否对准,提高了对准检测的效率和准确性。
具体实施方式
为解决上述现有技术中的问题,本发明提供一种用于晶圆键合的对准检测方法,通过分别将每片晶圆的光掩膜检测数据转换为图形数据流数据,将键合后的晶圆的图形数据流数据进行层叠,观察待检测位置的图形数据流数据是否有不一致的地方,从而判断晶圆能否对准,提高了对准检测的效率和准确性。
示例的实施例并不旨在穷尽根据本发明的所有实施例。可以理解,在不偏离本发明的范围的前提下,可以利用其他实施例,也可以进行结构性或者逻辑性的修改。因此,以下的具体描述并非限制性的,且本发明的范围由所附的权利要求所限定。
下面结合具体实施例对本发明进行详细阐述。
本发明提供一种用于晶圆键合的对准检测方法。目前,集成电路生产厂商一般都是根据设计公司提供的版图文件来制造相应的集成电路产品,所述版图文件通常被设计公司以图形数据流数据(GDS,Graphic Data Stream)的文件格式提供给集成电路生产厂商,不同的集成电路生产厂商分别从GDS数据中提取相应的版图数据,形成版图结构,制造光掩模并各自生成JDV数据,因此,当用于键合的晶圆由不同的集成电路生产厂商提供时,它们的JDV数据无法兼容层叠。但是因为,每片晶圆的JDV数据都可以转换为GDS数据,并且它们转化后的GDS数据是通用的,因此只需将键合后的晶圆的GDS数据进行层叠,即可方便地观察待检测位置(例如主芯片,划片槽测试结构,对准标记)的GDS数据是否有不一致的地方,从而判断晶圆能否对准。优选的,所述晶圆对准的最小精度为0.1μm。该方法节省了大量的人力和时间成本,提高了对准检测的效率和准确性。
优选的,所述晶圆可以通过混合键合技术进行键合。混合键合技术包含直接堆叠的两片晶圆,这些晶圆具有平面绝缘表面和隔离的金属互联,彼此正面相对进行键合。混合键合技术已经在CMOS图像传感器(CIS)中取代了硅通孔(TSV)互联,在该应用中实现了占用面积小,成本低等优点,因此被广泛用于高端便携电子设备的CIS制造。
综上所示,本发明的用于晶圆键合的对准检测方法,通过分别将每片晶圆的光掩膜检测数据转换为图形数据流数据,将键合后的晶圆的图形数据流数据进行层叠,观察待检测位置的图形数据流数据是否有不一致的地方,从而判断晶圆能否对准,提高了对准检测的效率和准确性,改善了产品的良率及性能。
对于本领域技术人员而言,显然本发明不限于上述示范性实施例的细节,而且在不背离本发明的精神或基本特征的情况下,能够以其他的具体形式实现本发明。因此,无论如何来看,均应将实施例看作是示范性的,而且是非限制性的。此外,明显的,“包括”一词不排除其他元素和步骤,并且措辞“一个”不排除复数。装置权利要求中陈述的多个元件也可以由一个元件来实现。第一,第二等词语用来表示名称,而并不表示任何特定的顺序。
Claims (6)
1.一种用于晶圆键合的对准检测方法,其特征在于,
分别将每片晶圆的光掩膜检测数据转换为图形数据流数据;
将键合后的晶圆的图形数据流数据进行层叠,观察待检测位置的图形数据流数据是否有不一致的地方,从而判断晶圆能否对准。
2.如权利要求1所述的用于晶圆键合的对准检测方法,其特征在于,所述待检测位置包括主芯片,划片槽测试结构,对准标记。
3.如权利要求1所述的用于晶圆键合的对准检测方法,其特征在于,所述晶圆对准的最小精度为0.1μm。
4.如权利要求1所述的用于晶圆键合的对准检测方法,其特征在于,所述晶圆通过混合键合技术进行键合。
5.如权利要求1所述的用于晶圆键合的对准检测方法,其特征在于,所述晶圆正面相对进行键合。
6.如权利要求1所述的用于晶圆键合的对准检测方法,其特征在于,所述晶圆以及光掩膜检测数据由不同的集成电路生产厂商提供。
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