CN112821755A - Power regulation method and system for power management chip adaptive load - Google Patents
Power regulation method and system for power management chip adaptive load Download PDFInfo
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- CN112821755A CN112821755A CN202110150407.2A CN202110150407A CN112821755A CN 112821755 A CN112821755 A CN 112821755A CN 202110150407 A CN202110150407 A CN 202110150407A CN 112821755 A CN112821755 A CN 112821755A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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Abstract
The invention belongs to the field of power regulation of power management chips, and particularly relates to a power regulation method and system for a power management chip adaptive load. The method provided by the invention comprises the following steps: s1, grouping power tubes in a power management chip; s2, detecting the power required by the load in real time; s3, starting the grouped power tubes according to the load size; the system comprises a power management chip, a sampling module, a selection module and a control signal module; the sampling module is connected with the FB end of the power management chip; the selection module is respectively connected with the sampling module, the control signal module and the power tube in the power management chip. The invention can realize the automatic adjustment of the output power of the power management chip according to different loads; therefore, the power regulation of the power management chip self-adaptive load can be completed, and the power management chip can output the power required by the load at the current moment in real time.
Description
Technical Field
The invention belongs to the field of power regulation of power management chips, and particularly relates to a power regulation method and system for a power management chip adaptive load.
Background
When a power management chip is used, an energy management center in an electronic device system is responsible for distribution of power to the chip or an output power source, voltage conversion, detection, battery protection and the like. The power management chip is an important support for power consumption performance of the electronic system, good power management can greatly reduce the power consumption of the electronic equipment, the cruising ability of the battery is increased, and user experience is improved. At the same time, good power management can enhance the performance index of the electronic device. The existing electronic system is more and more complex, and the requirement on a power management chip is higher and higher.
Most of traditional power regulation methods for power management chips are based on a software level, and load data obtained by sampling is analyzed through a program preset in an MCU (microprogrammed control unit), so that the power of the power management chip is regulated.
Disclosure of Invention
The invention aims to solve the problems that: the power adjustment method and the power adjustment system for the power management chip self-adaptive load can adjust the power of the power management chip in real time according to different loads, and achieve power adjustment of the power management chip self-adaptive load.
The technical scheme adopted by the invention is as follows:
a power regulation method of a power management chip self-adaptive load comprises the following steps:
s1, grouping power tubes in a power management chip;
s2, detecting the power required by the load in real time;
s3, starting the grouped power tubes according to the load size;
further, the grouping mode of the power tubes in the power management chip is as follows: any one of an average grouping, an uneven grouping and an index grouping.
The invention also provides a power regulating system of the power management chip self-adaptive load, which comprises a power management chip; the device comprises a sampling module, a selection module and a control signal module; the sampling module is connected with the FB end of the power management chip; the selection module is respectively connected with the sampling module, the control signal module and the power tube in the power management chip.
Furthermore, the control signal module comprises a frequency dividing circuit, and the clock signal passes through the frequency dividing circuit and outputs a plurality of control signals.
Further, the sampling module comprises a voltage division circuit and a comparator; each different voltage node of the voltage division circuit is respectively connected with the negative input end of the comparator; the positive input end of the comparator is connected with a reference voltage; the output end of the comparator outputs a selection signal; the reference voltage is generated by a reference voltage circuit.
Further, the selection module comprises an AND gate and a NOR gate; the AND gate is used for identifying the control signal and selecting a power tube driving signal corresponding to the control signal; or they are used to transmit control signals.
Further, the sampling module may include a first resistor, a second resistor, a third resistor, a first comparator, a second comparator, a first selection signal, a second selection signal, and a reference voltage; the end of the chip is connected with the first resistor; the other end of the first resistor is connected with a second resistor, the other end of the second resistor is connected with a third resistor, and the other end of the third resistor is grounded; the negative input end of the first comparator is connected with a node formed by the first resistor and the second resistor; the negative input end of the second comparator is connected with a node formed by the second resistor and the third resistor; the reference voltage is respectively input into the positive input ends of the first comparator and the second comparator; the output end of the first comparator outputs a first selection signal, and the output end of the second comparator outputs a second selection signal.
Further, the reference voltage may be 1.2V to 2.4V, and may be generated by a reference voltage circuit.
Further, the selection module may include: the first logic gate, the second logic gate, the third logic gate, the fourth logic gate and the fifth logic gate; the first logic gate, the second logic gate, the third logic gate and the fourth logic gate are all AND gates, and the fifth logic gate is a NOR gate; the first control signal is input into the input end of the first logic gate, the second control signal is input into the input end of the second logic gate, the third control signal is input into the input end of the third logic gate, and the fourth control signal is input into the input end of the fourth logic gate; the first selection signal is respectively input into the input ends of the second logic gate and the fourth logic gate, and the first selection signal is respectively input into the input ends of the first logic gate and the third logic gate through the phase inverter; the second selection signal is respectively input into the input ends of the third logic gate and the fourth logic gate, and the second selection signal is input into the input ends of the first logic gate and the second logic gate through the phase inverter; the output ends of the first logic gate, the second logic gate, the third logic gate and the fourth logic gate are all connected with the input end of the fifth logic gate; and the output end of the fifth logic gate is connected with a power tube on the chip through an inverter.
Further, the control signal module may include a frequency dividing circuit through which the clock signal passes to generate the first control signal, the second control signal, the third control signal, and the fourth control signal.
The invention has the beneficial effects that: the power regulation method of the power management chip self-adaptive load is provided, and based on the method, the output power of the power management chip can be automatically regulated according to different load sizes; the sampling circuit is used for detecting different voltage signals corresponding to different loads so as to select control signals required by power tubes in the power management chip under different load conditions, and the selection module is used for selecting different power tube control signals according to the control signals given by the sampling circuit; therefore, the power regulation of the power management chip self-adaptive load can be realized, and the power management chip can output the power required by the load in real time.
Drawings
FIG. 1 is a flow chart of a power regulation method for a power management chip adaptive load according to the present invention;
FIG. 2 is a block diagram of a power management chip adaptive load power regulation system according to the present invention;
FIG. 3 is a circuit diagram of a power management chip adaptive load power regulation system sampling module according to the present invention;
FIG. 4 is a circuit diagram of a power management chip adaptive load power regulation system selection module according to the present invention;
fig. 5 is a circuit diagram of a power management chip adaptive load power regulation system control signal module according to the present invention.
The labels in the figure are: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a VREF reference voltage, a Vsel1 first selection signal, a Vsel2 second selection signal, a D1 first comparator, a D2 second comparator, a T1 first control signal, a T2 second control signal, a T3 third control signal, a T4 fourth control signal, a K1 first logic gate, a K2 second logic gate, a K3 third logic gate, a K4 fourth logic gate, a K5 fifth logic gate, a CK clock terminal, a D enable terminal, a Q output terminal and a QB inverting output terminal.
Detailed Description
The invention is further described with reference to the accompanying drawings and the detailed description.
Example 1
The embodiment provides a power regulation method for a power management chip adaptive load, which comprises the following steps:
s1, grouping power tubes in a power management chip;
s2, detecting the power required by the load in real time;
s3, starting the grouped power tubes according to the load size;
example 2
The power tube grouping method in embodiment 1 may be any one of an average grouping, an uneven grouping and an exponential grouping.
For example, the total number of the power tubes is 100, and the average grouping makes the number of each group of power tubes equal; dividing into two groups of 50, and dividing into four groups of 25, etc.; this grouping situation applies to situations where the load size varies linearly.
For example, the total number of power tubes is 100, and the uneven grouping may be divided into a first group of 30 power tubes, a second group of 30 power tubes, a third group of 30 power tubes, a fourth group of 10 power tubes, etc. according to the experience of the designer. The method is suitable for the condition of uneven load change.
For example, the total number of power tubes is 85, and the index grouping makes the number of power tubes in the next group be multiple of the number of power tubes in the previous group. Such as a first set of 1, a second set of 4, a third set of 16, and a fourth set of 64. This grouping situation applies to situations where the load changes drastically.
Example 3
The embodiment provides a power regulation system of a power management chip adaptive load, which comprises: the device comprises a power management chip, a sampling module, a selection module and a control signal module; the sampling module is connected with the FB end of the power management chip; the selection module is respectively connected with the sampling module, the control signal module and the power tube in the power management chip.
And the control signal module comprises a frequency division circuit, and the clock signal passes through the frequency division circuit and outputs a plurality of control signals.
Meanwhile, the sampling module comprises a voltage division circuit and a comparator; each different voltage node of the voltage division circuit is respectively connected with the negative input end of the comparator; the positive input end of the comparator is connected with a reference Voltage (VREF); the output end of the comparator outputs a selection signal; the reference Voltage (VREF) is generated by a reference voltage circuit.
Furthermore, the selection module comprises an AND gate and a NOR gate; the AND gate is used for identifying the control signal and selecting the power tube driving signal corresponding to the control signal; the nor is used to convey the control signal.
When the power supply management circuit is used, the FB end of the power supply management chip can reflect the load condition of the current power supply at the port in a voltage mode, the sampling module detects the load condition in real time by collecting voltage data of the FB port, and different selection signals are output according to the real-time load size; the control signal module is used for generating a driving signal for adjusting power and controlling a power tube positioned on the power management chip; the selection module makes a selection according to the selection signal given by the adoption module, selects a power tube control signal suitable for the current load, and outputs and controls the power tube on the power management chip.
In order to adapt to different load requirements and control accuracy, the power tubes in the power management chip can be grouped, and meanwhile, the control signal module also generates different numbers of power tube control signals corresponding to different power tube groups. The sampling module can sample the FB terminal voltage of the power management chip reflecting the load degree with different accuracies, and the sampling result is reflected through binary number so as to adapt to the load control requirements with different accuracies; such as: dividing the resistance into 2-bit binary number by three resistors, dividing the resistance into 3-bit binary number by four resistors, dividing the resistance into 4-bit binary number by five resistors and the like; meanwhile, the selection module can also select the power tube control signal corresponding to the selection signals of different digit binary numbers output by the sampling module.
Example 4
Further, the sampling module includes a first resistor R1, a second resistor R2, a third resistor R3, a first comparator D1, a second comparator D2, a first selection signal Vsel1, a second selection signal Vsel2, and a reference voltage VREF; the FB end of the chip is connected with a first resistor R1; the other end of the first resistor is connected with a second resistor R2, the other end of the second resistor R2 is connected with a third resistor R3, and the other end of the third resistor R3 is grounded; the negative input end of the first comparator D1 is connected with a node formed by a first resistor R1 and a second resistor R2; the negative input end of the second comparator D2 is connected with a node formed by the second resistor R2 and the third resistor R3; the reference voltage VREF is respectively input into positive input ends of a first comparator D1 and a second comparator D2; the output terminal of the first comparator D1 outputs a first selection signal Vsel1, and the output terminal of the second comparator D2 outputs a second selection signal Vsel 2.
The voltage signal which is output by the FB end of the power management chip and reflects the weight of the load is divided by a first resistor R1, a second resistor R2 and a third resistor R3, and then the voltage signal is respectively compared with a reference voltage VREF through a comparator to judge the size of the load; a first selection signal Vsel1 and a second selection signal Vsel2 are given simultaneously, which may reflect the current load size.
When the voltage at the negative input terminal of the first comparator D1 is greater than the reference voltage VREF at the positive input terminal, the output of the first selection signal Vsel1 is "0", and when the voltage at the negative input terminal of the second comparator D2 is greater than the reference voltage VREF at the positive input terminal, the output of the second selection signal Vsel2 is "0", which corresponds to an operating state of the power transistor.
Further, the reference voltage VREF is 1.2V to 2.4V and is generated by a reference voltage circuit.
The reference voltage is used for comparing with a voltage signal which can reflect the load in the sampling circuit, so that a selection signal which can reflect the current load size is obtained.
Further, the selection module comprises: a first logic gate K1, a second logic gate K2, a third logic gate K3, a fourth logic gate K4, and a fifth logic gate K5; the first logic gate K1, the second logic gate K2, the third logic gate K3 and the fourth logic gate K4 are all AND gates, and the fifth logic gate K5 is a NOR gate; the first control signal T1 is input to an input of a first logic gate K1, the second control signal T2 is input to an input of a second logic gate K2, the third control signal T3 is input to an input of a third logic gate K3, and the fourth control signal T4 is input to an input of a fourth logic gate K4; the first selection signal Vsel1 is inputted to the input terminals of the second logic gate K2 and the fourth logic gate K4, respectively, and the first selection signal Vsel1 is inputted to the input terminals of the first logic gate K1 and the third logic gate K3 through the inverter, respectively; the second selection signal Vsel2 is inputted to the input terminals of the third logic gate K3 and the fourth logic gate K4, respectively, and the second selection signal Vsel2 is inputted to the input terminals of the first logic gate K1 and the second logic gate K2 through the inverter; the output ends of the first logic gate K1, the second logic gate K2, the third logic gate K3 and the fourth logic gate K4 are all connected with the input end of the fifth logic gate K5; the output terminal of the fifth logic gate K5 is connected to the power transistor on the chip through an inverter.
The selection module can select different power tube driving signals through different selection signals, and the different power tube driving signals control different types of power tube working modes; if the first selection signal Vsel1 is "1" and the second selection signal Vsel2 is "1", the selection module selects the power transistor to which the fourth control signal T4 is transmitted, so as to control the power transistors of the chip to be turned on in different operating states.
Further, the control signal module includes a frequency dividing circuit, through which the clock signal passes to generate a first control signal T1, a second control signal T2, a third control signal T3 and a fourth control signal T4; the frequency dividing circuit comprises four flip-flops which are connected in sequence, a clock signal is connected with a clock end CK of a first flip-flop, an enable end D of the first flip-flop is connected with a reverse output end QB and is connected with the clock end CK of a next flip-flop, and output ends B of the four flip-flops output a first control signal T1, a second control signal T2, a third control signal T3 and a fourth control signal T4 in sequence.
Different control signals correspond to different power tube opening schemes in the power management chip, so that the output power of the power management chip is changed, and the power required by the load is provided in real time.
Claims (10)
1. A power regulation method of a power management chip self-adaptive load is characterized by comprising the following steps:
s1, grouping power tubes in a power management chip;
s2, detecting the power required by the load in real time;
and S3, opening the grouped power tubes according to the load size.
2. The method according to claim 1, wherein the power management chips are grouped into the following power management chips: any one of an average grouping, an uneven grouping and an index grouping.
3. A power regulation system of a power management chip self-adaptive load comprises a power management chip; it is characterized by comprising: the device comprises a sampling module, a selection module and a control signal module;
the sampling module is used for collecting voltage data of the FB port and outputting different selection signals; the control signal module is used for generating a driving signal for controlling a power tube of the power management chip; the selection module is used for selecting different driving signals according to the result of the selection signal;
the sampling module is connected with the FB end of the power management chip; the selection module is respectively connected with the sampling module, the control signal module and the power tube in the power management chip.
4. The power management chip adaptive load power regulation system of claim 3, wherein the control signal module comprises a frequency divider circuit, and the frequency divider circuit is configured to process the clock signal and output a plurality of control signals.
5. The power management chip adaptive load power regulation system of claim 3, wherein the sampling module comprises a voltage divider circuit and a comparator; each different voltage node of the voltage division circuit is respectively connected with the negative input end of the comparator; the positive input end of the comparator is connected with a reference Voltage (VREF); the output end of the comparator outputs a selection signal; the reference Voltage (VREF) is generated by a reference voltage circuit.
6. The power management chip adaptive load power regulation system of claim 3, wherein the selection module comprises an AND gate and a NOR gate; the AND gate is used for identifying the control signal and selecting the power tube driving signal corresponding to the control signal; the nor is used to convey the control signal.
7. The power management chip adaptive load power regulation system of claim 5, wherein the sampling module comprises a first resistor (R1), a second resistor (R2), a third resistor (R3), a first comparator (D1), a second comparator (D2), a first select signal (Vsel1), a second select signal (Vsel2), and a reference Voltage (VREF); the FB end of the chip is connected with a first resistor (R1); the other end of the first resistor is connected with a second resistor (R2), the other end of the second resistor (R2) is connected with a third resistor (R3), and the other end of the third resistor (R3) is grounded; the negative input end of the first comparator (D1) is connected with a node formed by a first resistor (R1) and a second resistor (R2); the negative input end of the second comparator (D2) is connected with a node formed by the second resistor (R2) and the third resistor (R3); the reference Voltage (VREF) is respectively input into the positive input ends of the first comparator (D1) and the second comparator (D2); the output of the first comparator (D1) outputs a first select signal (Vsel1), and the output of the second comparator (D2) outputs a second select signal (Vsel 2).
8. The power management chip adaptive load power regulation system of claim 6, wherein the control signal block comprises a frequency divider circuit, the clock signal generates the first control signal (T1), the second control signal (T2), the third control signal (T3) and the fourth control signal (T4) via the frequency divider circuit; the frequency division circuit comprises four sequentially connected flip-flops, a clock end (CK) of a first flip-flop is connected with a clock signal, an enable end (D) of the first flip-flop is connected with a reverse output end (QB) and is connected with the clock end (CK) of a next flip-flop, and output ends (B) of the four flip-flops sequentially output a first control signal (T1), a second control signal (T2), a third control signal (T3) and a fourth control signal (T4).
9. The power management chip adaptive-load power regulation system of claim 5, wherein the reference Voltage (VREF) is 1.2V.
10. The power management chip adaptive-load power regulation system of claim 8, wherein the selection module comprises: a first logic gate (K1), a second logic gate (K2), a third logic gate (K3), a fourth logic gate (K4), a fifth logic gate (K5); the first logic gate (K1), the second logic gate (K2), the third logic gate (K3) and the fourth logic gate (K4) are all AND gates, and the fifth logic gate (K5) is a NOR gate; a first control signal (T1) is input to an input of the first logic gate (K1), a second control signal (T2) is input to an input of the second logic gate (K2), a third control signal (T3) is input to an input of the third logic gate (K3), and a fourth control signal (T4) is input to an input of the fourth logic gate (K4); the first selection signal (Vsel1) is respectively input to the input terminals of the second logic gate (K2) and the fourth logic gate (K4), and the first selection signal (Vsel1) is respectively input to the input terminals of the first logic gate (K1) and the third logic gate (K3) through an inverter; a second selection signal (Vsel2) is respectively input to the input terminals of the third logic gate (K3) and the fourth logic gate (K4), and the second selection signal (Vsel2) is input to the input terminals of the first logic gate (K1) and the second logic gate (K2) through an inverter; the output ends of the first logic gate (K1), the second logic gate (K2), the third logic gate (K3) and the fourth logic gate (K4) are all connected with the input end of the fifth logic gate (K5); the output end of the fifth logic gate (K5) is connected with a power tube on the chip through an inverter.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115635851A (en) * | 2022-10-31 | 2023-01-24 | 重庆长安新能源汽车科技有限公司 | Vehicle-mounted intelligent power distribution system, control method and storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115635851A (en) * | 2022-10-31 | 2023-01-24 | 重庆长安新能源汽车科技有限公司 | Vehicle-mounted intelligent power distribution system, control method and storage medium |
| CN115635851B (en) * | 2022-10-31 | 2024-06-04 | 深蓝汽车科技有限公司 | Vehicle-mounted intelligent power distribution system, control method and storage medium |
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