CN112820778A - Novel high-voltage VDMOS device and preparation method thereof - Google Patents
Novel high-voltage VDMOS device and preparation method thereof Download PDFInfo
- Publication number
- CN112820778A CN112820778A CN202110336336.5A CN202110336336A CN112820778A CN 112820778 A CN112820778 A CN 112820778A CN 202110336336 A CN202110336336 A CN 202110336336A CN 112820778 A CN112820778 A CN 112820778A
- Authority
- CN
- China
- Prior art keywords
- heavily doped
- region
- type
- type heavily
- source region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims description 39
- 239000011248 coating agent Substances 0.000 claims description 21
- 238000000576 coating method Methods 0.000 claims description 21
- 238000005468 ion implantation Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000003698 laser cutting Methods 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims 1
- 230000005855 radiation Effects 0.000 description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- -1 aluminum ion Chemical class 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a novel high-voltage VDMOS device and a preparation method thereof, wherein the preparation method comprises the following steps: the transistor comprises an N-type heavily doped substrate, an N-type lightly doped buffer region, a P-type well region, an N-type heavily doped source region, a P-type heavily doped source region, a NISI source region, a high-K insulating layer, a gate polysilicon region, a NISI drain region, a gate electrode, a source electrode and a drain electrode; the NISI drain electrode region is arranged on the lower surface of the N-type heavily doped substrate, a drain electrode is formed on the lower surface of the NISI drain electrode region, an N-type lightly doped buffer region is arranged on the N-type heavily doped substrate, two P-type well regions are arranged on the N-type lightly doped buffer region, an N-type heavily doped source region and a P-type heavily doped source region are arranged on the P-type well region, NISI source regions are arranged on the upper surfaces of the N-type heavily doped source region and the P-type heavily doped source region, high-K insulating layers are arranged on the P-type well regions and the N-type lightly doped buffer region, a grid polycrystalline silicon region is arranged on the high-K insulating layers, a grid.
Description
Technical Field
The invention relates to the technical field of semiconductor power, in particular to a novel high-voltage VDMOS device and a preparation method thereof.
Background
The VDMOS device is an electronic switch, the switching state of which is controlled by the gate voltage, and the conduction is performed by electrons or holes when the VDMOS device is turned on, and the VDMOS device has the advantages of simple control and fast switching, and thus is widely applied to power electronic systems, mainly including a switching power supply, a motor drive, and the like. The threshold voltage and the specific on-resistance are two main parameters of the power VDMOS, wherein the specific on-resistance of the power VDMOS also increases sharply with the increase of the threshold voltage of the power device, and the specific on-resistance is more obvious for the high-voltage VDMOS device.
The silicon carbide material has excellent electrical properties, such as larger forbidden band width, higher thermal conductivity, higher electron saturation drift velocity and higher critical breakdown electric field, so that the silicon carbide material becomes an ideal semiconductor material in high-temperature, high-frequency, high-power and anti-radiation application occasions. Silicon carbide semiconductor materials are widely used in the power field for the preparation of high-power electronic devices. Currently, silicon carbide electronic devices are subject to interference from the surrounding environment, which causes the electronic devices to be damaged to varying degrees, affecting their electrical performance, and even causing the devices to fail permanently, such as: the effect of the radiated signal.
Therefore, a new high-voltage VDMOS device is needed to reduce the influence of radiation signals on the device.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the VDMOS device is prepared by utilizing the characteristics of high temperature resistance, high critical electric field, high thermal conductivity and the like of SiC, the influence of radiation signals on the threshold voltage and the specific on-resistance of the device can be effectively reduced by adopting the VDMOS with an N-type channel, and the switching speed can be increased under the high-frequency condition.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a novel high voltage VDMOS device comprising: the device comprises an N-type heavily doped substrate, an N-type lightly doped buffer region, a P-type well region, an N-type heavily doped source region, a P-type heavily doped source region, a NISI source region, a high-K insulating layer, a gate polysilicon region, a NISI drain region, a gate electrode, a source electrode and a drain electrode.
Further, the NISI drain region is formed on the lower surface of the N-type heavily doped substrate, the drain electrode is formed on the lower surface of the NISI drain region, the N-type lightly doped buffer region is formed on the upper surface of the N-type heavily doped substrate, two P-type well regions are formed on the upper surface of the N-type lightly doped buffer region, a gap is formed between the two P-type well regions, the two P-type well regions are symmetrical about the center line of the device, two N-type heavily doped source regions and one P-type heavily doped source region are formed on the upper surface of each P-type well region, the P-type heavily doped source region is formed between the two N-type heavily doped source regions, the N-type heavily doped source region and the P-type heavily doped source region are connected to each other, and the NISI source regions are formed on the upper surfaces of the N-type heavily doped source region and the P-type heavily, and a space is arranged between the side edge of the N-type heavily doped source region and the side edge of the P-type well region.
Furthermore, a high-K insulating layer is arranged on the upper surfaces of the two P-type well regions and the N-type lightly doped buffer region, two side edges of the high-K insulating layer are arranged on the two N-type heavily doped source regions close to the central line of the device, the upper surface of the high-K insulating layer is provided with the gate polysilicon region, the upper surface of the gate polysilicon region is provided with a gate electrode, and the upper surfaces of the two N-type heavily doped source regions and one P-type heavily doped source region are provided with the source electrode.
Further, the thickness of the N-type lightly doped buffer region is smaller than that of the N-type heavily doped substrate.
Further, the thickness of the N-type lightly doped buffer region is greater than that of the P-type well region.
Further, the high-K insulating layer is a high-K insulating material of a single substance or a compound.
Further, the source electrode, the gate electrode, and the drain electrode are made of a copper material or an aluminum material.
Further, the semiconductor substrate material is a semiconductor SiC-based material.
A novel preparation method of a high-voltage VDMOS device comprises the following steps:
s1, cleaning and exposure: cleaning and drying a semiconductor substrate, coating a layer of photoresist on the upper surface of the semiconductor substrate, exposing by adopting a mask plate defined by the N-type heavily doped substrate and a laser, and developing to form the definition of the N-type heavily doped substrate;
s2, forming an N-type heavily doped substrate and an N-type lightly doped buffer region: forming the N-type heavily doped substrate in the semiconductor substrate in an ion implantation mode, and forming the N-type lightly doped buffer region on the upper surface of the N-type heavily doped substrate;
s3, defining a P-type well region: removing photoresist defined by the N-type heavily doped substrate, coating a new layer of photoresist, exposing by adopting a mask plate and a laser defined by the P-type well region, and developing to form the definition of the P-type well region;
s4, forming a P-type well region: forming the P-type well region in the semiconductor substrate and on the N-type lightly doped buffer region by ion implantation;
s5, definition of N-type heavily doped source region: removing the photoresist defined by the P-type well region, coating a new layer of photoresist, exposing by adopting a mask plate and a laser defined by the N-type heavily doped source region, and developing to form the definition of the N-type heavily doped source region;
s6, forming an N-type heavily doped source region in the semiconductor substrate in an ion implantation mode, and forming the N-type heavily doped source region on the P-type well region;
s7, definition of a P type heavily doped source region: removing the photoresist defined by the N-type heavily doped source region, coating a new layer of photoresist, exposing by adopting a mask plate and a laser defined by the P-type heavily doped source region, and forming the definition of the P-type heavily doped source region after developing;
s8, forming a P-type heavily doped source region in the semiconductor substrate in an ion implantation mode, and forming the P-type heavily doped source region on the P-type well region;
s9, formation of high-K insulating layer: removing the photoresist defined by the P-type heavily doped source region, and depositing a high-K insulating layer on the upper surface of the semiconductor substrate;
s10, forming a gate polycrystalline silicon layer: depositing a layer of grid polysilicon material on the upper surface of the high-K insulating layer to form a grid polysilicon layer;
s11, definition of gate structure: coating a layer of photoresist on the grid polycrystalline silicon layer, exposing by adopting a mask plate and a laser defined by the grid structure, and developing to form the definition of the grid structure;
s12, forming a gate structure: the gate structure comprises a high-K insulating layer and a gate polysilicon region, the gate structure is etched by adopting an etching technology, and photoresist defined by the gate structure is removed;
s13, definition of NISI source regions: coating a layer of photoresist on the upper surface of the semiconductor substrate formed in the step S12, exposing by using a mask plate and a laser defined by the NISI source region, and forming the definition of the NISI source region after developing;
s14, formation of NISI source regions: forming the NISI source region in the semiconductor substrate in an ion implantation mode on the N-type heavily doped source region and the P-type heavily doped source region;
s15, exposure of N-type heavily doped substrate: removing the photoresist defined by the NISI source region, and cutting off the redundant semiconductor substrate by a laser cutting method on the lower surface of the semiconductor substrate to expose the N-type heavily doped substrate;
s16, formation of NISI drain region: coating a new layer of photoresist on the lower surface of the semiconductor substrate in the step S15, exposing by adopting a mask plate and a laser defined by the NISI drain region, forming the definition of the NISI drain region after developing, and forming the NISI drain region in the semiconductor substrate and on the N-type heavily doped substrate in an ion implantation mode;
s17, formation of electrode: and depositing a metal electrode on the upper surface of the gate polysilicon region, depositing a metal electrode on the upper surface of the NISI source region, and depositing a metal electrode on the lower surface of the NISI drain region.
Advantageous effects
The invention discloses a novel high-voltage VDMOS device and a preparation method thereof, which are characterized in that the VDMOS device is prepared by utilizing the characteristics of high temperature resistance, high critical electric field, high thermal conductivity and the like of SiC, the influence of radiation signals on the threshold voltage and specific on-resistance of the device can be effectively reduced by adopting the VDMOS with an N-type channel, and the switching speed can be improved under the high-frequency condition.
Drawings
Fig. 1 is a schematic structural diagram of a novel high-voltage VDMOS device according to the present invention.
Fig. 2 is a flow chart of the preparation of a novel high-voltage VDMOS device according to the present invention.
FIG. 3 shows the effect of different proton mass on Vgs-Igs for a novel high voltage VDMOS device of the present invention under 5MeV energy irradiation.
Fig. 4 shows the effect of different proton amounts on Vth and Ron of a novel high voltage VDMOS device of the present invention under 5MeV energy irradiation.
Reference numerals: 1. an N-type heavily doped substrate; 2. an N-type lightly doped buffer region; 3. a P-type well region; 4. an N-type heavily doped source region; 5. a P-type heavily doped source region; 6. a NISI source region; 7. a high-K insulating layer; 8. a gate polysilicon region; 9. a NISI drain region; s, a source electrode; D. a drain electrode; G. a gate electrode; 11. radiation 1 curve; 12. radiation 2 curve; 13. radiation 3 curve; 101. a Ron curve; 201. the Vth curve.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a novel high-voltage VDMOS device according to the present invention.
The invention provides a novel high-voltage VDMOS device, which comprises: the transistor comprises an N-type heavily doped substrate 1, an N-type lightly doped buffer region 2, a P-type well region 3, an N-type heavily doped source region 4, a P-type heavily doped source region 5, an NISI source region 6, a high-K insulating layer 7, a gate polysilicon region 8, an NISI drain region 9, a gate electrode G, a source electrode S and a drain electrode D;
wherein the NISI drain region 9 is formed on the lower surface of the N-type heavily doped substrate 1, the drain electrode D is formed on the lower surface of the NISI drain region 9, the N-type lightly doped buffer region 2 is arranged on the upper surface of the N-type heavily doped substrate 1, two P-type well regions 3 are arranged on the upper surface of the N-type lightly doped buffer region 2, a gap is arranged between the two P-type well regions 3, the two P-type well regions 3 are symmetrical about the central line of the device, two N-type heavily doped source regions 4 and one P-type heavily doped source region 5 are arranged on the upper surface of each P-type well region 3, the P-type heavily doped source region 5 is arranged between the two N-type heavily doped source regions 4, the N-type heavily doped source regions 4 and the P-type heavily doped source regions 5 are connected with each other, and NISI source regions 6 are arranged on the upper surfaces of the N-type heavily doped source regions 4 and the P-type heavily doped source regions 5, a gap is arranged between the side edge of the N-type heavily doped source region 4 and the side edge of the P-type trap region 3;
two the upper surface of P type trap district 3 with N type lightly doped buffer 2 is equipped with high K insulating layer 7, two sides of high K insulating layer 7 are established and are close to two of device central line on the heavily doped source region 4 of N type, the upper surface of high K insulating layer 7 is equipped with grid polycrystalline silicon region 8, the upper surface of grid polycrystalline silicon region 8 is equipped with gate electrode G, two heavily doped source region 4 of N type and one the upper surface of P type heavily doped source region 5 is equipped with source electrode S.
Example one
The thickness of the N-type heavily doped substrate 1 is 350 μm, the thickness of the N-type lightly doped region 2 is 10 μm, and the doped nitrogen concentration is 5.8 × 1015cm-3(ii) a The thickness of the P-type well region 3 is 3 μm, and the doped aluminum ion concentration is 3.9 × 1017cm-3(ii) a The width of each of the two channels is 2 μm; the thickness of the high-K insulating layer 7 is 75 nm; the thickness of the gate polysilicon region 8 is 0.5 μm, and the width thereof is 6 μm; the distance between the two P-type well regions 3 is 2 mu m; the NISI source region 6 is 200nm and the NISI drain region 9 is 200 nm.
Referring to fig. 2, a method for manufacturing a novel high-voltage VDMOS device includes the following steps:
s1, cleaning and exposure: cleaning and drying a semiconductor substrate, coating a layer of photoresist on the upper surface of the semiconductor substrate, exposing by adopting a mask plate and a laser defined by the N-type heavily doped substrate 1, and developing to form the definition of the N-type heavily doped substrate 1;
s2, forming an N type heavily doped substrate 1 and an N type lightly doped buffer region 2: forming the N-type heavily doped substrate 1 in the semiconductor substrate in an ion implantation mode, and forming the N-type lightly doped buffer region 2 on the upper surface of the N-type heavily doped substrate 1;
s3, definition of P-type well region 3: removing the photoresist defined by the N-type heavily doped substrate 1, coating a new layer of photoresist, exposing by adopting a mask plate and a laser defined by the P-type well region 3, and developing to form the definition of the P-type well region 3;
s4, formation of P-type well region 3: forming the P-type well region 3 in the semiconductor substrate and on the N-type lightly doped buffer region 2 by ion implantation;
s5, definition of the N-type heavily doped source region 4: removing the photoresist defined by the P-type well region 3, coating a new layer of photoresist, exposing by adopting a mask plate and a laser defined by the N-type heavily doped source region 4, and developing to form the definition of the N-type heavily doped source region 4;
s6, forming an N-type heavily-doped source region 4, and forming the N-type heavily-doped source region 4 in the semiconductor substrate and on the P-type well region 3 in an ion implantation mode;
s7, definition of P-type heavily doped source region 5: removing the photoresist defined by the N-type heavily doped source region 4, coating a new layer of photoresist, exposing by adopting a mask plate and a laser defined by the P-type heavily doped source region 5, and developing to form the definition of the P-type heavily doped source region 5;
s8, forming a P-type heavily-doped source region 5, forming the P-type heavily-doped source region 5 in the semiconductor substrate in an ion implantation mode on the P-type well region 3;
s9, formation of high-K insulating layer: removing the photoresist defined by the P-type heavily doped source region 5, and depositing a high-K insulating layer on the upper surface of the semiconductor substrate;
s10, forming a gate polycrystalline silicon layer: depositing a layer of grid polysilicon material on the upper surface of the high-K insulating layer to form a grid polysilicon layer;
s11, definition of gate structure: coating a layer of photoresist on the grid polycrystalline silicon layer, exposing by adopting a mask plate and a laser defined by the grid structure, and developing to form the definition of the grid structure;
s12, forming a gate structure: the gate structure comprises a high-K insulating layer 7 and a gate polysilicon region 8, the gate structure is etched by adopting an etching technology, and photoresist defined by the gate structure is removed;
s13, definition of the NISI source region 6: coating a layer of photoresist on the upper surface of the semiconductor substrate formed in the step S12, exposing by using a mask plate and a laser defined by the NISI source region 6, and forming the definition of the NISI source region 6 after developing;
s14, formation of the NISI source region 6: forming the NISI source region 6 in the semiconductor substrate in an ion implantation manner and on the N-type heavily doped source region 4 and the P-type heavily doped source region 5;
s15, exposure of N-type heavily doped substrate 1: removing the photoresist defined by the NISI source region 6, and cutting off the redundant semiconductor substrate by a laser cutting method on the lower surface of the semiconductor substrate to expose the N-type heavily doped substrate 1;
s16, formation of the NISI drain region 9: coating a new layer of photoresist on the lower surface of the semiconductor substrate in the step S15, exposing by using a mask plate and a laser defined by the NISI drain region 9, forming the definition of the NISI drain region 9 after developing, and forming the NISI drain region 9 in the semiconductor substrate and on the N-type heavily doped substrate 1 in an ion implantation manner;
s17, formation of electrode: and depositing a metal electrode on the upper surface of the gate polysilicon region 8, depositing a metal electrode on the upper surface of the NISI source region 6, and depositing a metal electrode on the lower surface of the NISI drain region 9.
Based on the first embodiment, the high-voltage VDMOS device can achieve a voltage of 1.2KV, which is shown in fig. 3, which is a relationship diagram of a curve 101 of an amount of radiated protons and an on-resistance Ron and a curve 201 of a threshold voltage Vth, and values of the on-resistance Ron and the threshold voltage Vth both decrease with an increase in the amount of radiated protons; referring to FIG. 4, the effect of different proton doses on Vth and Ron is shown, where the radiation 1 curve 11 is the proton dose of 5 × 1012p/cm2The radiation 2 curve 12 is the proton quantity 5X 1013p/cm2The radiation 3 curve 13 is the proton quantity 5X 1014p/cm2Different amounts of irradiated protons have little effect on Igs.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. A novel high-voltage VDMOS device is characterized by comprising: the transistor comprises an N-type heavily doped substrate (1), an N-type lightly doped buffer region (2), a P-type well region (3), an N-type heavily doped source region (4), a P-type heavily doped source region (5), an NISI source region (6), a high-K insulating layer (7), a grid polysilicon region (8), an NISI drain region (9), a grid electrode (G), a source electrode (S) and a drain electrode (D);
wherein the NISI drain region (9) is formed on the lower surface of the N-type heavily doped substrate (1), the drain electrode (D) is formed on the lower surface of the NISI drain region (9), the N-type lightly doped buffer region (2) is arranged on the upper surface of the N-type heavily doped substrate (1), two P-type well regions (3) are arranged on the upper surface of the N-type lightly doped buffer region (2), a gap is arranged between the two P-type well regions (3), the two P-type well regions (3) are symmetrical about the central line of the device, two N-type heavily doped source regions (4) and one P-type heavily doped source region (5) are arranged on the upper surface of each P-type well region (3), the P-type heavily doped source region (5) is arranged between the two N-type heavily doped source regions (4), and the N-type heavily doped source regions (4) and the P-type heavily doped source regions (5) are connected with each other, NISI source regions (6) are arranged on the upper surfaces of the N-type heavily doped source region (4) and the P-type heavily doped source region (5), and intervals are arranged between the side edge of the N-type heavily doped source region (4) and the side edge of the P-type well region (3);
two the upper surface of P type well region (3) with N type lightly doped buffer region (2) is equipped with high K insulating layer (7), two sides of high K insulating layer (7) are established and are close to two of device central line on N type heavily doped source region (4), the upper surface of high K insulating layer (7) is equipped with grid polysilicon region (8), the upper surface of grid polysilicon region (8) is equipped with gate electrode (G), two N type heavily doped source region (4) and one the upper surface of P type heavily doped source region (5) is equipped with source electrode (S).
2. A new type of high voltage VDMOS device according to claim 1, characterized in that the thickness of the N-type lightly doped buffer (2) is smaller than the thickness of the N-type heavily doped substrate (1).
3. A new type of high voltage VDMOS device according to claim 1, characterized by the fact that the thickness of the N-type lightly doped buffer (2) is greater than the thickness of the P-type well (3).
4. A new type of high voltage VDMOS device according to claim 1, characterized by the fact that the high-K dielectric layer (7) is a simple or compound high-K dielectric material.
5. The new high-voltage VDMOS device according to claim 1, wherein the material of the source electrode (S), the gate electrode (G) and the drain electrode (D) is copper material or aluminum material.
6. The novel high-voltage VDMOS device as recited in claim 1, wherein the semiconductor substrate material is a semiconductor SiC-based material.
7. A novel preparation method of a high-voltage VDMOS device is characterized by comprising the following steps:
s1, cleaning and exposure: cleaning and drying a semiconductor substrate, coating a layer of photoresist on the upper surface of the semiconductor substrate, exposing by adopting a mask plate and a laser defined by the N-type heavily doped substrate (1), and developing to form the definition of the N-type heavily doped substrate (1);
s2, forming an N-type heavily doped substrate (1) and an N-type lightly doped buffer region (2): forming the N-type heavily doped substrate (1) in the semiconductor substrate in an ion implantation mode, and forming the N-type lightly doped buffer region (2) on the upper surface of the N-type heavily doped substrate (1);
s3, definition of the P-type well region (3): removing the photoresist defined by the N-type heavily doped substrate (1), coating a new layer of photoresist, exposing by adopting a mask plate and a laser defined by the P-type well region (3), and developing to form the definition of the P-type well region (3);
s4, forming a P-type well region (3): forming the P-type well region (3) in the semiconductor substrate and on the N-type lightly doped buffer region (2) by means of ion implantation;
s5, definition of an N-type heavily doped source region (4): removing the photoresist defined by the P-type well region (3), coating a new layer of photoresist, exposing by adopting a mask plate and a laser defined by the N-type heavily doped source region (4), and forming the definition of the N-type heavily doped source region (4) after developing;
s6, forming an N-type heavily doped source region (4), forming the N-type heavily doped source region (4) on the P-type well region (3) in the semiconductor substrate in an ion implantation mode;
s7, definition of a P type heavily doped source region (5): removing the photoresist defined by the N-type heavily doped source region (4), coating a new layer of photoresist, exposing by adopting a mask plate and a laser defined by the P-type heavily doped source region (5), and forming the definition of the P-type heavily doped source region (5) after developing;
s8, forming a P-type heavily doped source region (5), forming the P-type heavily doped source region (5) on the P-type well region (3) in the semiconductor substrate in an ion implantation mode;
s9, formation of high-K insulating layer: removing the photoresist defined by the P-type heavily doped source region (5), and depositing a high-K insulating layer on the upper surface of the semiconductor substrate;
s10, forming a gate polycrystalline silicon layer: depositing a layer of grid polysilicon material on the upper surface of the high-K insulating layer to form a grid polysilicon layer;
s11, definition of gate structure: coating a layer of photoresist on the grid polycrystalline silicon layer, exposing by adopting a mask plate and a laser defined by the grid structure, and developing to form the definition of the grid structure;
s12, forming a gate structure: the gate structure comprises a high-K insulating layer (7) and a gate polysilicon region (8), the gate structure is etched by adopting an etching technology, and photoresist defined by the gate structure is removed;
s13, definition of the NISI source region (6): coating a layer of photoresist on the upper surface of the semiconductor substrate formed in the step S12, exposing by using a mask plate defined by the NISI source region (6) and a laser, and forming the definition of the NISI source region (6) after developing;
s14, formation of NISI source region (6): forming the NISI source region (6) in the semiconductor substrate and on the N-type heavily doped source region (4) and the P-type heavily doped source region (5) by means of ion implantation;
s15, exposure of N-type heavily doped substrate (1): removing the photoresist defined by the NISI source region (6), and cutting off the redundant semiconductor substrate by a laser cutting method on the lower surface of the semiconductor substrate to expose the N-type heavily doped substrate (1);
s16, formation of the NISI drain region (9): coating a new photoresist on the lower surface of the semiconductor substrate in the step S15, exposing by using a mask plate defined by the NISI drain region (9) and a laser, forming the definition of the NISI drain region (9) after developing, and forming the NISI drain region (9) in the semiconductor substrate and on the N-type heavily doped substrate (1) in an ion implantation mode;
s17, formation of electrode: and depositing a metal electrode on the upper surface of the gate polysilicon region (8), depositing a metal electrode on the upper surface of the NISI source region (6), and depositing a metal electrode on the lower surface of the NISI drain region (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110336336.5A CN112820778A (en) | 2021-03-29 | 2021-03-29 | Novel high-voltage VDMOS device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110336336.5A CN112820778A (en) | 2021-03-29 | 2021-03-29 | Novel high-voltage VDMOS device and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112820778A true CN112820778A (en) | 2021-05-18 |
Family
ID=75863528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110336336.5A Pending CN112820778A (en) | 2021-03-29 | 2021-03-29 | Novel high-voltage VDMOS device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112820778A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123271A (en) * | 2006-08-11 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
| CN102683210A (en) * | 2011-03-18 | 2012-09-19 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102751332A (en) * | 2012-07-20 | 2012-10-24 | 杭州士兰微电子股份有限公司 | Depletion type power semiconductor device and manufacturing method thereof |
| CN102770949A (en) * | 2010-11-16 | 2012-11-07 | 住友电气工业株式会社 | Silicon carbide semiconductor device |
| CN103077895A (en) * | 2012-12-19 | 2013-05-01 | 上海宏力半导体制造有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) transistor and formation method thereof |
| CN103247684A (en) * | 2012-02-13 | 2013-08-14 | 台湾积体电路制造股份有限公司 | Insulated gate bipolar transistor structure having low substrate leakage |
| US20190221560A1 (en) * | 2016-08-31 | 2019-07-18 | Csmc Technologies Fab2 Co., Ltd. | Device integrated with depletion-mode junction fielf-effect transistor and method for manufacturing the same |
| CN111048580A (en) * | 2019-12-20 | 2020-04-21 | 中国科学院微电子研究所 | Silicon carbide insulated gate bipolar transistor and manufacturing method thereof |
| CN112466936A (en) * | 2020-12-21 | 2021-03-09 | 厦门芯一代集成电路有限公司 | High-voltage IGBT device and preparation method thereof |
| CN212810309U (en) * | 2020-09-11 | 2021-03-26 | 厦门芯一代集成电路有限公司 | Planar split gate IGBT semiconductor power device |
-
2021
- 2021-03-29 CN CN202110336336.5A patent/CN112820778A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123271A (en) * | 2006-08-11 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
| CN102770949A (en) * | 2010-11-16 | 2012-11-07 | 住友电气工业株式会社 | Silicon carbide semiconductor device |
| CN102683210A (en) * | 2011-03-18 | 2012-09-19 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103247684A (en) * | 2012-02-13 | 2013-08-14 | 台湾积体电路制造股份有限公司 | Insulated gate bipolar transistor structure having low substrate leakage |
| CN102751332A (en) * | 2012-07-20 | 2012-10-24 | 杭州士兰微电子股份有限公司 | Depletion type power semiconductor device and manufacturing method thereof |
| CN103077895A (en) * | 2012-12-19 | 2013-05-01 | 上海宏力半导体制造有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) transistor and formation method thereof |
| US20190221560A1 (en) * | 2016-08-31 | 2019-07-18 | Csmc Technologies Fab2 Co., Ltd. | Device integrated with depletion-mode junction fielf-effect transistor and method for manufacturing the same |
| CN111048580A (en) * | 2019-12-20 | 2020-04-21 | 中国科学院微电子研究所 | Silicon carbide insulated gate bipolar transistor and manufacturing method thereof |
| CN212810309U (en) * | 2020-09-11 | 2021-03-26 | 厦门芯一代集成电路有限公司 | Planar split gate IGBT semiconductor power device |
| CN112466936A (en) * | 2020-12-21 | 2021-03-09 | 厦门芯一代集成电路有限公司 | High-voltage IGBT device and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107464837B (en) | Super junction power device | |
| CN112701151B (en) | SiC MOSFET device and manufacturing method thereof | |
| JP2001135831A (en) | Semiconductor device | |
| US20200006494A1 (en) | Silicon carbide semiconductor device | |
| JP5003598B2 (en) | Semiconductor device | |
| CN116504841B (en) | High-reliability silicon carbide MOSFET device and forming method thereof | |
| CN117253917A (en) | GaN MIS HEMT shielded by surface trap and preparation method thereof | |
| CN112466936A (en) | High-voltage IGBT device and preparation method thereof | |
| CN109713035B (en) | Planar gate bipolar transistor and manufacturing method thereof | |
| CN112713195B (en) | High-voltage VDMOS device and preparation method thereof | |
| CN113241381B (en) | High-voltage trench gate MOS device and preparation method thereof | |
| US11721755B2 (en) | Methods of forming semiconductor power devices having graded lateral doping | |
| CN112750912A (en) | High-voltage silicon carbide MOS device and preparation method thereof | |
| CN112820778A (en) | Novel high-voltage VDMOS device and preparation method thereof | |
| CN114220860A (en) | High-reliability planar gate SiC MOSFET device structure and preparation method thereof | |
| CN112838131B (en) | Schottky diode based on silicon carbide planar MOS structure | |
| CN114256355A (en) | High-reliability planar split gate SiC MOSFET device with source electrode field plate and preparation method thereof | |
| JPH0548117A (en) | Electrostatic induction semiconductor device | |
| CN110047931B (en) | Silicon carbide planar vertical field effect transistor and manufacturing method thereof | |
| CN116779537B (en) | Method for manufacturing semiconductor structure and semiconductor structure | |
| CN113130635B (en) | MOS device of I-type gate and preparation method thereof | |
| CN118136677B (en) | Planar gate type power metal-oxide field effect transistor and power device | |
| CN114927565B (en) | Integrated base region PNP transistor silicon carbide MOSFET device and preparation method | |
| CN214542246U (en) | Novel high-voltage VDMOS device | |
| US20220246723A1 (en) | Silicon carbide vertical conduction mosfet device for power applications and manufacturing process thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210518 |