CN112820712A - Fan-out type packaging structure integrated by three-dimensional heterogeneous and manufacturing method - Google Patents

Fan-out type packaging structure integrated by three-dimensional heterogeneous and manufacturing method Download PDF

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Publication number
CN112820712A
CN112820712A CN202011642597.1A CN202011642597A CN112820712A CN 112820712 A CN112820712 A CN 112820712A CN 202011642597 A CN202011642597 A CN 202011642597A CN 112820712 A CN112820712 A CN 112820712A
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layer
substrate
chip
metal interconnection
interconnection layer
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王楠鑫
马盛林
金玉丰
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The application discloses a three-dimensional heterogeneous integrated fan-out type packaging structure and a manufacturing method thereof. The three-dimensional heterogeneous integrated fan-out type packaging structure comprises: the base plate upside is provided with the recess, the recess is used for placing the chip, the recess bottom is provided with and leads electrical pillar, it runs through the base plate and connects the chip that corresponds to lead electrical pillar, first fixed bed sets up at the base plate upside, the setting of second metal interconnection layer is at the base plate downside, the connection of second metal interconnection layer corresponds leads electrical pillar, the second metal interconnection layer is used for making the electricity between the chip to be connected, the second fixed bed sets up at the base plate downside, the second metal interconnection layer that the micro-welding structural connection corresponds, the micro-welding structure is used for forming packaging structure's solder joint. Through set up the chip in the recess of same base plate to through leading electrical connection between the chip that electrical pillar and metal interconnection layer will correspond, realized three-dimensional heterogeneous integrated structure, satisfied small-size, high density, low-cost encapsulation demand.

Description

Fan-out type packaging structure integrated by three-dimensional heterogeneous and manufacturing method
Technical Field
The application relates to the technical field of microelectronic packaging, in particular to a three-dimensional heterogeneous integrated fan-out type packaging structure and a manufacturing method thereof.
Background
Micro Electro Mechanical Systems (MEMS) refers to a stand-alone System with dimensions in the micrometer range or smaller, and generally includes three major parts, i.e., a sensor, an actuator, and a signal processing unit. The MEMS captures external signals through the sensors and converts the signals into electric signals, and the electric signals are processed by the signal processing unit and then are transmitted to the actuator to carry out corresponding operation, so that the interconnection with the outside is realized, and the interconnection with all things can be really realized by configuring a sufficient number of sensors and actuators. However, to actually realize the functions of the whole system, it is often necessary to match the MEMS chip with its corresponding Application Specific Integrated Circuit (ASIC), but since the MEMS chip and the ASIC chip are very different in terms of the used materials, the size, the processing technology, and the like, the integration and packaging of the MEMS chip and the ASIC chip become a critical issue. In the related art, the ASIC chip and the MEMS chip are manufactured on the same wafer and are interconnected and integrated by using the fan-out type packaging platform, but three-dimensional integration is not realized by the method, and the steps of the IC process and the MEMS process are inserted together by the process, so that the process difficulty requirement is high, and the integration is difficult to be independently completed by a packaging factory.
Disclosure of Invention
The present application is directed to solving at least one of the problems in the prior art. Therefore, the fan-out type packaging structure for three-dimensional heterogeneous integration is provided, interconnection and integration of various chips in the same packaging structure can be achieved, three-dimensional heterogeneous integration is achieved, and therefore the packaging requirements of small size, high density and low cost are met.
According to the first aspect of the application, the three-dimensional heterogeneous integrated fan-out type packaging structure comprises: the chip packaging structure comprises a substrate, wherein at least two grooves are formed in the upper side of the substrate, and each groove is used for placing a chip; at least one conductive column is arranged at the bottom of each groove, penetrates through the substrate and is connected with a corresponding bonding pad of the chip; at least one first metal interconnection layer, each first metal interconnection layer connecting the corresponding conductive pillar; the first fixing layer is arranged on the upper side of the substrate and used for fixing each chip and each first metal interconnection layer; each second metal interconnection layer is arranged on the lower side of the substrate and is connected with the corresponding conductive column, and the second metal interconnection layers are used for enabling at least two chips to be electrically connected; the second fixing layer is arranged on the lower side of the substrate and used for fixing each second metal interconnection layer; and each micro-welding structure is connected with the corresponding second metal interconnection layer and is used for forming a welding spot of the packaging structure.
According to the fan-out type packaging structure of the three-dimensional heterogeneous integration, the following beneficial effects are at least achieved: through set up the chip in the recess of same base plate to through leading electrical connection between the chip that electrical pillar and metal interconnection layer will correspond, realized three-dimensional heterogeneous integrated structure, satisfied small-size, high density, low-cost encapsulation demand.
According to some embodiments of the present application, the substrate is a silicon substrate.
According to some embodiments of the present application, each of the conductive pillars includes, in order from outside to inside: an insulating layer, a diffusion barrier layer, and a conductive layer.
According to some embodiments of the present application, a material of the insulating layer is at least one of silicon oxide, silicon nitride, aluminum oxide, benzocyclobutene, polyimide, glass, polypropylene, or parylene.
According to some embodiments of the present application, the material of the diffusion barrier layer is at least one of tantalum, tantalum nitride, and titanium tungsten.
According to some embodiments of the application, the material of the conductive layer is at least one of copper, aluminum, gold, tungsten.
According to some embodiments of the application, further comprising: at least one adhesive linkage, each the adhesive linkage sets up and is in the correspondence the recess bottom, the adhesive linkage is used for bonding each the chip extremely on the base plate, the material of adhesive linkage is at least one in benzocyclobutene or the epoxy glue.
According to the third aspect of the application, the manufacturing method of the three-dimensional heterogeneous integrated fan-out type package comprises the following steps: etching the upper side of the substrate to obtain at least two grooves; etching and depositing the bottom of each groove to obtain at least one conductive column penetrating through the substrate; depositing at least one first metal interconnection layer on the upper side of the substrate, wherein the first metal interconnection layer is connected with the corresponding conductive column; placing a chip in each groove, and connecting a bonding pad of each chip with the corresponding conductive post; depositing a first fixing layer on the upper side of the substrate, wherein the first fixing layer is used for fixing each chip and the substrate; depositing at least one second metal interconnection layer on the lower side of the substrate, wherein the second metal interconnection layer is connected with the corresponding conductive column; depositing a second fixing layer on the lower side of the substrate, wherein the second fixing layer is used for fixing each second metal interconnection layer; etching the second fixed layer to obtain at least one connecting port; and arranging a micro-welding structure on each connecting port to form a welding spot of the packaging structure.
According to some embodiments of the present application, the step of etching and depositing the bottom of each groove to obtain at least one conductive pillar penetrating through the substrate includes: and etching the bottom of each groove to obtain at least one through hole penetrating through the substrate, and sequentially filling an insulating layer, a diffusion barrier layer and a conductive layer in each through hole to form at least one conductive column penetrating through the substrate.
According to some embodiments of the present application, the step of connecting the bonding pad of each chip to the corresponding conductive pillar specifically includes: and spraying an adhesive layer at the bottom of each groove, adhering each chip with the corresponding groove, and connecting the bonding pad of the chip with the corresponding conductive column.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The present application is further described with reference to the following figures and examples, in which:
FIG. 1 is a cross-sectional view of a three-dimensional heterogeneous integrated fan-out package structure according to an embodiment of the present application;
FIG. 2 is a flow chart of a method for manufacturing a fan-out package for three-dimensional heterogeneous integration according to an embodiment of the present application;
FIG. 3 is a partial cross-sectional view of a fan-out package structure for three-dimensional heterogeneous integration according to an embodiment of the present application;
FIG. 4 is another partial cross-sectional view of a fan-out package structure for three-dimensional heterogeneous integration according to an embodiment of the present application;
fig. 5 is a sectional view of another part of a three-dimensional heterogeneous integrated fan-out package structure according to an embodiment of the present application.
Reference numerals:
the substrate 110, the conductive pillar 120, the first metal interconnection layer 130, and the first fixed layer 140;
a second metal interconnection layer 150, a second fixing layer 160, and a micro-soldering structure 170.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it is to be understood that the positional descriptions, such as the directions of up, down, front, rear, left, right, etc., referred to herein are based on the directions or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific direction, be constructed and operated in a specific direction, and thus, should not be construed as limiting the present application.
In the description of the present application, the meaning of a plurality is one or more, the meaning of a plurality is two or more, and the above, below, exceeding, etc. are understood as excluding the present number, and the above, below, within, etc. are understood as including the present number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present application, unless otherwise expressly limited, terms such as set, mounted, connected and the like should be construed broadly, and those skilled in the art can reasonably determine the specific meaning of the terms in the present application by combining the detailed contents of the technical solutions.
Some embodiments, referring to fig. 1, the three-dimensional heterogeneous integrated fan-out package structure provided by the present application includes: the micro-soldering structure comprises a substrate 110, at least one conductive pillar 120, at least one first metal interconnection layer 130, a first fixed layer 140, at least one second metal interconnection layer 150, a second fixed layer 160 and at least one micro-soldering structure 170. At least two grooves are arranged on the upper side of the substrate 110, and each groove is used for placing a chip; at least one conductive pillar 120 is disposed at the bottom of each groove, each conductive pillar 120 penetrates through the substrate 110, and each conductive pillar 120 is connected to a pad of a corresponding chip; each first metal interconnection layer 130 is connected to the corresponding conductive pillar 120; the first fixing layer 140 is disposed on the upper side of the substrate 110, and the first fixing layer 140 is used for fixing each chip and each first metal interconnection layer 130; each second metal interconnection layer 150 is disposed on the lower side of the substrate 110, the second metal interconnection layer 150 is connected to the corresponding conductive pillar 120, and the second metal interconnection layer 150 is used for electrically connecting at least two chips; the second fixing layer 160 is disposed on the lower side of the substrate 110, and the second fixing layer 160 is used for fixing each second metal interconnection layer 150; each micro-solder structure 170 is connected to the corresponding second metal interconnection layer 150, and each micro-solder structure 170 is used for forming a solder joint of the package structure.
The three-dimensional heterogeneous integrated fan-out package structure of the present application is described in detail below with an exemplary embodiment in a package structure including two chips. The substrate 110 is provided with two grooves, the side walls of the grooves are perpendicular to the substrate 110, each groove is provided with a chip, one of the chips is a MEMS chip, the other is an ASIC chip, the heights of the two chips are different, in other embodiments, the number of the grooves can be arbitrarily set according to the number of the chips, the side walls of the grooves can be set to be inclined, and the chips can be the same type of chips or the same height of chips.
All be provided with a plurality of electrically conductive poles 120 in the bottom of two recesses, electrically conductive pole 120 can be hollow structure or solid structure, and the quantity of electrically conductive pole 120 can be according to the demand of interconnection between the different chips arbitrary setting, and the pad of chip is the interface that communicates and realize the complete function of chip with other components, and through being connected the pad with electrically conductive pole 120, communication connection between the convenient messenger a plurality of chips.
The first metal interconnection layer 130 is disposed along the sidewall of the groove, the first metal interconnection layer 130 leads out the connection port of the chip from the upper side of the substrate 110, and the function of connecting the external element from the upper side of the substrate 110 to the chip can be realized through the opening disposed on the first fixing layer 140, wherein the number and the routing shape of the first metal interconnection layer 130 can be arbitrarily set. The first fixing layer 140 wraps the plurality of chips and the plurality of first metal interconnection layers 130, so that the different first metal interconnection layers 130 are insulated and isolated, and the first fixing layer 140 also plays a role in fixing the chips and the first metal interconnection layers 130, so that the whole packaging structure is stabilized.
The second metal interconnection layer 150 is arranged on the lower side of the substrate 110, the conductive columns 120 arranged below different chips are connected, so that the different chips are electrically connected, the number of the second metal interconnection layers 150 can be set at will, if the number of the second metal interconnection layers 150 in the same plane is too large, another layer connection layer can be arranged at a position farther away from the lower side of the substrate 110 after being isolated by the second fixing layer 160, and therefore the effect of connecting the conductive columns 120 is achieved on different planes, and the number of the layers can be set at will according to the complexity of connection of different chips. The material of each of the first and second fixed layers 140 and 160 may be at least one of silicon oxide, silicon nitride, aluminum oxide, benzocyclobutene, polyimide, glass, polypropylene, or parylene.
Through the arrangement of the micro-welding structure 170, the second metal interconnection layer 150 is led out to form a connector required by three-dimensional integration, and the three-dimensional integrated packaging chip can be conveniently welded on a PCB to complete different functions. The micro-soldering structure 170 may be a micro-solder ball, a micro-solder pad or a micro-solder point, and the material of the micro-soldering structure 170 may be at least one of a tin-silver alloy, a tin-gold alloy or a tin-copper alloy.
The problem of three-dimensional system packaging and stacking can be solved by arranging the grooves and the conductive posts 120, chip three-dimensional stacking and three-dimensional packaging application are realized, the problem of overlarge height difference of different chips in heterogeneous integration is solved, the application range of a product is greatly increased, and the packaging requirements of small size, high density and low cost are met.
In some embodiments, the substrate 110 is a silicon substrate. Compared with common plastic package materials, the silicon substrate is used as the substrate 110, the warping degree of a packaged product can be obviously reduced, the silicon substrate has the characteristics of high strength and low stress, the packaging of a large-size chip can be realized, and the silicon substrate is used for matching the thermal stress between the substrate 110 and the chip more and improving the reliability of the product because the chip is mainly made of silicon-based chips.
In some embodiments, each conductive pillar 120 includes, in order from outside to inside: an insulating layer, a diffusion barrier layer, and a conductive layer. By arranging the insulating layer on the outermost side of the conductive posts 120, the insulating property between different conductive posts 120 is increased, and the generation of leakage current is prevented. The diffusion barrier layer is arranged to prevent metal in the conducting layer from diffusing, and the service life of the device is prolonged.
In some embodiments, the material of the insulating layer is at least one of silicon oxide, silicon nitride, aluminum oxide, benzocyclobutene, polyimide, glass, polypropylene, or parylene.
In some embodiments, the material of the diffusion barrier layer is at least one of tantalum, tantalum nitride, and titanium tungsten.
In some embodiments, the material of the conductive layer is at least one of copper, aluminum, gold, and tungsten.
In some embodiments, the three-dimensional heterogeneous integrated fan-out package structure of the present application further comprises: at least one adhesive linkage, each adhesive linkage sets up in corresponding recess bottom, and the adhesive linkage is used for bonding each chip to the base plate 110 on, and the material of adhesive linkage is at least one in benzocyclobutene or epoxy. The chip is bonded to the bottom of the groove through the adhesive layer, so that the pad of the chip is tightly connected to the conductive post 120.
The application also provides a manufacturing method of the three-dimensional heterogeneous integrated fan-out package, which refers to fig. 2 and comprises the following steps:
210, etching the upper side of the substrate to obtain at least two grooves;
220, etching and depositing the bottom of each groove to obtain at least one conductive post penetrating through the substrate;
230, depositing at least one first metal interconnection layer on the upper side of the substrate, wherein the first metal interconnection layer is connected with the corresponding conductive column;
240, placing a chip in each groove, and connecting the bonding pad of each chip with the corresponding conductive post;
250, depositing a first fixing layer on the upper side of the substrate, wherein the first fixing layer is used for fixing each chip and the substrate;
260, depositing at least one second metal interconnection layer on the lower side of the substrate, wherein the second metal interconnection layer is connected with the corresponding conductive column;
270, depositing a second fixing layer on the lower side of the substrate, wherein the second fixing layer is used for fixing each second metal interconnection layer;
280, etching the second fixed layer to obtain at least one connecting port;
and 290, arranging a micro-welding structure on each connecting port to form a welding point of the packaging structure.
In a specific example, referring to fig. 3, a substrate 110 is provided, and an etching process is used on the upper side of the substrate 110 to obtain two grooves, wherein the etching process may be one of deep reactive ion etching, inductively coupled plasma etching, and organic or inorganic wet etching. And etching the bottom of the groove by deep reactive ion etching or laser etching and other technologies to obtain different numbers of through holes with small size and high depth-to-width ratio. After the through hole is obtained, a conductive material is deposited in the through hole by using methods such as electroplating or chemical plating, and the conductive column 120 is obtained, and the conductive column 120 obtained by deposition can be a hollow structure or a solid structure, and only the requirement of current circulation needs to be met. First metal interconnection layers 130 with different connection directions are prepared on the upper side of the substrate 110 by using a deposition process, and the first metal interconnection layers 130 are connected with the corresponding conductive pillars 120. And manufacturing a connection point connected with the chip pad in a flip-chip bonding mode at the bottom of the groove.
Referring to fig. 4, the corresponding chip is connected to conductive post 120 by flip-chip bonding. The first fixing layer 140 is formed on the chip and the first metal interconnection layer 130 by at least one of a physical or chemical method, such as plasma enhanced chemical vapor deposition, physical vapor deposition, spin coating, or spray coating, to fix the structure on the upper side of the substrate 110, thereby facilitating the subsequent process on the lower side of the substrate 110. A plurality of second metal interconnection layers 150 are prepared on the lower side of the substrate 110 by using a deposition process, and each second metal interconnection layer 150 is connected to a corresponding conductive pillar 120. Under the condition that one metal layer cannot accommodate all the second metal interconnection layers 150, the first metal layer may be fixed by one fixing layer, and the openings are formed at the corresponding conductive pillars 120, and then the second metal layer is deposited until all the second metal interconnection layers 150 are prepared, and the second fixing layer 160 is composed of a plurality of fixing layers.
And finally, opening the position of the second metal interconnection layer 150 to be led out by etching to obtain a connector, and manufacturing a micro-welding structure 170 on the connector to form a welding spot of the whole packaging structure for connecting with an external element.
In some other embodiments, referring to fig. 5, when the chip is not connected, the second metal interconnection layer 150 is prepared on the lower side of the substrate 110 by a deposition process for connecting the conductive pillars 120, and after the second metal interconnection layer 150 and the second fixing layer 160 are prepared, the chip is connected, and the first fixing layer 140 is formed on the upper side of the substrate 110 in a covering manner, so that the same package structure can be obtained.
In some embodiments, the step of etching and depositing the bottom of each groove to obtain at least one conductive pillar 120 penetrating through the substrate 110 includes: and etching the bottom of each groove to obtain at least one through hole penetrating through the substrate 110, and sequentially filling an insulating layer, a diffusion barrier layer and a conductive layer in each through hole to form at least one conductive column 120 penetrating through the substrate 110. The insulating layer is filled in the same manner as the fixing layer, and the material of the insulating layer may also be the same, and then the diffusion barrier layer and the conductive layer are sequentially deposited by electroplating and chemical plating, thereby completing the preparation of the conductive post 120.
In some embodiments, the step of connecting the pad of each chip to the corresponding conductive pillar 120 includes: and spraying an adhesive layer at the bottom of each groove, and adhering each chip to the corresponding groove, so that the bonding pad of the chip is connected to the corresponding conductive post 120. The bonding layer is used for firmly bonding the chip to the bottom of the groove, so that the chip is prevented from loosening, and the subsequent process manufacturing is facilitated.
In the description of the present application, reference to the description of the terms "some embodiments," "exemplary embodiments," "examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The embodiments of the present application have been described in detail with reference to the drawings, but the present application is not limited to the embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present application. Furthermore, the embodiments and features of the embodiments of the present application may be combined with each other without conflict.

Claims (10)

1. Three-dimensional heterogeneous integrated fan-out type packaging structure, its characterized in that includes:
the chip packaging structure comprises a substrate, wherein at least two grooves are formed in the upper side of the substrate, and each groove is used for placing a chip;
at least one conductive column is arranged at the bottom of each groove, penetrates through the substrate and is connected with a corresponding bonding pad of the chip;
at least one first metal interconnection layer, each first metal interconnection layer connecting the corresponding conductive pillar;
the first fixing layer is arranged on the upper side of the substrate and used for fixing each chip and each first metal interconnection layer;
each second metal interconnection layer is arranged on the lower side of the substrate and is connected with the corresponding conductive column, and the second metal interconnection layers are used for enabling at least two chips to be electrically connected;
the second fixing layer is arranged on the lower side of the substrate and used for fixing each second metal interconnection layer;
and each micro-welding structure is connected with the corresponding second metal interconnection layer and is used for forming a welding spot of the packaging structure.
2. The three-dimensional heterogeneous integrated fan-out package structure of claim 1, wherein the substrate is a silicon substrate.
3. The three-dimensional heterogeneous integrated fan-out package structure of claim 1, wherein each conductive pillar comprises, in order from outside to inside: an insulating layer, a diffusion barrier layer, and a conductive layer.
4. The three-dimensional heterogeneous integrated fan-out package structure of claim 3, wherein the insulating layer is made of at least one of silicon oxide, silicon nitride, aluminum oxide, benzocyclobutene, polyimide, glass, polypropylene, or parylene.
5. The three-dimensional heterogeneous integrated fan-out package structure of claim 3, wherein the material of the diffusion barrier layer is at least one of tantalum, tantalum nitride and titanium tungsten.
6. The three-dimensional heterogeneous integrated fan-out package structure of claim 3, wherein the material of the conductive layer is at least one of copper, aluminum, gold, and tungsten.
7. The three-dimensional heterogeneous integrated fan-out package structure of claim 1, further comprising: at least one adhesive linkage, each the adhesive linkage sets up and is in the correspondence the recess bottom, the adhesive linkage is used for bonding each the chip extremely on the base plate, the material of adhesive linkage is at least one in benzocyclobutene or the epoxy glue.
8. The manufacturing method of the three-dimensional heterogeneous integrated fan-out type package is characterized by comprising the following steps:
etching the upper side of the substrate to obtain at least two grooves;
etching and depositing the bottom of each groove to obtain at least one conductive column penetrating through the substrate;
depositing at least one first metal interconnection layer on the upper side of the substrate, wherein the first metal interconnection layer is connected with the corresponding conductive column;
placing a chip in each groove, and connecting a bonding pad of each chip with the corresponding conductive post;
depositing a first fixing layer on the upper side of the substrate, wherein the first fixing layer is used for fixing each chip and the substrate;
depositing at least one second metal interconnection layer on the lower side of the substrate, wherein the second metal interconnection layer is connected with the corresponding conductive column;
depositing a second fixing layer on the lower side of the substrate, wherein the second fixing layer is used for fixing each second metal interconnection layer;
etching the second fixed layer to obtain at least one connecting port;
and arranging a micro-welding structure on each connecting port to form a welding spot of the packaging structure.
9. The manufacturing method of the three-dimensional heterogeneous integrated fan-out package according to claim 8, wherein the step of etching and depositing the bottom of each groove to obtain at least one conductive pillar penetrating through the substrate includes:
and etching the bottom of each groove to obtain at least one through hole penetrating through the substrate, and sequentially filling an insulating layer, a diffusion barrier layer and a conductive layer in each through hole to form at least one conductive column penetrating through the substrate.
10. The manufacturing method of the three-dimensional heterogeneous integrated fan-out package according to claim 8, wherein the step of connecting the bonding pad of each chip with the corresponding conductive pillar specifically comprises:
and spraying an adhesive layer at the bottom of each groove, adhering each chip with the corresponding groove, and connecting the bonding pad of the chip with the corresponding conductive column.
CN202011642597.1A 2020-12-31 2020-12-31 Fan-out type packaging structure integrated by three-dimensional heterogeneous and manufacturing method Pending CN112820712A (en)

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CN116169115A (en) * 2022-12-21 2023-05-26 惠州市金百泽电路科技有限公司 Embedded chip packaging module structure and manufacturing method thereof

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CN109860065A (en) * 2019-02-14 2019-06-07 南通通富微电子有限公司 A kind of fan-out package method
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CN107452689A (en) * 2017-09-14 2017-12-08 厦门大学 The embedded fan-out-type silicon pinboard and preparation method of three-dimensional systematic package application
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