CN112805958A

CN112805958A - Time synchronization method and device

Info

Publication number: CN112805958A
Application number: CN201980065832.2A
Authority: CN
Inventors: 傅健新
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-01-18
Filing date: 2019-01-18
Publication date: 2021-05-14
Anticipated expiration: 2039-01-18
Also published as: CN112805958B; WO2020147108A1

Abstract

A time synchronization method and a device relate to the technical field of communication and are used for improving the synchronization performance of a time interface and ensuring lower implementation cost, power consumption and complexity. The method comprises the following steps: in the NPPS signal and the TOD signal sent by the first device to the second device, the time value corresponding to the rising/falling edge of the NPPS includes a time value less than a second, and the TOD signal can carry the time value less than the second, so that the second device can realize time synchronization based on the time value less than the second when receiving the NPPS signal and the TOD signal, thereby improving the accuracy of time synchronization, and simultaneously reducing the cost, power consumption and complexity in circuit implementation.

Description

Time synchronization method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for time synchronization.

Background

There is a continuing need in the field of communications for time synchronization, which may refer to setting times of multiple devices communicating with each other to coincide, for example, setting times of multiple devices communicating with each other to coincide with a time source on a network, where the time source may be provided by a reliable device in the network, such as a GPS satellite or a time server. When time synchronization is performed between the devices, the sending end device can output a time value corresponding to a certain moment through a standard time interface, the receiving end device obtains the corresponding time value through analysis, and the time synchronization between the devices is realized based on the time value obtained through analysis.

In the prior art, a standard time interface generally comprises: pulse per second (1 PPS) + time of day (TOD) interface and Direct Current Level Shift (DCLS) interface. In the protocol definition, the two time interfaces output the time information once per second, and the minimum unit of the output time information is second, so that the time synchronization can be carried out only at the time of the whole second. In addition, based on the above protocol definition, the two time interfaces have the following problems in terms of circuit implementation: the digital circuit is difficult to control the time of each output to be the time of the whole second, so that certain deviation exists between the output time and the actual time; the analog circuit can realize accurate output at the time of a whole second, but has high cost, large power consumption and high realization complexity. Therefore, how to improve the synchronization performance of the time interface and ensure that the implementation cost, power consumption and complexity are low is a key issue.

Disclosure of Invention

Embodiments of the present application provide a method and an apparatus for time synchronization, which are used to improve synchronization performance of a time interface and ensure lower implementation cost, power consumption, and complexity.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in a first aspect, a method for time synchronization is provided, the method comprising: the first device generates an NPPS signal and a TOD signal of time of day, wherein the NPPS signal is generated for N times per second, the TOD signal is used for carrying time values corresponding to rising/falling edges of the NPPS signal, the time values corresponding to the rising/falling edges comprise time values smaller than second, and N is an integer larger than 1; the first device transmits the NPPS signal and the TOD signal to the second device to synchronize the second device with the time of the first device. In the above technical solution, the minimum time unit of the time value carried by the TOD signal may be less than a second, so that the accuracy of the time value in the time synchronization process can be improved; in addition, when the NPPS signal and the TOD signal are transmitted through the digital circuit, although the clock of the digital circuit is not ideal, which may cause the time value corresponding to the rising/falling edge of the NPPS to include a time value less than a second, because the TOD signal can carry the time value less than the second, the time value corresponding to the rising/falling edge of the NPPS can be directly output, thereby avoiding the problem of deviation between the output time and the actual time, and meanwhile, the digital circuit has a simpler structure, and is lower in implementation cost, power consumption and complexity, so that the synchronization performance of the time interface can be improved.

In one possible implementation form of the first aspect, the time value of less than a second includes at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal. In the possible implementation manner, the time synchronization of millisecond, microsecond, nanosecond and/or nanosecond is realized, so that the accuracy of the time value in the time synchronization process is improved.

In a possible implementation manner of the first aspect, the time value of the TOD bearer corresponds to a time value corresponding to a rising/falling edge of the NPPS in a one-to-one manner. In the possible implementation manner, the flexibility of the time value carried by the TOD can be improved, so that the cost, the power consumption and the complexity are lower in circuit implementation.

In a possible implementation manner of the first aspect, the TOD signal is further configured to carry a first delay, where the first delay includes at least one of a transmission delay inside the first device or a transmission delay between the first device and the second device, that is, the first device may carry the first delay on the TOD signal after superimposing the first delay and a time value corresponding to a rising edge and a falling edge of the NPPS signal, so as to implement compensation of the transmission delay. In the possible implementation manner, a simple and effective method for compensating the delay is provided, and the problem of high complexity in circuit implementation is not caused.

In a second aspect, a method for time synchronization is provided, the method comprising: the second device receives N times of pulse NPPS signals and time of day TOD signals sent by the first device, wherein the TOD signals are used for bearing time values corresponding to rising/falling edges of the NPPS signals, the time values comprise time values smaller than seconds, and N is an integer larger than 1; the second device synchronizes the second device with the first device in time according to the NPPS signal and the TOD signal. In the above technical solution, a minimum time unit of a time value corresponding to a rising/falling edge of an NPPS signal carried by the TOD signal may be less than a second, so that accuracy of the time value in a time synchronization process can be improved; in addition, when the NPPS signal and the TOD signal are transmitted through the digital circuit, although the clock of the digital circuit is not ideal, which may cause the time value corresponding to the rising/falling edge of the NPPS to include a time value less than a second, because the TOD signal can also bear the time value less than the second, the time value corresponding to the rising/falling edge of the NPPS can be directly output, thereby avoiding the problem of deviation between the output time and the actual time, and meanwhile, the digital circuit has a simpler structure, and is lower in implementation cost, power consumption and complexity, so that the synchronization performance of the time interface can be improved.

In one possible implementation of the second aspect, the time information of less than a second includes at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal. In the possible implementation manner, the time synchronization of millisecond, microsecond, nanosecond and/or nanosecond is realized, so that the accuracy of the time value in the time synchronization process is improved.

In a possible implementation manner of the second aspect, the time value of the TOD bearer corresponds to a time value corresponding to a rising/falling edge of the NPPS in a one-to-one manner. In the possible implementation manner, the flexibility of the time value carried by the TOD can be improved, so that the cost, the power consumption and the complexity are lower in circuit implementation.

In a possible implementation manner of the second aspect, the TOD signal is further configured to carry a first delay, where the first delay includes at least one of a transmission delay inside the first device or a transmission delay between the first device and the second device, that is, the first device may carry the first delay on the TOD signal after superimposing the first delay and a time value corresponding to a rising edge and a falling edge of the NPPS signal, so as to implement compensation of the transmission delay. In the possible implementation manner, a simple and effective method for compensating the delay is provided, and the problem of high complexity in circuit implementation is not caused.

In a third aspect, an apparatus for time synchronization is provided, the apparatus comprising: the processing unit is used for generating N pulses per second NPPS signals and time of day TOD signals, the TOD signals are used for bearing time values corresponding to rising/falling edges of the NPPS signals, the time values comprise time values smaller than second, and N is an integer larger than 1; a transmitting unit for transmitting the NPPS signal and the TOD signal to the second device so that the second device is time-synchronized with the apparatus.

In one possible implementation manner of the third aspect, the time information less than a second includes at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal.

In a possible implementation manner of the third aspect, the time value of the TOD bearer corresponds to a time value corresponding to a rising/falling edge of the NPPS in a one-to-one manner.

In a possible implementation manner of the third aspect, the TOD signal is further configured to carry a first delay, where the first delay includes at least one of a transmission delay inside the apparatus or a transmission delay between the apparatus and the second device.

In a fourth aspect, an apparatus for time synchronization is provided, the apparatus comprising: a receiving unit, configured to receive an NPPS signal and a TOD signal, which are sent by a first device, of pulses N times per second, where the TOD signal is used to carry a time value corresponding to a rising/falling edge of the NPPS signal, the time value includes a time value smaller than a second, and N is an integer greater than 1; and the processing unit is used for synchronizing the device with the time of the first equipment according to the NPPS signal and the TOD signal.

In one possible implementation manner of the fourth aspect, the time information less than a second includes at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal.

In a possible implementation manner of the fourth aspect, the time information carried by the TOD corresponds to a time value corresponding to a rising/falling edge of the NPPS in a one-to-one manner.

In a possible implementation manner of the fourth aspect, if there is a transmission delay of the first delay inside the first device or there is a transmission delay of the first delay between the first device and the apparatus, the TOD signal is further used to carry the first delay.

In a fifth aspect, a method for time synchronization is provided, the method comprising: the first device generates a direct current level conversion N-DCLS signal for N times per second, wherein each DCLS signal comprises W code elements, the W code elements are used for carrying time values corresponding to rising/falling edges of a first reference code element in the W code elements, the time values corresponding to the rising/falling edges comprise time values smaller than second, and N is an integer larger than 1; the first device transmits an N-DCLS signal to the second device to synchronize the second device with the time of the first device. In the above technical solution, the minimum time unit of the time value carried by the W code elements may be less than a second, so that the accuracy of the time value in the time synchronization process can be improved; in addition, when the N-DCLS signal is sent through the digital circuit, although the clock of the digital circuit is not ideal, which may cause the time value corresponding to the rising/falling edge of the first reference symbol to include a time value smaller than a second, since the W symbols can carry the time value smaller than the second, the time value corresponding to the rising/falling edge of the first reference symbol may be directly output, thereby avoiding the problem of deviation between the output time and the actual time, and meanwhile, the digital circuit has a simpler structure, and is lower in implementation cost, power consumption and complexity, so that the synchronization performance of the time interface can be improved.

In a possible implementation manner of the fifth aspect, W is an integer greater than 100, and a symbol of the W symbols before dividing by the first 100 symbols is used to carry the time value less than the second; optionally, the W symbols are 100 × M symbols, and M is an integer greater than 1. The implementation manner provided for bearing the time value less than the second can be compatible with the existing manner of implementing time synchronization by using the DCLS signal 1 time per second.

In one possible implementation of the fifth aspect, the time value of less than a second comprises at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal. In the possible implementation manner, the time synchronization of millisecond, microsecond, nanosecond and/or nanosecond is realized, so that the accuracy of the time value in the time synchronization process is improved.

In a possible implementation manner of the fifth aspect, the other symbols of the W symbols except the first reference symbol are used to carry time values corresponding to rising/falling edges of the first reference symbol. In the possible implementation manner, the flexibility of the time value carried by the W code elements can be improved, so that the cost, the power consumption and the complexity are lower in circuit implementation.

In a possible implementation manner of the fifth aspect, the N-DCLS signal is further configured to carry a first delay, where the first delay includes at least one of a transmission delay inside the first device or a transmission delay between the first device and the second device, that is, the first device may carry the first delay on the N-DCLS signal after superimposing the first delay with a time value corresponding to a rising edge and a falling edge of the first reference symbol, so as to implement compensation of the transmission delay. In the possible implementation manner, a simple and effective method for compensating the delay is provided, and the problem of high complexity in circuit implementation is not caused.

In a sixth aspect, a method of time synchronization is provided, the method comprising: the second device receives a direct current level conversion N-DCLS signal sent by the first device every second for N times, each DCLS signal comprises W code elements, the W code elements are used for carrying time values corresponding to rising/falling edges of first reference code elements in the W code elements, the time values corresponding to the rising/falling edges comprise time values smaller than the second, and N is an integer larger than 1; the second device synchronizes the second device with the time of the first device according to the N-DCLS signal. In the above technical solution, the minimum time unit of the time value carried by the W code elements may be less than a second, so that the accuracy of the time value in the time synchronization process can be improved; in addition, when the N-DCLS signal is sent through the digital circuit, although the clock of the digital circuit is not ideal, which may cause the time value corresponding to the rising/falling edge of the first reference symbol to include a time value smaller than a second, since the W symbols can carry the time value smaller than the second, the time value corresponding to the rising/falling edge of the first reference symbol may be directly output, thereby avoiding the problem of deviation between the output time and the actual time, and meanwhile, the digital circuit has a simpler structure, and is lower in implementation cost, power consumption and complexity, so that the synchronization performance of the time interface can be improved.

In a possible implementation manner of the sixth aspect, W is an integer greater than 100, and a symbol of the W symbols before dividing by the first 100 symbols is used to carry the time value less than the second; optionally, the W symbols are 100 × M symbols, and M is an integer greater than 1. The implementation manner provided for bearing the time value less than the second can be compatible with the existing manner of implementing time synchronization by using the DCLS signal 1 time per second.

In one possible implementation of the sixth aspect, the time value of less than a second includes at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal. In the possible implementation manner, the time synchronization of millisecond, microsecond, nanosecond and/or nanosecond is realized, so that the accuracy of the time value in the time synchronization process is improved.

In a possible implementation manner of the sixth aspect, the other symbols of the W symbols except the first reference symbol are used to carry time values corresponding to rising/falling edges of the first reference symbol. In the possible implementation manner, the flexibility of the time value carried by the W code elements can be improved, so that the cost, the power consumption and the complexity are lower in circuit implementation.

In a possible implementation manner of the sixth aspect, the N-DCLS signal is further configured to carry a first delay, where the first delay includes at least one of a transmission delay inside the first device or a transmission delay between the first device and the second device, that is, the first device may carry the first delay on the N-DCLS signal after superimposing the first delay and a time value corresponding to a rising edge and a falling edge of the first reference symbol, so as to implement compensation of the transmission delay. In the possible implementation manner, a simple and effective method for compensating the delay is provided, and the problem of high complexity in circuit implementation is not caused.

In a seventh aspect, an apparatus for time synchronization is provided, the apparatus comprising: the processing unit is used for generating a direct current level conversion N-DCLS signal for N times per second, wherein each DCLS signal comprises W code elements, the W code elements are used for carrying time values corresponding to rising/falling edges of a first reference code element in the W code elements, the time values corresponding to the rising/falling edges comprise time values smaller than second, and N is an integer larger than 1; a transmitting unit for transmitting the N-DCLS signal to the second device so that the second device is synchronized with the time of the apparatus.

In a possible implementation manner of the seventh aspect, W is an integer greater than 100, and a symbol of the W symbols before dividing by the first 100 symbols is used to carry the time value less than the second; optionally, the W symbols are 100 × M symbols, and M is an integer greater than 1.

In one possible implementation of the seventh aspect, the time value of less than a second includes at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal.

In a possible implementation manner of the seventh aspect, the other symbols of the W symbols except the first reference symbol are used to carry time values corresponding to rising/falling edges of the first reference symbol.

In a possible implementation manner of the seventh aspect, the N-DCLS signal is further configured to carry a first delay, where the first delay includes at least one of a transmission delay inside the apparatus or a transmission delay between the apparatus and the second device.

In an eighth aspect, there is provided an apparatus for time synchronization, the apparatus comprising: a receiving unit, configured to receive an N-level converted dc-dc ls signal sent by a first device N times per second, where each DCLS signal includes W symbols, where the W symbols are used to carry time values corresponding to rising/falling edges of a first reference symbol in the W symbols, the time values corresponding to the rising/falling edges include time values smaller than a second, and N is an integer greater than 1; a processing unit for time synchronizing the apparatus with the first device based on the N-DCLS signal.

In a possible implementation manner of the eighth aspect, W is an integer greater than 100, and a symbol of the W symbols before dividing by the first 100 symbols is used to carry the time value less than the second; optionally, the W symbols are 100 × M symbols, and M is an integer greater than 1.

In one possible implementation of the eighth aspect, the time value of less than a second includes at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal.

In a possible implementation manner of the eighth aspect, the other symbols of the W symbols except the first reference symbol are used to carry time values corresponding to rising/falling edges of the first reference symbol.

In a possible implementation manner of the eighth aspect, the N-DCLS signal is further configured to carry a first delay, where the first delay includes at least one of a transmission delay inside the first device or a transmission delay between the first device and the apparatus.

In yet another aspect of the present application, a system for time synchronization is provided, the system comprising a first device and a second device; the first device is a time synchronization apparatus provided in any possible implementation manner of the third aspect or the third aspect, and the second device is a time synchronization apparatus provided in any possible implementation manner of the fourth aspect or the fourth aspect; or, the first device is a time synchronization apparatus provided in any possible implementation manner of the seventh aspect or the seventh aspect, and the second device is a time synchronization apparatus provided in any possible implementation manner of the eighth aspect or the eighth aspect.

It can be understood that the apparatus of any one of the time synchronization methods provided above is used for executing the corresponding method provided above, and therefore, the beneficial effects achieved by the apparatus can refer to the beneficial effects in the corresponding method provided above, and are not described herein again.

Drawings

Fig. 1 is a schematic structural diagram of a communication system according to an embodiment of the present application;

fig. 2 is a schematic diagram of a 1PPS + TOD interface according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a DCLS interface according to an embodiment of the present disclosure;

fig. 4 is a flowchart illustrating a method for time synchronization according to an embodiment of the present application;

fig. 5 is a schematic diagram of a first time interface according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a frame structure according to an embodiment of the present application;

fig. 7 is a schematic flowchart of another method for time synchronization according to an embodiment of the present application;

fig. 8 is a first schematic structural diagram of a time synchronization apparatus according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a time synchronization apparatus according to an embodiment of the present application.

Detailed Description

In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c or a-b-c, wherein a, b and c can be single or multiple. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. In addition, in the embodiments of the present application, the words "first", "second", and the like do not limit the number and the execution order.

It is noted that, in the present application, words such as "exemplary" or "for example" are used to mean exemplary, illustrative, or descriptive. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

Fig. 1 is a schematic structural diagram of a communication system according to an embodiment of the present application, and referring to fig. 1, the communication system includes a first device and a second device, and the first device and the second device perform time synchronization using a time interface. The first device and the second device are connected by a wired manner, for example, the first device and the second device are connected by a cable. In practical applications, the first device and the second device may be network elements in a network (for example, the first device and the second device are two terminals in the network), or may be test meters in a time synchronization performance test (for example, the first device is a network element, and the second device is a test meter for testing the time synchronization performance of the first device), and the like.

The time interface may refer to an interface for performing time synchronization, and for example, the time interface may include a pulse per second (1 PPS) + time of day (TOD) interface, a Direct Current Level Shift (DCLS) interface, and the like. The following takes an example of sending a time value from the first device to the second device as an example, and respectively illustrates the 1PPS + TOD interface and the DCLS interface.

1PPS + TOD interface: the time value is transmitted through two signal lines including a signal line for transmitting a 1PPS signal) and a signal line for transmitting a TOD signal, where TOD is a timing manner. As shown in fig. 2, the 1PPS signal is a 1Hz signal, i.e. one pulse is sent per second, and the rising edge of the 1PPS signal is used to represent the whole second moment of the first device; the TOD signal is used to carry a time value (in seconds) corresponding to a rising edge of the 1PPS signal, for example, the time value corresponding to the rising edge of the 1PPS signal is xxxx year xx month xx day xx minute xx second. The TOD signal is in high level when no data is transmitted; when data is transmitted, each byte contains 8 bits, each byte takes 1 bit "0" as a starting bit, 1 bit "1" as an ending bit, and 8 bits of data are in the middle. The baud rate of the TOD signal can support 9600, 19200, 38400 and the like, and the level width of each bit can comply with the baud rate agreed by the equipment at the transmitting and receiving ends. In fig. 2, the high-level pulse width of the 1PPS signal is 20ms to 200ms, the time information carried by the TOD signal corresponding to the rising edge of the 1PPS signal is greater than 1ms between the start position and the rising edge, and the length of the time value transmitted each time is less than 500 ms.

It should be noted that the frame structure of the TOD may include a frame header 1, a frame header 2, a message class, a message ID, a message length field, a payload field, and a check field (specifically, as shown in fig. 5 below), where the length of the payload field may be 16 bytes, and the description about the 16 bytes may refer to the description about the first 16 bytes shown in table 2 below, which is not described herein again in this embodiment of the present application.

DCLS interface: the time information is transmitted through one signal line for transmitting the DCLS signal. As shown in fig. 3, the DCLS interface may transmit 100 symbols per second, each symbol having a time width of 10ms, each symbol representing different information at different duty cycles. Wherein, 8ms:2ms (i.e. the high-low level ratio is 4) represents a reference symbol (also called a reference symbol), 5ms:5ms (i.e. the high-low level ratio is 1) represents data 1, and 2ms:8ms (i.e. the high-low level ratio is 1/4) represents data 0. Wherein the first symbol and the last symbol in 100 symbols transmitted per second have a duty cycle of 8ms:2ms, i.e. the first symbol and the last symbol are both reference symbols. When time is expressed, the rising edge of the first reference symbol per second represents the time of the first device in whole second, and the time of the first device corresponding to the time is carried by other symbols except the reference symbol in the second. Wherein, the description about the symbol definition and definition of 100 symbols transmitted per second can refer to the related description in the prior art, which is not set forth in the embodiments of the present application.

Fig. 4 is a flowchart illustrating a method for time synchronization according to an embodiment of the present application, and referring to fig. 4, the method includes the following steps.

S401: the first device generates an N Pulse Per Second (NPPS) signal and a time of day (TOD) signal, the TOD signal being used to carry time values corresponding to rising/falling edges of the NPPS signal, the time values corresponding to the rising/falling edges including time values less than a second, and N being an integer greater than 1.

The NPPS signal is an N Hz signal, that is, N pulses are transmitted every second, for example, N ═ 2 indicates that pulses are transmitted twice every second, and N ═ 3 indicates that pulses are transmitted 3 times every second. The TOD signal is used to carry a time value corresponding to a rising/falling edge of the NPPS signal, that is, the TOD signal may be used to indicate a time value corresponding to a rising edge of the NPPS signal, and may also be used to indicate a time value corresponding to a falling edge of the NPPS signal, and it is specifically indicated that the time value corresponding to the rising edge or the time value corresponding to the falling edge may be agreed in advance by the first device and the second device.

It should be noted that, in practical applications, the value of N may also be equal to 1, that is, 1pulse is sent every second, but the interval for performing time synchronization is only 1 second, and the interval for performing time synchronization when N is an integer greater than 1 is 1/N, so that the frequency of time synchronization can be increased compared to the case where N is equal to 1, and the performance of time synchronization can be improved.

In addition, the time value corresponding to the rising/falling edge of the NPPS signal includes a time value smaller than second, that is, the minimum time unit of the time value carried by the TOD signal may be smaller than second, for example, the minimum time unit may be millisecond (ms), microsecond (us), nanosecond (ns), or nanosecond decimal (ns decimal), so that the time value carried by the TOD signal may be a time value including ms, us, ns, or ns decimal, for example, the time value may be 14 milliseconds, 00 minutes, 23 seconds, 12 hours at 06/2008.

The TOD signal is used for carrying a time value corresponding to a rising/falling edge of the NPPS signal, when the time value corresponding to the rising/falling edge of the NPPS signal is a whole second value, the time value carried by the TOD signal can be the whole second value, and the time value smaller than the second is 0; when the time value corresponding to the rising/falling edge of the NPPS signal is a non-integer second value (for example, time information including ns or a fraction of ns), the time value carried by the TOD signal may also be a non-integer second value, and at this time, the time information smaller than a second is not 0.

Specifically, the time value carried by the TOD signal corresponds to the time value corresponding to the rising/falling edge of the NPPS signal, i.e., each time value carried by the TOD signal is used to indicate the time value corresponding to a different rising/falling edge of the NPPS signal. Fig. 5 is a schematic diagram of an NPPS signal and a TOD signal, where (a) in fig. 5 shows that a time value carried by the TOD signal corresponds to a time value corresponding to a falling edge of the NPPS signal, and (b) in fig. 5 shows that a time value carried by the TOD signal corresponds to a time value corresponding to a rising edge of the NPPS signal. The TOD signal is high level when no data is transmitted; when data is transmitted, each byte contains 8 bits, each byte takes 1 bit "0" as a starting bit, 1 bit "1" as an ending bit, and 8 bits of data are in the middle. In the embodiment of the present application, the high-level pulse width of the NPPS signal, the time width between the start position of the time value carried by the TOD signal corresponding to the rising/falling edge of the NPPS signal and the rising/falling edge, and the length of the time value sent each time are not specifically limited, as long as the implementation of the above method can be ensured.

The frame structure of the TOD signal may be as shown in fig. 6, where the frame structure includes a frame header 1, a frame header 2, a message class, a message ID, a message length field, a payload field, and a check range of the check field may be from the message class to the payload field. Wherein the payload field may include 21 bytes, such as 16 th to 19 th bytes may be used to represent nanosecond integers and 20 th to 21 th bytes may be used to represent nanosecond decimals. The payload field may also include more or less bytes in actual use as long as time information less than a second can be expressed. The following table 1 explains the definition of a partial byte by taking an example that the payload field includes 21 bytes, and the description of the bytes with byte offset of 5-12 in table 1 can specifically refer to the related description in the prior art, which is not set forth in the embodiments of the present application.

TABLE 1

It should be noted that, the above description only illustrates the definitions of the 16 th to 21 st bytes in the payload field, and does not limit the embodiments of the present application. In addition, for the detailed description of the frame structure, reference may be made to related technologies, and the embodiments of the present application are not described herein again.

S402: the first device transmits the NPPS signal and the TOD signal to the second device.

S403: the second device receives the NPPS signal and the TOD signal transmitted by the first device. The NPPS signal and the TOD signal in S403 are the same as the NPPS signal and the TOD signal in S401, for specific reference, the description in S401 is referred to, and the embodiments of the present application are not repeated herein.

When the second device receives the NPPS signal and the TOD signal sent by the first device, the second device may analyze the NPPS signal and the TOD signal to obtain a time value corresponding to a rising/falling edge of the NPPS signal carried by the TOD signal. If the time value carried by the TOD signal and agreed in advance by the first device and the second device indicates a time value corresponding to the rising edge of the NPPS signal, the time value obtained by the second device through analysis may be the time value corresponding to the rising edge of the NPPS signal; if the time value carried by the TOD signal, which is indicated by the time value agreed in advance by the first device and the second device, is the time value corresponding to the falling edge of the NPPS signal, the time value analyzed by the second device may be the time value corresponding to the falling edge of the NPPS signal.

S404: the second device synchronizes the second device with the first device in time according to the NPPS signal and the TOD signal.

When the second device analyzes the time value corresponding to the falling edge of the NPPS signal, the second device may calibrate the local time of the second device according to the time value, for example, the second device calibrates the local time of the second device to be consistent with the time value corresponding to the falling edge of the NPPS signal, so as to implement time synchronization between the second device and the first device.

Further, when there is a transmission delay of the first delay inside the first device or there is a transmission delay of the first delay between the first device and the second device, the TOD signal is also used to carry the first delay, that is, a time value carried by the TOD signal may be a superposition of the first delay and a time value corresponding to a rising/falling edge of the NPPS. At this time, the first delay is compensated by the first device, that is, the first device adds the first delay and a time value corresponding to a rising/falling edge of the NPPS signal in advance, and then sends the time value carried by the TOD signal to the second device.

Or, the first time delay is compensated by the second device, that is, the time value corresponding to the rising/falling edge of the NPPS signal is consistent with the time value carried by the TOD signal, and after the second device obtains the time value carried by the TOD signal by analysis, the second device superimposes the first time delay and the time value carried by the TOD signal, and performs time synchronization by using the time value obtained after the superimposition. For example, the time value (i.e. local time) corresponding to the falling edge of the NPPS signal sent by the first device is: at the time of 100ms per 1 second, the TOD signal carries the information of 100ms per 1 second, if the transmission path delay between the first device and the second device is 100ns (i.e. the first delay is 100ns), when the second device performs time synchronization, the second device needs to add the time value "100 ms per 1 second" carried by the TOD signal to the first delay "100 ns" and set its own local time to be consistent with the added time value "100 ms per 1 second", i.e. when the falling edge of the NPPS signal reaches the second device, the local time of the first device is "100 ms per 1 second 100 ns".

In this embodiment of the present application, the minimum time unit of the time value carried by the TOD signal may be less than a second, so as to improve the accuracy of the time value in the time synchronization process. In addition, when the scheme is implemented by a digital circuit, although the clock of the digital circuit is not ideal, the deviation between the actual timing step and the theoretical timing step may be caused due to network jitter or temperature drift (for example, taking a clock of 1GHz as an example, the theoretical timing step is 1ns, and the actual timing step may be 0.95ns), and further the time value corresponding to the rising/falling edge of the NPPS includes a time value smaller than a second, but since the TOD signal can carry a time value smaller than a second, the time value corresponding to the rising/falling edge of the NPPS can be directly output, so that the problem that the output time is deviated from the actual time is avoided, and meanwhile, the structure of the digital circuit is relatively simple, and the implementation cost, the power consumption and the complexity are relatively low. Therefore, the method can improve the synchronization performance of the time interface.

Fig. 7 is a flowchart illustrating a method for time synchronization according to an embodiment of the present application, and referring to fig. 7, the method includes the following steps.

S701: the first device generates a DCLS (N-DCLS) signal N times per second, each DCLS signal including W symbols for carrying time values corresponding to rising/falling edges of a first reference symbol of the W symbols, the time values corresponding to the rising/falling edges including time values less than a second, N being an integer greater than 1.

For example, W may be an integer greater than 100, for example, W symbols may be 110 symbols, 120 symbols, 200 symbols, or 300 symbols, etc. Optionally, W symbols are equal to 100 × M symbols, M is a positive integer greater than 1, that is, the number of W symbols may be an integer multiple of 100, and in this embodiment, the example that W symbols are equal to 100 × M symbols is used as an example for description.

The DCLS signal is sent N times per second, that is, the DCLS signal is sent N times per second, for example, N ═ 2 indicates that the DCLS signal is sent twice per second, and N ═ 3 indicates that the DCLS signal is sent 3 times per second. Each transmitted DCLS signal may include 100 × M symbols, and the time width of each symbol is 10/(M × N) ms, for example, M ═ 2 indicates that each transmitted DCLS signal includes 200 symbols, and M ═ 3 indicates that each transmitted DCLS signal includes 300 symbols, and this embodiment of the present application does not limit specific values of M. Wherein each symbol represents different information with different duty cycles, and specifically, similar to the description in the above DCLS interface, the high-low level ratio is 4 to represent the reference symbol (also called reference symbol), the high-low level ratio is 1 to represent data 1, that is, the high-low level ratio is 1/4 to represent data 0. The high-low level ratio corresponding to the first symbol and the last symbol in 100 × M symbols transmitted each time is 4, that is, the first symbol and the last symbol are both reference symbols.

The W symbols are used to carry time values corresponding to rising/falling edges of a first reference symbol (i.e., a first base station symbol) in the W symbols, that is, the W symbols are used to carry time values corresponding to rising edges of the first reference symbol in the W symbols, and may also be used to carry time values corresponding to falling edges of the first reference symbol in the W symbols, where a specific indication is that a time value corresponding to a rising edge or a time value corresponding to a falling edge may be agreed in advance by the first device and the second device.

It should be noted that, in practical applications, the value of N may also be equal to 1, that is, 1 time per second, but the interval for performing time synchronization is only 1 second, and the interval for performing time synchronization when N is an integer greater than 1 is 1/N, so that the frequency of time synchronization can be increased compared to the case where N is equal to 1, and the performance of time synchronization can be improved.

In addition, the time value carried by the W symbols includes a time value smaller than second, that is, the minimum time unit of the time value carried by the W symbols may be smaller than second, for example, the minimum time unit may be ms, us, ns or ns decimal, and the like, so that the time value may be a time value including ms, us, ns or ns decimal, such as that the time value is 14 milliseconds at 12 hours 00 minutes 23 seconds at 06 days 12 of 04.2008.

The W symbols are used for carrying time values corresponding to rising/falling edges of a first reference symbol in the W symbols, when the time values corresponding to the rising/falling edges of the first reference symbol are full-second values, the time values carried by the W symbols may be full-second values, and at this time, time information smaller than second is 0; when the time value corresponding to the rising/falling edge of the first reference symbol is a non-integer-second value (for example, time information including ns or a fraction of ns), the time value carried by the W symbols may also be a non-integer-second value, and in this case, the time information smaller than a second is not 0.

Specifically, the other symbols (i.e., symbols representing data) of the 100 × M symbols except for the first reference symbol are used to carry the time value corresponding to the rising/falling edge of the first reference symbol. That is, 100 × M symbols transmitted each time can be used to transmit a time value, and of the 100 × M symbols transmitted each time, the other symbols (symbols used to represent data) except the first reference symbol are used to carry the time value corresponding to the rising/falling edge of the first reference symbol.

For convenience of understanding, the definition and description of the last 100 symbols (symbol numbers 100-. In the following table 2, the description is given by taking as an example that the nanosecond value includes 32 bytes (i.e., 0-31), the nanosecond decimal value includes 16 bytes (i.e., 0-15), and the symbols with the symbol numbers 160-199 are reserved symbols.

TABLE 2

Code element serial number	Definition of	Description of the invention
100	Index bit	Set to be 0 "
101～104	Nanosecond value 31:28]

…	…	…
136～139	Nanosecond value 3:0]
140	Index bit	Set to be 0 "
141～144	Nanosecond decimal value [15: 12%]
…	…	…
156～159	Nanosecond decimal value [3: 0%]
…	…	…
196～199	Retention

It should be noted that the above description only illustrates the definition of 100 symbols with the symbol number 100-.

S702: the first device transmits an N-DCLS signal to the second device.

S703: the second device receives the N-DCLS signal transmitted by the first device. The N-DCLS signal in S703 is the same as the N-DCLS signal in S7401, which is specifically referred to the description in S701, and the description of the embodiment of the present application is not repeated herein.

When the second device receives the N-DCLS signal sent by the first device, the second device may parse the N-DCLS signal to obtain a time value corresponding to a rising/falling edge of a first reference symbol in the W symbols carried by the W symbols. If the time value carried by the W symbols is agreed in advance by the first device and the second device to indicate the time value corresponding to the rising edge of the first reference symbol, the time value obtained by the second device through analysis may be the time value corresponding to the rising edge of the first reference symbol; if the time value carried by the W symbols is agreed in advance by the first device and the second device to indicate the time value corresponding to the falling edge of the first reference symbol, the time value analyzed by the second device may be the time value corresponding to the falling edge of the first reference symbol.

S704: the second device synchronizes the second device with the first device in time based on the N-DCLS signal.

When the second device analyzes to obtain the time value corresponding to the falling edge of the first reference symbol in the W symbols, the second device may calibrate the local time of the second device according to the time value, for example, the second device calibrates the local time of itself to be consistent with the time value corresponding to the falling edge of the first reference symbol in the W symbols, so as to implement time synchronization between the second device and the first device.

Further, if there is a transmission delay of the first delay inside the first device or there is a transmission delay of the first delay between the first device and the second device, the time value carried by the W symbols may be a superposition of the first delay and a time value corresponding to a rising/falling edge of the first reference symbol. At this time, the first delay is compensated by the first device, that is, the first device adds the first delay with the time value corresponding to the rising/falling edge of the first reference symbol in advance and then sends the time value carried by the W symbols to the second device.

Or, the first time delay is compensated by the second device, that is, the time value corresponding to the rising/falling edge of the first reference symbol is consistent with the time value carried by the W symbols, and after the second device analyzes the time value carried by the W symbols, the second device superimposes the first time delay and the time value carried by the W symbols to perform time synchronization. For example, the time value corresponding to the falling edge of the first symbol of the W symbols sent by the first device is: at the time of 100ms for 1 second, the W symbols carry the information of this "100 ms for 1 second", if the transmission path delay between the first device and the second device is 100ns (i.e. the first delay is 100ns), when the second device performs time synchronization, the second device needs to add the information value of "100 ms for 1 second" carried on the W symbols to the first delay "100 ns", and set its own local time to be consistent with the added time value of "100 ms for 1 second" 100ns ", i.e. when the falling edge of the first symbol in the W symbols reaches the second device, the local time of the first device is" 100ms for 1 second 100ns ".

In this embodiment of the present application, the minimum time unit of the time value carried by the W code elements may be less than a second, so that the accuracy of the time value in the time synchronization process can be improved. In addition, when the scheme is implemented by a digital circuit, although the clock of the digital circuit is not ideal, the deviation between the actual timing step and the theoretical timing step may be caused due to network jitter or temperature drift (for example, taking a clock of 1GHz as an example, the theoretical timing step is 1ns, and the actual timing step may be 0.95ns), and further, when the time value corresponding to the rising/falling edge of the first reference symbol is the non-whole-second time, since the W symbols can carry a time value smaller than a second, the time value corresponding to the rising/falling edge of the first reference symbol may be directly output, thereby avoiding the problem that the output time is deviated from the actual time, and meanwhile, the structure of the digital circuit is relatively simple, and the implementation cost, the power consumption and the complexity are relatively low. Therefore, the method can improve the synchronization performance of the time interface.

The above-mentioned solutions provided in the embodiments of the present application are mainly introduced from the perspective of device interaction, and it can be understood that, in order to implement the above-mentioned functions, the first device and the second device include hardware structures and/or software modules corresponding to the respective functions. Those of skill in the art would readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the first device and the second device may be divided into the functional modules according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The functional modules can be realized in a hardware form, and can also be realized in a software functional module form. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation.

In the case of dividing each functional module according to each function, fig. 8 shows a schematic diagram of a possible structure of the apparatus for time synchronization in the foregoing embodiment, where the apparatus may be a first device or a chip or a system on a chip in the first device, or a circuit, a module, or a unit in the first device for implementing the foregoing method embodiment. The device includes: a processing unit 801 and a transmitting unit 802. Wherein, the processing unit 801 is configured to support the apparatus to perform S401 in the foregoing method embodiment, or S701 in the foregoing method embodiment, and/or other technical processes described herein; the sending unit 802 is configured to support the apparatus to execute S402 in the foregoing method embodiment or S702 in the foregoing method embodiment.

In the case of dividing each functional module according to each function, fig. 9 shows a schematic structural diagram of a possible apparatus for time synchronization in the foregoing embodiment, where the apparatus may be a second device or a chip or a system on a chip in the second device, or may be a circuit, a module, or a unit in the second device for implementing the foregoing method embodiment. The device includes: a receiving unit 901 and a processing unit 902. Wherein, the receiving unit 901 is configured to support the apparatus to execute S403 in the foregoing method embodiment or S703 in the foregoing method embodiment; the processing unit 902 is configured to enable the apparatus to perform S404 in the above-mentioned method embodiment, or S704 in the above-mentioned method embodiment, and/or other technical processes described herein.

The embodiment of the application also provides a time synchronization system, which comprises a first device and a second device; wherein, the first device may be as described above with reference to fig. 8, for performing the steps of the first device in the above-described method embodiment; the second device may be as described above for fig. 9 for performing the steps of the second device in the above-described method embodiment.

In this embodiment of the present application, a minimum time unit of the time value sent by the first device may be less than a second, so that accuracy of the time information in a time synchronization process can be improved; in addition, when the scheme is realized through a digital circuit, the problem that the output time is deviated from the actual time can be avoided, and meanwhile, the digital circuit is simple in structure and low in realization cost, power consumption and complexity. Therefore, the scheme can improve the synchronization performance of the time interface.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical functional division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another device, or some features may be omitted, or not executed.

The units described as separate parts may or may not be physically separate, and parts displayed as units may be one physical unit or a plurality of physical units, that is, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

Finally, it should be noted that: the above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A method of time synchronization, the method comprising:

the method comprises the steps that a first device generates an NPPS signal and a TOD signal of time of day, wherein the NPPS signal is used for carrying time values corresponding to rising/falling edges of the NPPS signal, the time values comprise time values smaller than seconds, and N is an integer larger than 1;

the first device transmits the NPPS signal and the TOD signal to a second device to synchronize the second device with a time of the first device.
The method of claim 1, wherein the time value of less than a second comprises at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal.
The method of claim 1 or 2, wherein the TOD signal carries time values corresponding to rising/falling edges of the NPPS signal.
The method according to any of claims 1-3, wherein the TOD signal is further configured to carry a first time delay, the first time delay comprising at least one of a transmission time delay internal to the first device or a transmission time delay between the first device and the second device.
A method of time synchronization, the method comprising:

the method comprises the steps that a second device receives N times of pulse NPPS signals and time-of-day TOD signals sent by a first device, wherein the TOD signals are used for bearing time values corresponding to rising/falling edges of the NPPS signals, the time values comprise time values smaller than seconds, and N is an integer larger than 1;

the second device synchronizes the time of the second device with the time of the first device according to the NPPS signal and the TOD signal.
The method of claim 5, wherein the time value of less than a second comprises at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal.
The method of claim 5 or 6, wherein the TOD signal carries time values corresponding to rising/falling edges of the NPPS signal.
The method according to any of claims 5-7, wherein the TOD signal is further configured to carry a first time delay, and wherein the first time delay comprises at least one of a transmission time delay inside the first device or a transmission time delay between the first device and the second device.
An apparatus for time synchronization, the apparatus comprising:

the device comprises a processing unit, a processing unit and a control unit, wherein the processing unit is used for generating an NPPS signal and a TOD signal of time of day, the NPPS signal is used for carrying time values corresponding to rising/falling edges of the NPPS signal, the time values comprise time values smaller than seconds, and N is an integer larger than 1;

a transmitting unit, configured to transmit the NPPS signal and the TOD signal to a second device, so that the second device is time-synchronized with the apparatus.
The apparatus of claim 9, wherein the time value of less than a second comprises at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal.
The apparatus of claim 9 or 10, wherein the TOD signal carries time values corresponding to rising/falling edges of the NPPS signal in a one-to-one correspondence.
The apparatus of claim 11, wherein the TOD signal is further configured to carry a first delay, and wherein the first delay comprises at least one of a transmission delay internal to the apparatus or a transmission delay between the apparatus and the second device.
An apparatus for time synchronization, the apparatus comprising:

a receiving unit, configured to receive an NPPS signal and a TOD signal, which are sent by a first device, of pulses N times per second, where the TOD signal is used to carry a time value corresponding to a rising/falling edge of the NPPS signal, the time value includes a time value smaller than a second, and N is an integer greater than 1;

a processing unit, configured to synchronize the apparatus with the time of the first device according to the NPPS signal and the TOD signal.
The apparatus of claim 13, wherein the time value of less than a second comprises at least one of: a millisecond, microsecond, nanosecond, or nanosecond decimal.
The apparatus of claim 13 or 14, wherein the TOD signal carries time values corresponding to rising/falling edges of the NPPS signal in a one-to-one correspondence.
The apparatus of any of claims 13-15, wherein the TOD signal is further configured to carry a first delay, and wherein the first delay comprises at least one of a transmission delay internal to the first device or a transmission delay between the first device and the apparatus.
A system for time synchronization, comprising a first device and a second device, wherein the first device is the apparatus for time synchronization according to any one of claims 9-12, and the second device is the apparatus for time synchronization according to any one of claims 13-16.