CN113794529A

CN113794529A - Clock synchronization system

Info

Publication number: CN113794529A
Application number: CN202111063313.8A
Authority: CN
Inventors: 韩叶祥; 钱俊波; 王宏飞; 姜明武
Original assignee: Suzhou Guangge Technology Co Ltd
Current assignee: Suzhou Guangge Technology Co Ltd
Priority date: 2021-09-10
Filing date: 2021-09-10
Publication date: 2021-12-14

Abstract

The present application relates to a clock synchronization system. The system comprises: at least one first device configured for clock synchronization by a global positioning system and a time synchronization protocol; at least one second device configured to perform clock synchronization by a time synchronization protocol; at least one first device and at least one second device are sequentially connected through a network interface, the first device performs clock synchronization through the global positioning system, and the second device connected with the first device takes a clock synchronized by the first device as a master clock source; when at least one second device is connected behind the second device, the clock synchronized by more than one second device is used as a main clock source for clock synchronization of each second device until the clock synchronization of all the second devices is completed. By adopting the system, a high-precision clock synchronization mode of the equipment can be realized step by step.

Description

Clock synchronization system

Technical Field

The application relates to the technical field of power detection, in particular to a clock synchronization system.

Background

With the development of power detection technology, an NTP ethernet time service mode appears, and a general NTP ethernet time service mode only has millisecond-level synchronization precision, but in applications of long-distance power transmission line fault location, hidden danger positioning and the like, monitoring equipment deployed at a line terminal is required to have an accurate synchronous clock source, so that the NTP ethernet time service mode is far from meeting the requirement of accurate positioning.

Based on this, a GNSS synchronous clock source is generally adopted in the occasions where the outdoor wireless communication is good, and a PTP fiber synchronous clock source is generally adopted in the occasions such as a cable tunnel. However, due to the complexity of the laying environment of each local power transmission line, especially for the mixed lines, the same kind of clock source is difficult to be applied. Therefore, a multi-source reliable high-precision synchronization mode is designed for the monitoring devices, and the unified clock source has important significance.

Disclosure of Invention

In view of the above, it is necessary to provide a clock synchronization system capable of synchronizing clocks of different devices step by step.

A clock synchronization system, the clock synchronization system comprising:

at least one first device configured for clock synchronization by a global positioning system and a time synchronization protocol;

at least one second device configured to perform clock synchronization by a time synchronization protocol;

the first device and the second device are sequentially connected through a network interface, the first device performs clock synchronization through the global positioning system, and the first device takes a clock synchronized through the global positioning system as a master clock source of the second device connected with the first device behind;

and when at least one second device is connected behind the second device, the second device connected with the first device performs clock synchronization on the clock of the next second device according to the master clock source, and the clock synchronized by the next second device is used as a master clock source to continue performing clock synchronization on the second devices connected in sequence until the clock synchronization of all the second devices is completed.

In one embodiment, the first device is a device disposed above ground and the second device is a device disposed below ground.

In one embodiment, the first device includes a global positioning system and a first crystal oscillator, and the first device performs clock synchronization through a signal sent by the global positioning system and a signal output by the first crystal oscillator.

In one embodiment, the first device further includes a first clock synchronization module, a second clock synchronization module, and at least one first slave clock source module; the input end of the first clock synchronization module is connected with the first output end of the global positioning system, the output ends of the first clock synchronization module are respectively connected with the first input end of at least one first slave clock source module, the input end of the second clock synchronization module is connected with the second output end of the global positioning system, and the output end of the second clock synchronization module is connected with the input end of the first crystal oscillator;

the first clock synchronization module is used for reading and analyzing the global positioning system message and sending a timestamp of the analyzed first message to at least one first slave clock source module; the second clock synchronization module is used for correcting the frequency error of the first crystal oscillator, and the first crystal oscillator is used for respectively sending first relative timestamps to at least one first slave clock source module after the second clock synchronization module corrects the frequency error.

In one embodiment, the first clock synchronization module includes a first interrupt unit and a first information processing unit; the input end of the first interrupt unit is connected with the first output end of the global positioning system, the output end of the first interrupt unit is connected with the input end of the first information processing unit, and the output end of the first information processing unit is respectively connected with the first input end of at least one first slave clock source module;

the first interrupt unit is used for interrupting a pulse signal sent by the global positioning system, the first information processing unit is used for reading a message carried in the pulse signal, analyzing the message to obtain a first message timestamp, latching the first message timestamp, and respectively sending the first message timestamp to at least one first slave clock source module.

In one embodiment, the second clock synchronization module comprises a first listening unit and a first data processing unit; the input end of the first monitoring unit is connected with the second output end of the global positioning system, the first output end of the first monitoring unit is connected with the control end of the first interrupt unit, the second output end of the first monitoring unit is connected with the input end of the first data processing unit, and the output end of the first data processing unit is connected with the input end of the first crystal oscillator;

the first monitoring unit is used for judging whether the global positioning system sends out a pulse signal and controlling the first interruption unit to implement interruption operation, and the first data processing unit is used for calculating and correcting the frequency error of the first crystal oscillator according to the pulse signal sent by the global positioning system.

In one embodiment, the second device includes a master clock source module, a second slave clock source module, and a second crystal oscillator, and the second device performs clock synchronization through a signal sent by the master clock source module after synchronization and a signal output by the second crystal oscillator;

the master clock source module is configured to receive a synchronization timestamp sent by the first device or a previous second device, and perform clock synchronization on the second slave clock source module according to the synchronization timestamp and a signal output by the second oscillator.

In one embodiment, the second device further comprises a third clock synchronization module and a fourth clock synchronization module; the input end of the third clock synchronization module is connected with the first output end of the master clock source module, the output end of the third clock synchronization module is connected with the first input end of the second slave clock source module, the input end of the fourth clock synchronization module is connected with the second output end of the master clock source module, and the output end of the fourth clock synchronization module is connected with the input end of the second crystal oscillator;

the third clock synchronization module is used for reading and latching a second message timestamp, and sending the latched second message timestamp to a second slave clock source module; the fourth clock synchronization module is configured to correct a frequency error of the second crystal oscillator, and the second crystal oscillator is configured to send a second relative timestamp to the second slave clock source module after the second clock synchronization module corrects the frequency error;

and the second slave clock source module is used for calculating to obtain a synchronous timestamp according to the second message timestamp and the second relative timestamp, and sending the calculated synchronous timestamp to the next second device.

In one embodiment, the third clock synchronization module includes a second interrupt unit and a second information processing unit; the input end of the second interrupt unit is connected with the first output end of the second master clock source module, the output end of the second interrupt unit is connected with the input end of the second information processing unit, and the output end of the second information processing unit is connected with the first input end of the second slave clock source module;

the second interrupt unit is used for interrupting a pulse signal sent by a second master clock source module, and the second information processing unit is used for reading a message carried by the pulse signal sent by the second master clock source, analyzing the message to obtain a second message timestamp, latching the second message timestamp, and sending the second message timestamp to a second slave clock source module.

In one embodiment, the fourth clock synchronization module includes a second listening unit and a second data processing unit; the input end of the second monitoring unit is connected with the second output end of the second master clock source module, the first output end is connected with the control end of the second interrupt unit, the second output end is connected with the input end of the second data processing unit, and the output end of the second data processing unit is connected with the input end of the second crystal oscillator;

the second monitoring unit is configured to determine whether the second master clock source module sends a pulse signal and control the second interrupt unit to perform an interrupt operation, and the second data processing unit is configured to calculate and correct a frequency error of the second crystal oscillator according to the pulse signal sent by the second master clock source module.

Firstly, a first device synchronizes through a global positioning system, and a synchronized clock is used as a main clock source of a second device; when the second device is connected with at least one second device later, the current second device performs clock synchronization on the next second device according to the clock synchronized with the first device, and the clock synchronized with the next second device is used as a master clock source to continue to perform clock synchronization on the connected second devices in sequence, so that the clock synchronization of the devices is realized step by step.

Drawings

FIG. 1 is a diagram illustrating clock synchronization of various devices in one embodiment;

FIG. 2 is a schematic diagram of an embodiment hybrid power transmission line;

FIG. 3 is a block diagram of a first device in one embodiment;

FIG. 4 is a block diagram showing the structure of a first device in another embodiment;

fig. 5 is a block diagram of a second device in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In one embodiment, as shown in fig. 1, there is provided a clock synchronization system comprising: at least one first device 100 and at least one second device 200. Wherein, at least one first device 100 and at least one second device 200 are connected in sequence through a network interface. Preferably, the network interfaces are connected by optical fibers. It should be noted that, in conjunction with fig. 2, the ordering of the first devices 100 and the second devices 200 may be arbitrary, for example, two first devices 100 are above ground in fig. 2, and a plurality of second devices 200 are below ground, alternatively, in other embodiments, only at least one first device 100 or at least one second device 200 may be included, or the first devices 100 and the second devices 200 may be mixed and connected, but the order and the number of the connections are not limited specifically.

Wherein the first device 100 is configured to perform clock synchronization by a global positioning system and a time synchronization protocol and the second device 200 is configured to perform clock synchronization by a time synchronization protocol. The first device 100 performs clock synchronization through the global positioning system, and uses the clock synchronized by the first device 100 through the global positioning system as a master clock source of the second device 200 connected to the first device 100, and when only 1 second device 200 is connected to the first device 100, the synchronization is finished.

Alternatively, as shown in fig. 1, when the second device 200 is connected to at least one second device 200 later, the second device 200 connected to the first device 100 performs clock synchronization on the next connected second device 200 according to that the clock synchronized by the global positioning system of the first device 100 is used as a master clock source, and sequentially performs clock synchronization on the next connected second device 200 by using the clock synchronized by the next second device 200 as a master clock source until all the second devices complete clock synchronization.

Specifically, in conjunction with fig. 1, the first device 100 performs clock synchronization through a global positioning system, such as GNSS, so that a crystal oscillator meets a requirement, and then sends a clock obtained through synchronization to the second device 200 connected to the first device 100, the second device 200 performs clock synchronization using the received clock as a master clock to obtain a clock synchronized by the second device 200, and the second device 200 uses the clock as a master clock of a next second device 200, that is, the second device 200 sends the clock to a next second device, and the next second device continues to repeat the clock synchronization process until the clocks of all the second devices are synchronized, so that after synchronization is completed, the clocks of all the devices are the same as the clocks of the first device 100.

It should be noted that the first device 100 and the second device 200 are both provided with a crystal oscillator, and the crystal oscillator counts the clock to correct the crystal oscillator error, thereby implementing clock synchronization. And in order to ensure accuracy, it is preferable that the crystal oscillators in the first and

second devices

100 and 200 may be the same.

Referring to fig. 1, the first device 100 selects a GNSS as a master clock source, and uses a PPS second pulse signal and a 100MHz constant temperature crystal oscillator to implement clock synchronization, and the synchronized accurate clock is used as a clock source of PTP (time synchronization protocol) -based. The PTP is connected to the next second device 200 through a network interface, and a master-slave relationship is established according to an IEEE1588 protocol, thereby synchronizing a PTP slave clock (i.e., PTPs) of the second device 200. While the synchronized PTPS clock of the second device 200 generates a precise PPS-second pulse signal, synchronizing its PTPM clock. The subsequent devices are synchronized in sequence until the last second device 200. After the synchronization is successful, the clock sources of all the devices are the GNSS clock sources of the first device 100.

In the clock synchronization system, first, the first device 100 synchronizes through the global positioning system, and the synchronized clock is used as a master clock source of the second device 200; when the second device 200 is connected to at least one second device later, the current second device 200 performs clock synchronization on the next second device 200 according to the clock synchronized with the first device 100, and uses the clock synchronized with the next second device 200 as a master clock source to continue to perform clock synchronization on the connected second devices 200 in sequence, thereby realizing the clock synchronization of the devices step by step.

In one embodiment, as shown in FIG. 2, the first device is a device disposed above ground and the second device is a device disposed below ground.

The first device is arranged in occasions with good outdoor wireless communication, and the second device is arranged in occasions such as cable tunnels. The second device adopts a time synchronization protocol clock source, and the first device adopts a global positioning system and time synchronization protocol double clock source. The first device takes a global positioning system as a main clock source to carry out clock synchronization on a time synchronization protocol clock source, and then the first device is synchronized to the underground device, namely the second device through optical fibers. Optionally, the first device and the second device are the same device, and both may support a global positioning system and a time synchronization protocol clock source, and when installed, the clock source of the device may be selectively configured as required.

In the above embodiment, the first device and the second device are respectively deployed according to the above-ground and underground communication conditions, and different devices adopt different clock sources, so that clock synchronization can be better performed.

The global positioning system is a master clock source of the first device, the global positioning system can send out a pulse signal, preferably the pulse signal is a pulse per second signal, and the first device can read a first message timestamp according to message information carried by the pulse signal sent out by the global positioning system; the first crystal oscillator can correct a frequency error according to a pulse signal sent by a global positioning system, the first crystal oscillator outputs a first relative timestamp after the frequency error is corrected, and the first device performs clock synchronization according to the first message timestamp and the first relative timestamp. Preferably, the first crystal oscillator may be a constant temperature crystal oscillator of 100MHz, and in other embodiments, parameters of the crystal oscillator may be set according to needs, which is not specifically limited herein.

In the above embodiment, the clock synchronization of the first device is achieved according to the time stamps output by the global positioning system and the first crystal oscillator.

In one embodiment, as shown in fig. 3, the first device further includes a first clock synchronization module, a second clock synchronization module, and at least one first slave clock source module; the input end of the first clock synchronization module is connected with the first output end of the global positioning system, the output ends of the first clock synchronization module are respectively connected with the first input end of at least one first slave clock source module, the input end of the second clock synchronization module is connected with the second output end of the global positioning system, and the output end of the second clock synchronization module is connected with the input end of the first crystal oscillator; the first clock synchronization module is used for reading and analyzing global positioning system messages and sending analyzed first message timestamps to at least one first slave clock source module; the second clock synchronization module is used for correcting the frequency error of the first crystal oscillator, and the first crystal oscillator is used for respectively sending the first relative timestamp to at least one first slave clock source module after the second clock synchronization module corrects the frequency error.

The first clock synchronization module is used for latching a second-level first message timestamp according to a signal output by the global positioning system, the second clock synchronization module is used for enabling the first crystal oscillator to output a second-level first relative timestamp according to the signal output by the global positioning system, the first slave clock source module is used for synchronizing the complete timestamp of the first slave clock source module, namely the second-level timestamp of the signal latch output by the global positioning system and the nanosecond-level relative timestamp of the signal output by the first crystal oscillator, to second equipment connected with the first equipment, the first slave clock source is in the first equipment, the global positioning system outputs a master clock source, and therefore the synchronized clock source is a slave clock source.

The first clock synchronization module reads message information carried in a pulse signal sent by the global positioning system through a first output end of the global positioning system, analyzes a first message timestamp and latches and sends the first message timestamp to a first input end of at least one first slave clock source module; the second clock synchronization module triggers pulse counting of the first crystal oscillator and corrects frequency errors of the first crystal oscillator after receiving pulse signals sent by the global positioning system twice continuously, the first crystal oscillator corrects the frequency errors through the second clock synchronization module and then sends the first relative timestamp to the second input end of the at least one first slave clock source module, and the first and second input ends of the at least one first slave clock source receive the first message timestamp and the first relative timestamp and then complete clock synchronization with the global positioning system.

Preferably, the first clock synchronization module reads the global positioning system message information through the serial port and analyzes that the first timestamp is a Coordinated Universal Time Coordinated (UTC) second-level timestamp, and the first relative timestamp sent by the first crystal oscillator after the first crystal oscillator corrects the frequency error through the second clock synchronization module is a nanosecond-level timestamp.

In the above embodiment, the first clock synchronization module and the second clock module of the first device respectively obtain the first packet timestamp and the first relative timestamp through the pulse signal sent by the global positioning system, so that the first slave clock source module performs high-precision clock synchronization with the global positioning system through the first packet timestamp and the first relative timestamp.

In one embodiment, with reference to fig. 3, the first clock synchronization module includes a first interrupt unit and a first information processing unit; the input end of the first interrupt unit is connected with the first output end of the global positioning system, the output end of the first interrupt unit is connected with the input end of the first information processing unit, and the output end of the first information processing unit is respectively connected with the first input end of at least one first slave clock source module; the first interrupt unit is used for interrupting a pulse signal sent by a global positioning system, the first information processing unit is used for reading a message carried in the pulse signal, analyzing the message to obtain a first message timestamp, latching the first message timestamp, and respectively sending the first message timestamp to at least one first slave clock source module.

The first information processing unit reads message information carried in the pulse signal sent by the global positioning system through a serial port immediately after the pulse signal sent by the global positioning system is sent by the first interrupt unit, analyzes the message information to obtain a first message timestamp, latches the first message timestamp immediately, and sends the latched first message timestamp to at least one first slave clock source module. Optionally, specifically, as shown in fig. 4, if the first device includes two first slave clock source modules, the first information processing unit sends the latched first packet timestamps to the first input ends of the first slave clock source modules through the first and second output ends respectively after obtaining the packet timestamps.

In the above embodiment, after the first interrupt unit generates an interrupt, the first information processing unit reads and analyzes message information carried in a pulse signal sent by the global positioning system in time, and immediately latches a first message timestamp after obtaining the first message timestamp, and sends the latched first message timestamp to the at least one first slave clock source module, so that the first device realizes clock synchronization with the at least one first slave clock source module.

In one embodiment, the second clock synchronization module comprises a first listening unit and a first data processing unit; the input end of the first monitoring unit is connected with the second output end of the global positioning system, the first output end is connected with the control end of the first interrupt unit, the second output end is connected with the input end of the first data processing unit, and the output end of the first data processing unit is connected with the input end of the first crystal oscillator; the first monitoring unit is used for judging whether the global positioning system sends out a pulse signal and controlling the first interruption unit to carry out interruption operation, and the first data processing unit is used for calculating and correcting the frequency error of the first crystal oscillator according to the pulse signal sent out by the global positioning system.

The first monitoring unit controls the first interruption unit to generate interruption after receiving pulse signals sent by the global positioning system twice continuously, and sends a pulse notice to the first data processing unit, the first data processing unit triggers pulse counting of the first crystal oscillator after receiving the pulse notice sent by the first interruption unit, and corrects a pulse error of the first crystal oscillator after obtaining the frequency of the first crystal oscillator according to the pulse counting.

With reference to fig. 3, the first data processing unit includes a first pulse counting subunit and a first crystal oscillator correction subunit. The first input end of the first pulse counting subunit is connected with the output end of the first monitoring unit, the second input end of the first pulse counting subunit is connected with the second output end of the first crystal oscillator, the output end of the first pulse counting subunit is connected with the input end of the first crystal oscillator correcting subunit, and the output end of the first crystal oscillator correcting subunit is connected with the input end of the first crystal oscillator.

The first pulse counting subunit performs pulse counting on the first crystal oscillator after receiving pulse information sent by the first monitoring unit, calculates a time error of the first crystal oscillator according to pulse counting between two continuous pulse signals, sends the calculated time error of the first crystal oscillator to the first crystal oscillator correcting subunit, and calculates a frequency error of the first crystal oscillator according to the crystal oscillator error and corrects the frequency of the first crystal oscillator. And after correcting the frequency error, the first crystal oscillator respectively sends the first relative time stamps to a second input end of the at least one first slave clock source.

In the above embodiment, the first listening unit and the first data processing unit correct the frequency error of the first crystal oscillator according to the pulse information sent by the global positioning system, and the first crystal oscillator corrects the frequency error and then sends the first relative timestamp to the at least one first slave clock source module, so that the first device realizes clock synchronization with the at least one first slave clock source module.

In particular, in order to make the operation of the first apparatus well understood to those skilled in the art, it will be described in detail with reference to fig. 3 and 4.

The global positioning system of the first device outputs pulse signals and serial port information, and the time error of the first crystal oscillator can be calculated by counting the pulses of the first crystal oscillator triggered by the pulse signals for two times continuously, so that the frequency error of the first crystal oscillator is calculated, and the frequency of the crystal oscillator is corrected; meanwhile, the pulse generates interruption, the message information of the global positioning system is read in time through the serial port, the timestamp of the first message is resolved, and the first message is latched immediately. The first slave clock source module performs time synchronization communication with the slave device through an IEEE1588 protocol, and synchronizes the complete timestamp information of the first slave clock source module to the second device at regular time, wherein the complete timestamp information comprises a first relative counting timestamp output by the first crystal oscillator and a timestamp of a first message output and latched by a global positioning system.

With reference to fig. 4, the first device has 1 global positioning system and 2 first slave clock source modules, the global positioning system is used as a master clock source to synchronize the first slave clock source modules, and the first slave clock source modules can be used as a master clock source to synchronize clocks of the two paths of second devices at the back end.

In one embodiment, the second device includes a master clock source module, a second slave clock source module and a second crystal oscillator, and the second device performs clock synchronization through a signal sent by the master clock source module after synchronization and a signal output by the second crystal oscillator; the master clock source module is used for receiving a synchronization timestamp sent by the first device or the previous second device, and performing clock synchronization on the second slave clock source module according to the synchronization timestamp and a signal output by the second crystal oscillator.

The master clock source module performs clock synchronization with the first device or the previous second device after receiving a synchronization timestamp sent by the first device or the previous second device, and the master clock source module is used as a master clock source of the second device after completing the clock synchronization with the first device, and the second device can read a message timestamp according to message information carried by a pulse signal sent by the master clock module; the second oscillator can correct the frequency error according to the pulse signal sent by the master clock source, the second oscillator after correcting the frequency error outputs a second relative timestamp, and the second slave clock source module performs clock synchronization with the master clock source according to the first message timestamp and the first relative timestamp. Preferably, the second crystal oscillator may be a 100MHz constant temperature crystal oscillator, and in other embodiments, parameters of the crystal oscillator may be set according to needs, which is not specifically limited herein.

It should be noted that, the master clock source module and the second slave clock source module in the second device are relative, and after the second device performs clock synchronization with the first device, the master clock source module is used as the master clock source of the second device, so that the synchronized device is the slave clock source; and if at least one second device is connected behind the current second device, the second slave clock source module of the current second device is used as the master clock source of the next second device to perform clock synchronization.

In the above embodiment, the first packet timestamp and the first relative timestamp are obtained according to the pulse signal output by the master clock source module that completes clock synchronization with the first device or the previous second device, so as to perform high-precision clock synchronization with the second device.

In one embodiment, as shown in fig. 5, the second device further includes a third clock synchronization module and a fourth clock synchronization module; the input end of the third clock synchronization module is connected with the first output end of the master clock source module, the output end of the third clock synchronization module is connected with the first input end of the second slave clock source module, the input end of the fourth clock synchronization module is connected with the second output end of the master clock source module, and the output end of the fourth clock synchronization module is connected with the input end of the second crystal oscillator; the third clock synchronization module is used for reading and latching the second message timestamp, and sending the latched second message timestamp to the second slave clock source module; the fourth clock synchronization module is used for correcting the frequency error of the second crystal oscillator, and the second crystal oscillator is used for sending the second relative timestamp to the second slave clock source module after the second clock synchronization module corrects the frequency error; and the second slave clock source module is used for calculating to obtain a synchronous timestamp according to the second message timestamp and the second relative timestamp, and sending the calculated synchronous timestamp to the next second device.

The third clock synchronization module is used for latching the second message timestamp according to the signal output by the master clock source module, the fourth clock synchronization module is used for enabling the second oscillator to output a second relative timestamp according to the signal output by the master clock source module, the second slave clock source module is used for synchronizing the complete timestamp of the second slave clock module, namely the latched second message timestamp and the second relative timestamp, to the next second device, and the second slave clock source is in the second device, and the master clock source module synchronized with the first device or the previous second device outputs the master clock source, so that the acclimatized and synchronized clock source is the slave clock source.

The third clock synchronization module reads a second message timestamp in message information carried in a pulse signal sent by the master clock source module through a first output end of the master clock source module, latches the second message timestamp and sends the latched second message timestamp to a first input end of a second slave clock source; the fourth clock synchronization module triggers pulse counting of the second crystal oscillator and corrects a frequency error of the second crystal oscillator after receiving pulse signals sent by the master clock source twice continuously, the second crystal oscillator error sends a second relative timestamp to a second input end of the second slave clock source after correcting the frequency error through the fourth clock synchronization module, and the second slave clock source completes clock synchronization with the master clock source module after receiving a second message timestamp and the second relative timestamp.

Preferably, the first clock synchronization module reads the global positioning system message information through the serial port and analyzes that the first timestamp is a UTC second-level timestamp, and the first relative timestamp sent by the first crystal oscillator after the first crystal oscillator corrects the frequency error through the second clock synchronization module is a nanosecond-level timestamp.

In the above embodiment, after the master clock source module sends out the pulse signal, the third clock synchronization module and the fourth clock module obtain the second message timestamp and the second relative timestamp, so that the second slave clock source module completes clock synchronization with the master clock source module through the second message timestamp and the second relative timestamp.

In one embodiment, as shown in fig. 5, the third clock synchronization module includes a second interrupt unit and a second information processing unit; the input end of the second interrupt unit is connected with the first output end of the second master clock source module, the output end of the second interrupt unit is connected with the input end of the second information processing unit, and the output end of the second information processing unit is connected with the first input end of the second slave clock source module; the second information processing unit is used for reading a message carried by the pulse signal sent by the second master clock source, analyzing the message to obtain a second message timestamp, latching the second message timestamp, and sending the second message timestamp to the second slave clock source module.

The second information processing unit reads message information carried in the pulse signal sent by the master clock source module through the serial port immediately after the pulse signal sent by the second interrupt unit to the master clock source module, analyzes the message to obtain a second message timestamp, latches the second message timestamp immediately, and sends the latched second message timestamp to the first input end of the second slave clock source module.

In the above embodiment, after the second interrupt unit generates an interrupt, the second information processing unit reads and analyzes the message information carried in the master clock source module in time, and sends the analyzed second message timestamp to the second slave clock source module, so that the second slave clock source module realizes clock synchronization with the master clock source module.

In one embodiment, the fourth clock synchronization module comprises a second listening unit and a second data processing unit; the input end of the second monitoring unit is connected with the second output end of the second main-end clock source module, the first output end is connected with the control end of the second interrupt unit, the second output end is connected with the input end of the second data processing unit, and the output end of the second data processing unit is connected with the input end of the second crystal oscillator; the second monitoring unit is used for judging whether the second master clock source module sends out a pulse signal and controlling the second interrupt unit to implement interrupt operation, and the second data processing unit is used for calculating and correcting the frequency error of the second crystal oscillator according to the pulse signal sent out by the second master clock source module.

With reference to fig. 4, after receiving the pulse signals sent by the master clock source module twice, the second interception unit controls the second interruption unit to generate interruption and sends the pulse notification to the second data processing unit, and the second data processing unit triggers pulse counting of the second crystal oscillator after receiving the pulse notification sent by the second interruption unit, and corrects the pulse error of the second crystal oscillator after obtaining the frequency of the second crystal oscillator according to the pulse counting.

The first data processing unit comprises a second pulse counting subunit and a second crystal oscillation correcting subunit. The first input end of the second pulse counting subunit is connected with the output end of the second monitoring unit, the second input end of the second pulse counting subunit is connected with the second output end of the second crystal oscillator, the output end of the second pulse counting subunit is connected with the input end of the second crystal oscillator correcting subunit, and the output end of the second crystal oscillator correcting subunit is connected with the input end of the second crystal oscillator.

The second pulse counting subunit performs pulse counting on the second crystal oscillator after receiving pulse information sent by the second monitoring unit, calculates a time error of the second crystal oscillator according to pulse counting between two consecutive pulse signals, sends the calculated time error of the second crystal oscillator to the second crystal oscillator correcting subunit, and calculates a frequency error of the second crystal oscillator according to the time error of the second crystal oscillator and corrects the frequency of the second crystal oscillator. And the second crystal oscillator sends the second relative timestamp to a second input end of the second slave clock source module after correcting the frequency error.

In the above embodiment, the second listening unit and the second data processing unit correct the frequency error of the second crystal oscillator according to the pulse information sent by the global positioning system, and the second crystal oscillator corrects the frequency error and then sends the second relative timestamp to the second slave clock source module, so that the second slave clock source module realizes clock synchronization with the master clock source module.

In particular, in order to make the operation of the second apparatus well understood to those skilled in the art, it will be described in detail with reference to fig. 5.

The second device has two PTP clock sources, which are divided into a slave PTPs, i.e., a master clock source module of the second device, and a master PTPM, i.e., a second slave clock source module of the second device, and correspond to the front and rear PTP fiber links, respectively, and both support IEEE1588 protocol. And the PTPS receives the synchronization time stamp of the first device or the previous second device, and the PTPM sends the own synchronization time stamp to the next second device. After the PTPS performs clock synchronization with the first device or with the last second device, the PTPS serves as a master clock source of the second device to perform clock synchronization with the PTPM. In order to maintain a uniform clock, a pulse signal generated by the PTPS is used as a synchronous clock source of the second crystal oscillator, the pulse counting of the second crystal oscillator is triggered by the pulse signal twice continuously, the frequency error of the second crystal oscillator is obtained and corrected, the second crystal oscillator after correcting the frequency error sends a second relative timestamp to the PTPM, meanwhile, the pulse signal of the PTPS generates interruption, and a third clock synchronization module reads and latches the second-level first message timestamp. And then the first message timestamp and the second relative timestamp form a complete timestamp of the PTPM, and the complete timestamp is synchronously output to the next second device.

In one embodiment, the clock synchronization system may include the steps of:

as shown in fig. 1, if only one first device and two second devices are included, they are connected in sequence through a network interface. For convenience of description, the two second apparatuses are referred to as a second apparatus 1 and a second apparatus 2, respectively.

Firstly, a global positioning system in first equipment sends out a pulse signal, and a first interception unit controls a first interruption unit to interrupt the pulse signal after receiving the pulse signal sent out by the global positioning system twice continuously, and sends a pulse notice to a first pulse counting unit. After the first interrupt unit generates interrupt, the first information processing unit immediately reads message information carried in a pulse signal sent by a global positioning system through a serial port, analyzes the message information to obtain a first message timestamp, immediately latches the first message timestamp, and sends the latched first message timestamp to a first input end of a first slave clock source module; the first pulse counting unit is used for counting pulses of the first crystal oscillator after receiving pulse information sent by the first monitoring unit, calculating time errors of the first crystal oscillator according to the pulse counting between two continuous pulse signals, sending the calculated time errors of the first crystal oscillator to the first crystal oscillator correcting subunit, calculating frequency errors of the first crystal oscillator according to the crystal oscillator errors by the first correcting subunit, and correcting the frequency of the first crystal oscillator. And the first crystal oscillator sends the first relative timestamp to a second input end of the first slave clock source module after correcting the frequency error. And the first slave clock source module performs clock synchronization with the global positioning system after receiving the first message timestamp and the first relative timestamp, and sends the calculated synchronization timestamp to the second device 1. The master clock source module 1 of the second device 1 performs clock synchronization with the first device after receiving the synchronization timestamp sent by the first device, and serves as a master clock source of the second device 1 after completing the clock synchronization with the first device. After receiving the pulse signal sent by the master clock source module 1 twice, the second listening unit 1 in the second device 1 controls the second interrupting unit 1 to generate an interrupt, and sends a pulse notification to the second data processing unit 1. After the second interrupt unit 1 generates an interrupt, the second information processing unit 1 immediately reads message information carried in a pulse signal sent by the master clock source module through a serial port, and immediately latches a second message timestamp 1 after analyzing the message to obtain the second message timestamp 1, and sends the latched second message timestamp 1 to a first input end of the second slave clock source module 1; the second pulse counting subunit 1 performs pulse counting on the second crystal oscillator 1 after receiving pulse information sent by the second monitoring unit 1, calculates a time error of the second crystal oscillator 1 according to the pulse counting between two consecutive pulse signals, the second pulse counting subunit 1 sends the calculated time error of the second crystal oscillator to the second crystal oscillator correcting subunit 1, the second correcting subunit 1 calculates a frequency error of the second crystal oscillator 1 according to the time error of the second crystal oscillator 1 and corrects the frequency of the second crystal oscillator 1, the second crystal oscillator 1 sends a second relative timestamp 1 to a second input end of the second slave clock source module 1 after correcting the frequency error, the second slave clock source module 1 performs clock synchronization with the master clock source module 1 after receiving the second message timestamp 1 and the second relative timestamp 1, the second slave clock source module 1 performs clock synchronization with the master clock source module 1 after completing clock synchronization, the synchronization time stamp is calculated and sent to the second device 2. The master clock source module of the second device 2 completes clock synchronization with the second device 1 after receiving the synchronization timestamp sent by the second device 1, and serves as a master clock source of the second device 2. A second monitoring unit 2 in the second device 2 receives pulse signals sent by the master clock source module 1 twice continuously and sends a pulse notification to a second data processing unit 2, the second pulse counting subunit 2 performs pulse counting on the second crystal oscillator 2 after receiving pulse information sent by the second monitoring unit 2 and calculates a time error of the second crystal oscillator 2 according to the pulse counting between the two continuous pulse signals, the second pulse counting subunit 2 sends the calculated time error of the second crystal oscillator to a second crystal oscillator correction subunit 2, and the second correction subunit 2 calculates a frequency error of the second crystal oscillator 2 according to the time error of the second crystal oscillator 2 and corrects the frequency of the second crystal oscillator 2. At this time, the first device, the second device 1, and the second device 2 complete clock synchronization.

The first message timestamp and the second message timestamp 1 are UTC second-level timestamps, and the first relative timestamp and the second relative timestamp 2 are nanosecond relative timestamps.

The clock synchronization among the devices establishes a master-slave relationship through an IEEE1588 protocol, 1588 protocol messages are received and sent between the master device and the slave device at regular time, the synchronization of hardware clocks is kept at any time, and nanosecond precise timestamps are automatically added when the messages come in and go out of a physical layer. The slave end compares the time stamp in the master end message with the clock of the slave end, and performs clock correction according to the difference, thereby realizing accurate synchronous time service of master and slave time.

In the above embodiment, first, the first device synchronizes through the global positioning system, the synchronized clock serves as a master clock source of the second device 1, and the second device 1 performs clock synchronization on the second device 2 according to the master clock source, so that all devices in the same network system have an accurate unique clock source.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A clock synchronization system, the clock synchronization system comprising:

2. The clock synchronization system of claim 1, wherein the first device is a device disposed above ground and the second device is a device disposed below ground.

3. The clock synchronization system of claim 1, wherein the first device comprises a global positioning system and a first crystal oscillator, and the first device performs clock synchronization by a signal sent by the global positioning system and a signal output by the first crystal oscillator.

4. The clock synchronization system of claim 3, wherein the first device further comprises a first clock synchronization module, a second clock synchronization module, and at least one first slave clock source module; the input end of the first clock synchronization module is connected with the first output end of the global positioning system, the output ends of the first clock synchronization module are respectively connected with the first input end of at least one first slave clock source module, the input end of the second clock synchronization module is connected with the second output end of the global positioning system, and the output end of the second clock synchronization module is connected with the input end of the first crystal oscillator;

5. The clock synchronization system according to claim 4, wherein the first clock synchronization module includes a first interrupt unit and a first information processing unit; the input end of the first interrupt unit is connected with the first output end of the global positioning system, the output end of the first interrupt unit is connected with the input end of the first information processing unit, and the output end of the first information processing unit is respectively connected with the first input end of at least one first slave clock source module;

6. The clock synchronization system of claim 5, wherein the second clock synchronization module comprises a first listening unit and a first data processing unit; the input end of the first monitoring unit is connected with the second output end of the global positioning system, the first output end of the first monitoring unit is connected with the control end of the first interrupt unit, the second output end of the first monitoring unit is connected with the input end of the first data processing unit, and the output end of the first data processing unit is connected with the input end of the first crystal oscillator;

7. The clock synchronization system according to claim 1, wherein the second device includes a master clock source module, a second slave clock source module and a second crystal oscillator, and the second device performs clock synchronization through a signal sent by the master clock source module after synchronization and a signal output by the second crystal oscillator;

8. The clock synchronization system of claim 7, wherein the second device further comprises a third clock synchronization module and a fourth clock synchronization module; the input end of the third clock synchronization module is connected with the first output end of the master clock source module, the output end of the third clock synchronization module is connected with the first input end of the second slave clock source module, the input end of the fourth clock synchronization module is connected with the second output end of the master clock source module, and the output end of the fourth clock synchronization module is connected with the input end of the second crystal oscillator;

9. The clock synchronization system of claim 8, wherein the third clock synchronization module comprises a second interrupt unit and a second information processing unit; the input end of the second interrupt unit is connected with the first output end of the second master clock source module, the output end of the second interrupt unit is connected with the input end of the second information processing unit, and the output end of the second information processing unit is connected with the first input end of the second slave clock source module;

10. The clock synchronization system of claim 8, wherein the fourth clock synchronization module comprises a second listening unit and a second data processing unit; the input end of the second monitoring unit is connected with the second output end of the second master clock source module, the first output end is connected with the control end of the second interrupt unit, the second output end is connected with the input end of the second data processing unit, and the output end of the second data processing unit is connected with the input end of the second crystal oscillator;