CN112803949A

CN112803949A - DAC multichannel control circuit and driving device

Info

Publication number: CN112803949A
Application number: CN202110119132.6A
Authority: CN
Inventors: 陈克勇; 郭伟峰; 李照华
Original assignee: Shenzhen Sunmoon Microelectronics Co Ltd
Current assignee: Shenzhen Sunmoon Microelectronics Co Ltd
Priority date: 2021-01-28
Filing date: 2021-01-28
Publication date: 2021-05-14

Abstract

A DAC multichannel control circuit and a driving device are provided, wherein the DAC multichannel control circuit can convert a group of input multichannel synchronous serial data into multichannel parallel data by adopting a first clock circuit and a data conversion circuit, and can realize the digital-to-analog conversion of the multichannel parallel data by only using one digital-to-analog conversion circuit by adopting a control signal generating circuit, a digital-to-analog conversion circuit and a switch circuit, and output the multichannel parallel data through different switch channels of the switch circuit, namely, the time-sharing multiplexing of the digital-to-analog conversion circuit is realized. DAC multichannel control circuit in this application need adopt a plurality of DACs just can realize the DAC multichannel circuit of multichannel output in more tradition, only uses a DAC, has reduced circuit area and consumption, guarantees the current uniformity between constant current precision and different passageways moreover, has solved and has had circuit area big among the traditional DAC multichannel circuit, and the consumption is big and the passageway uniformity is poor problem.

Description

DAC multichannel control circuit and driving device

Technical Field

The present application relates to Digital-to-analog converter (DAC) multi-channel control circuits and driving devices, and particularly to a DAC multi-channel control circuit and a driving device.

Background

With the rapid development of semiconductor technology, the device size is gradually reduced, and the circuit integration level is higher and higher. Therefore, some precision instruments and equipment put higher requirements on the current regulation precision. However, in the conventional circuit, to realize high-precision current control, a DAC module is often adopted, and for a multi-channel circuit, a plurality of DAC circuits are required, which greatly increases the circuit area and power consumption and increases the design cost. In addition, due to the influence of the manufacturing process, the channel consistency is poor due to the difference of the DACs, and the constant current precision and the current consistency among different channels are reduced.

Therefore, the traditional DAC multichannel circuit has the problems of large circuit area, large power consumption and poor channel consistency.

Disclosure of Invention

The application aims to provide a DAC multichannel control circuit and a driving device, and aims to solve the problems of large circuit area, large power consumption and poor channel consistency of a traditional DAC multichannel circuit.

A first aspect of an embodiment of the present application provides a DAC multi-channel control circuit, including:

a first clock circuit for generating a first clock signal;

a control signal generation circuit for generating a plurality of switching signals;

the data conversion circuit is connected with the first clock circuit and used for accessing a group of multi-channel synchronous serial data, sequentially sampling the multi-channel serial data in the group of multi-channel synchronous serial data according to the first clock signal and respectively converting the sampled multi-channel serial data into multi-channel parallel data;

the digital-to-analog conversion circuit is connected with the data conversion circuit and the control signal generation circuit and is used for sequentially converting each path of parallel data in the multiple paths of parallel data into corresponding analog signals under the control of the switching signals; and

and the switch circuit is connected with the digital-to-analog conversion circuit and is used for sequentially conducting a switch channel under the control of the plurality of switch signals so as to output corresponding analog signals in a time-sharing manner.

In one embodiment, the switch circuit includes a plurality of switch channels, one switch channel corresponds to one analog signal and one switch signal, an input end of each switch channel is commonly connected to the digital-to-analog conversion circuit, a control end of each switch channel is respectively connected to the control signal generation circuit, and the switch channels are not simultaneously conducted.

In one embodiment, the switch channel includes a first switch tube, a first conducting end of the first switch tube is an input end of the switch channel, and a control end of the first switch tube is a control end of the switch channel.

In one embodiment, the DAC multi-channel control circuit further comprises a plurality of storage circuits, one of the storage circuits is connected to an input terminal of one of the switch channels, and the storage circuit is used for storing the analog signals output by the switch channels.

In one embodiment, the waveforms of the switching signals are the same, and the phases are different; and the positive pulse time of each switching signal is not overlapped.

In one embodiment, the control signal generating circuit includes:

a second clock circuit for generating a second clock signal;

the plurality of cascaded shift registers are connected with the second clock circuit and used for sequentially shifting and outputting the second clock signal according to a cascade sequence; and

the input end of one delay circuit is connected with the output end of one shift register of the plurality of shift registers, the output end of one delay circuit is connected with the digital-to-analog conversion circuit, and the delay circuit is used for inserting delay dead time into the shifted second clock signal accessed by the delay circuit and outputting the second clock signal as the switch signal.

In one embodiment, the DAC multi-channel control circuit further includes a plurality of voltage-controlled constant current source circuits, one of the voltage-controlled constant current source circuits is connected to an output terminal of one of the switch channels, and the voltage-controlled constant current source circuits are configured to control a current of the analog signal to be a target constant current.

In one embodiment, the voltage controlled constant current source circuit comprises: the high-voltage switch comprises a first operational amplifier, a second switch tube and a first resistor, wherein the positive input end of the first operational amplifier is connected with the output end of a switch channel, the negative input end of the first operational amplifier is connected with the first end of the first resistor and the second conduction end of the second switch tube, the second end of the first resistor is grounded, the control end of the second switch tube is connected with the output end of the first operational amplifier, and the first conduction end of the second switch tube serves as the output end of the multi-channel control circuit.

In one embodiment, the DAC multi-channel control circuit further comprises a band-gap reference voltage source connected to the digital-to-analog conversion circuit, and the band-gap reference voltage source is used for providing a reference voltage for the digital-to-analog conversion circuit.

A second aspect of an embodiment of the present application provides a driving apparatus, including: in the DAC multi-channel control circuit according to the first aspect of the embodiment of the present application, a plurality of output terminals of the DAC multi-channel control circuit are respectively connected to a plurality of loads, one of the output terminals is used for outputting a driving signal to one of the loads, and the driving signal is the analog signal.

According to the DAC multichannel control circuit, the first clock circuit and the data conversion circuit are adopted, so that an input group of multichannel synchronous serial data can be converted into multichannel parallel data, the control signal generation circuit, the digital-to-analog conversion circuit and the switch circuit are adopted, digital-to-analog conversion of the multichannel parallel data can be achieved by only using one digital-to-analog conversion circuit, and the multichannel digital-to-analog conversion circuit is output through different switch channels of the switch circuit, so that time-sharing multiplexing of one digital-to-analog conversion circuit is achieved. DAC multichannel control circuit in this application need adopt a plurality of DACs just can realize the DAC multichannel circuit of multichannel output in more tradition, only uses a DAC, has reduced circuit area and consumption, guarantees the current uniformity between constant current precision and different passageways moreover, has solved and has had circuit area big among the traditional DAC multichannel circuit, and the consumption is big and the passageway uniformity is poor problem.

Drawings

FIG. 1 is a circuit diagram of a multi-channel DAC control circuit according to an embodiment of the present disclosure;

FIG. 2 is an exemplary circuit schematic of the DAC multi-channel control circuit shown in FIG. 1;

FIG. 3 is another exemplary circuit schematic of the DAC multi-channel control circuit shown in FIG. 2;

FIG. 4 is another exemplary circuit schematic of the DAC multi-channel control circuit shown in FIG. 3;

fig. 5 is a signal timing diagram of the DAC multi-channel control circuit shown in fig. 4.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Fig. 1 shows a schematic structural diagram of a DAC multi-channel control circuit provided in a first aspect of an embodiment of the present application, and for convenience of description, only parts related to the embodiment are shown, and detailed as follows:

the DAC multi-channel control circuit in this embodiment includes: the clock circuit comprises a first clock circuit 100, a control signal generating circuit 200, a data conversion circuit 300, a digital-to-analog conversion circuit 400 and a switch circuit 500. The output end of the first clock circuit 100 is connected to the data conversion circuit 300, the input end of the data conversion circuit 300 is connected to a group of multi-channel synchronous serial data, the output end of the control signal generation circuit 200 is connected to the enable end of the digital-to-analog conversion circuit 400, the output ends of the data conversion circuit 300 are connected to the input ends of the digital-to-analog conversion circuit 400, the output end of the digital-to-analog conversion circuit 400 is connected to the input end of the switch circuit 500, and the output ends of the switch circuit 500 are used for respectively outputting analog signals (VDAC1, VDAC 2.. VDACn).

The first clock circuit 100 is used for generating a first clock signal. The control signal generating circuit 200 is used for a plurality of switch signals (SW1, SW 2.. SWn). The data conversion circuit 300 is configured to access a group of multi-channel synchronous serial data, sequentially sample the multi-channel serial data in the group of multi-channel synchronous serial data according to a first clock signal, and respectively convert the sampled multi-channel serial data into multi-channel parallel data. The digital-to-analog conversion circuit 400 is configured to sequentially convert each of the multiple paths of parallel data into a corresponding analog signal under the control of multiple switching signals. The switch circuit 500 is used for sequentially turning on a switch channel 510 under the control of a plurality of switch signals to output corresponding analog signals in a time-sharing manner.

It is understood that the first clock circuit 100 may be formed of a low frequency oscillation circuit or a chip. The control signal generating circuit 200 may be constituted by an oscillation circuit. The data conversion circuit 300 may be constituted by a data processing chip, or a sampling chip and a serial-parallel converter. The digital-to-analog conversion chip may be constituted by a digital-to-analog conversion chip. The switching circuit 500 may be formed by a plurality of controllable switches connected in parallel.

It is to be understood that the first clock signal may be a low frequency clock signal. The plurality of switching signals may be a plurality of parallel switching signals whose positive pulse time is not overlapped, and one switching signal controls the on/off of one switching channel 510 in the switching circuit 500. The positive pulse time of the switching signals in one period reaches the sequence of the conduction sequence of each switching channel 510 in the switching circuit 500. The plurality of switching signals constitute a set of time-sharing timing signals.

It is understood that the sampling times of the multiple serial data do not overlap. Optionally, the frequency of the first clock signal may be adjusted according to the length and the number of the data, so as to adjust the sampling frequency and the duration of the data, and avoid the occurrence of sampling time overlap and insufficient data processing time, thereby causing confusion or mutual interference between the data.

In the DAC multi-channel control circuit in this embodiment, the first clock circuit 100 and the data conversion circuit 300 are used to convert a set of input multi-channel synchronous serial data into multi-channel parallel data, and the control signal generation circuit 200, the digital-to-analog conversion circuit 400 and the switch circuit 500 are used to realize digital-to-analog conversion of the multi-channel parallel data by using only one digital-to-analog conversion circuit 400 and output the multi-channel parallel data through different switch channels 510 of the switch circuit 500, so that time-sharing multiplexing of one digital-to-analog conversion circuit 400 is realized. DAC multichannel control circuit in this application need adopt a plurality of DACs just can realize the DAC multichannel circuit of multichannel output in more tradition, only uses a DAC, has reduced circuit area and consumption, guarantees the current uniformity between constant current precision and different passageways moreover, has solved and has had circuit area big among the traditional DAC multichannel circuit, and the consumption is big and the passageway uniformity is poor problem.

Referring to fig. 2, in an embodiment, the switch circuit 500 includes a plurality of switch channels 510, one switch channel 510 corresponds to one analog signal and one switch signal, input terminals of the switch channels 510 are commonly connected to the digital-to-analog conversion circuit 400, control terminals of the switch channels 510 are respectively connected to the control signal generation circuit 200, and the switch channels 510 are not simultaneously conducted.

It is understood that the switch path 510 may be formed by a controllable switch, such as a transistor, or a normally-open relay. The switch channels 510 of the switch circuit 500 in this embodiment are not turned on simultaneously, so that overlapping or confusion of different data is avoided, and malfunction or failure of an external circuit driven by the DAC multi-channel control circuit is avoided.

Referring to fig. 2, in an embodiment, taking the switch channel 510 corresponding to the first channel of the DAC multi-channel control circuit as an example, the switch channel 510 includes a first switch Q1, a first conducting terminal of the first switch Q1 is an input terminal of the switch channel 510, and a control terminal of the first switch Q1 is a control terminal of the switch channel 510.

It is understood that the first switch Q1 in this embodiment is an NMOS transistor, the gate of the NMOS transistor is the control terminal of the first switch Q1, the drain of the NMOS transistor is the first conducting terminal of the first switch Q1, and the source of the NMOS transistor is the second conducting terminal of the first switch Q1. In other embodiments, other switch tubes may be used.

Referring to fig. 3, in an embodiment, the DAC multi-channel control circuit further includes a plurality of storage circuits 600, one storage circuit 600 is connected to an input terminal of one switch channel 510, and the storage circuit 600 is used for storing the analog signals output by the switch channels 510.

It is understood that the storage circuit 600 may be formed of a storage capacitor. The DAC multi-channel control circuit controls the digital-to-analog conversion circuit 400 by inputting a plurality of switching signals, and when different data are inputted, the corresponding channel switches in the switching circuit 500 are opened, the analog signals converted by the digital-to-analog conversion circuit 400 are stored by using the storage circuit 600 connected to the switching channel 510, and the channel switches are closed before the other channel data come, so as to prevent the analog data converted by the other channel data from being interfered.

Optionally, referring to fig. 5, in an embodiment, waveforms of the switching signals are the same, and phases are different; and the positive pulse time of each switching signal is not overlapped. Fig. 5 is a timing diagram of data and signals when the number of channels is 3, in which the switch circuit 500 includes 3 switch channels 510, and the switch signals SW1, SW2 and SW3 respectively control the 3 switch channels 510. Data is a set of 3-way synchronous serial Data bus signals, which includes Data1, Data2, and Data 3.

It is to be understood that the plurality of switching signals may be signals obtained by delaying one timing signal by different delays. Or a plurality of switch signals are cascaded, and each switch signal is a signal obtained by shifting and delaying the previous switch signal in sequence.

It will be appreciated that the duration of the positive pulse of the switching signal is greater than the output duration of the analog signal to ensure that the analog signal is output through the corresponding switching channel 510.

It can be understood that the waveforms of the respective switching signals in this embodiment are the same, and the phases are different; and the positive pulse time of each switching signal is not overlapped, so that the conduction time of each switching channel 510 of the switching circuit 500 is not overlapped, and the mutual interference among the switching channels 510 is avoided.

Referring to fig. 4, in one embodiment, the control signal generating circuit 200 includes: the clock circuit 410, a plurality of cascaded shift registers 420 and a plurality of delay circuits 430, the plurality of shift registers 420 are connected with the clock circuit 410, an input end of a delay circuit 430 is connected with an output end of one shift register 420 of the plurality of shift registers 420, and an output end of a delay circuit 430 is connected with the digital-to-analog conversion circuit 400. The second clock circuit 410 is used for generating a second clock signal; the plurality of shift registers 420 are used for sequentially shifting and outputting the second clock signals according to a cascade sequence; the delay circuit 430 is used for inserting delay dead time in the shifted second clock signal connected thereto, and outputting as a switching signal.

It will be appreciated that a plurality of shift registers 420 are coupled to the second clock circuit 410, such that a first shift register 420 is coupled to the second clock circuit 410, a second shift register 420 is coupled to the first shift register 420, a third shift register 420 is coupled to the second shift register 420, and so on. The dead time inserted by each delay circuit 430 may or may not be the same duration.

It is understood that the second clock circuit 410 may be formed by a high frequency oscillator and the second clock signal may be a high frequency clock signal. The delay circuit 430 may be formed of a delay or a delay module.

Referring to fig. 4, in an embodiment, the DAC multi-channel control circuit further includes a plurality of voltage-controlled constant current source circuits 700, one voltage-controlled constant current source circuit 700 is connected to an output terminal of one switch channel 510, and the voltage-controlled constant current source circuit 700 is configured to control a current of the analog signal to be a target constant current.

It is understood that the DAC multi-channel control circuit in the present embodiment, by adding a plurality of voltage-controlled constant current source circuits 700, makes the output of the analog signal become the current signal output of the target constant current to drive or control the load connected to the DAC multi-channel control circuit by current. OUT1, OUT2, OUTn, etc. in the figure are the output terminals of the respective channels of the DAC multi-channel control circuit.

Optionally, when the constant voltage output is required, a current-voltage conversion circuit may be further added to convert the current signal into a voltage signal for output, or an analog signal of the voltage signal is directly output to the operational amplifier for output.

Referring to fig. 4, in an embodiment, taking a voltage-controlled constant current source circuit 700 corresponding to a first channel of the DAC multi-channel control circuit as an example, the voltage-controlled constant current source circuit 700 includes: the multi-channel control circuit comprises a first operational amplifier U1, a second switch tube M1 and a first resistor R1, wherein the positive input end of the first operational amplifier U1 is connected with the output end of the switch channel 510, the negative input end of the first operational amplifier U1 is connected with the first end of a first resistor R1 and the second conducting end of a second switch tube M1, the second end of the first resistor R1 is grounded, the control end of the second switch tube M1 is connected with the output end of the first operational amplifier U1, and the first conducting end of the second switch tube M1 serves as the output end OUT1 of the multi-channel control circuit.

It is understood that the second switch transistor M1 in this embodiment is an NMOS transistor, the gate of the NMOS transistor is the control terminal of the second switch transistor M1, the drain of the NMOS transistor is the first conducting terminal of the second switch transistor M1, and the source of the NMOS transistor is the second conducting terminal of the second switch transistor M1. In other embodiments, other switch tubes may be used.

Referring to fig. 4, in an embodiment, the DAC multi-channel control circuit further includes a bandgap reference voltage source 800, the bandgap reference voltage source 800 is connected to the digital-to-analog conversion circuit 400, and the bandgap reference voltage source 800 is configured to provide a reference voltage VREF for the digital-to-analog conversion circuit 400.

It is understood that the reference voltage VREF is used to adjust the ratio of digital-to-analog conversion of the digital-to-analog conversion circuit 400. The bandgap reference voltage source 800 may be composed of a plurality of transistors and resistors, or composed of the bandgap reference voltage source 800 chip and its peripheral elements.

A second aspect of embodiments of the present application provides a driving apparatus, including: in the DAC multi-channel control circuit according to the first aspect of the embodiments of the present application, a plurality of output terminals of the DAC multi-channel control circuit are respectively connected to a plurality of loads, one output terminal is used for outputting a driving signal to one load, and the driving signal is an analog signal.

It can be understood that the driving apparatus in the present embodiment, by using the DAC multi-channel control circuit according to the first aspect of the embodiments of the present application, realizes multi-channel output of a plurality of driving signals by using one DAC to drive or control a plurality of loads simultaneously.

It is understood that the multiple synchronous serial data correspond to multiple loads, that is, one serial data is data for driving or controlling one load in a group of multiple synchronous serial data.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A DAC multi-channel control circuit, comprising:

a first clock circuit for generating a first clock signal;

2. The DAC multi-channel control circuit of claim 1 wherein said switch circuit includes a plurality of switch channels, one of said switch channels corresponding to one of said analog signals and one of said switch signals, input terminals of each of said switch channels being commonly connected to said digital to analog conversion circuit, control terminals of each of said switch channels being respectively connected to said control signal generation circuit, said switch channels being non-simultaneously conductive with respect to each other.

3. The DAC multi-channel control circuit of claim 2 wherein the switch channel includes a first switch tube, the first conducting terminal of the first switch tube being an input terminal of the switch channel, the control terminal of the first switch tube being a control terminal of the switch channel.

4. The DAC multi-channel control circuit of claim 2 further comprising a plurality of storage circuits, one said storage circuit connected to an input of one said switch channel, said storage circuit for storing said analog signal output by said switch channel.

5. The DAC multi-channel control circuit of claim 2 wherein the waveforms of the respective switching signals are the same and are different in phase; and the positive pulse time of each switching signal is not overlapped.

6. The DAC multi-channel control circuit of claim 5 wherein the control signal generation circuit comprises:

a second clock circuit for generating a second clock signal;

7. The DAC multichannel control circuit as claimed in any one of claims 1 to 6, further comprising a plurality of voltage-controlled constant current source circuits, one of the voltage-controlled constant current source circuits being connected to an output terminal of one of the switch channels, the voltage-controlled constant current source circuits being configured to control a current of the analog signal to a target constant current.

8. The DAC multi-channel control circuit of claim 7 wherein the voltage controlled constant current source circuit comprises: the high-voltage switch comprises a first operational amplifier, a second switch tube and a first resistor, wherein the positive input end of the first operational amplifier is connected with the output end of a switch channel, the negative input end of the first operational amplifier is connected with the first end of the first resistor and the second conduction end of the second switch tube, the second end of the first resistor is grounded, the control end of the second switch tube is connected with the output end of the first operational amplifier, and the first conduction end of the second switch tube serves as the output end of the multi-channel control circuit.

9. The DAC multi-channel control circuit of claim 7 further comprising a bandgap reference voltage source coupled to the digital to analog conversion circuit, the bandgap reference voltage source for providing a reference voltage to the digital to analog conversion circuit.

10. A drive device, comprising: the DAC multi-channel control circuit of any one of claims 1-9, wherein a plurality of output terminals of the DAC multi-channel control circuit are respectively connected to a plurality of loads, one of the output terminals is used for outputting a driving signal to one of the loads, and the driving signal is the analog signal.