CN112786746A - Epitaxial wafer of light emitting diode and preparation method thereof - Google Patents

Epitaxial wafer of light emitting diode and preparation method thereof Download PDF

Info

Publication number
CN112786746A
CN112786746A CN202011623709.9A CN202011623709A CN112786746A CN 112786746 A CN112786746 A CN 112786746A CN 202011623709 A CN202011623709 A CN 202011623709A CN 112786746 A CN112786746 A CN 112786746A
Authority
CN
China
Prior art keywords
layer
temperature
epitaxial wafer
aln buffer
aln
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202011623709.9A
Other languages
Chinese (zh)
Other versions
CN112786746B (en
Inventor
丁涛
龚程成
尹涌
梅劲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boe Huacan Optoelectronics Zhejiang Co ltd
Original Assignee
HC Semitek Zhejiang Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HC Semitek Zhejiang Co Ltd filed Critical HC Semitek Zhejiang Co Ltd
Priority to CN202011623709.9A priority Critical patent/CN112786746B/en
Publication of CN112786746A publication Critical patent/CN112786746A/en
Application granted granted Critical
Publication of CN112786746B publication Critical patent/CN112786746B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The disclosure provides an epitaxial wafer of a light emitting diode and a preparation method thereof, belonging to the technical field of photoelectron manufacturing. The epitaxial wafer comprises a substrate, and a first high-temperature AlN buffer layer, a superlattice layer, a second high-temperature AlN buffer layer, an AlGaN transition layer, an n-type AlGaN layer, a multi-quantum well layer and a p-type layer which are sequentially formed on the substrate, wherein the superlattice layer comprises a plurality of AlN layers and a plurality of SiN layers which are alternately stacked. The SiN layer can play the effect of blockking threading dislocation, and alternately range upon range of AlN layer and SiN layer can make by the dislocation bending that the first high temperature AlN buffer layer extends, increase the probability that the dislocation was annihilated each other, make in the direction that each layer is range upon range of, the crystal quality of AlN is better and better, be favorable to promoting the holistic crystal quality of epitaxial wafer, the tensile stress in the AlN material can also be alleviated to the superlattice layer, make ultraviolet LED's luminous efficacy obtain promoting.

Description

Epitaxial wafer of light emitting diode and preparation method thereof
Technical Field
The disclosure relates to the technical field of photoelectron manufacturing, and in particular relates to an epitaxial wafer of a light emitting diode and a preparation method thereof.
Background
The Light Emitting Diode (LED) is a new product with great influence in the photoelectronic industry, has the characteristics of small volume, long service life, rich and colorful colors, low energy consumption and the like, and is widely applied to the fields of illumination, display screens, signal lamps, backlight sources, toys and the like. The core structure of the LED is an epitaxial wafer, and the manufacturing of the epitaxial wafer has great influence on the photoelectric characteristics of the LED.
The epitaxial wafer typically includes a buffer layer, an n-type layer, a multiple quantum well layer, and a p-type layer. In an epitaxial wafer of an ultraviolet light emitting diode, a buffer layer is usually an AlN layer, more dislocation defects are easily accumulated in the AlN layer, the quality of a subsequently grown crystal structure in the epitaxial wafer is poor, and the AlN layer also has larger tensile stress and is easy to generate cracks due to the overlarge tensile stress.
Disclosure of Invention
The embodiment of the disclosure provides an epitaxial wafer of a light emitting diode and a preparation method thereof, which can improve the crystal quality of the epitaxial wafer of the ultraviolet light emitting diode and reduce the tensile stress in an AlN layer. The technical scheme is as follows:
in one aspect, the present disclosure provides an epitaxial wafer of a light emitting diode, where the epitaxial wafer includes a substrate, and a first high-temperature AlN buffer layer, a superlattice layer, a second high-temperature AlN buffer layer, an AlGaN transition layer, an n-type AlGaN layer, a multiple quantum well layer, and a p-type layer that are sequentially formed on the substrate, where the superlattice layer includes a plurality of AlN layers and a plurality of SiN layers that are alternately stacked.
Optionally, the number of the alternately laminated AlN layers and SiN layers is 20-40.
Optionally, the AlN layer has a thickness of 1nm to 100nm, and the SiN layer has a thickness of 1nm to 100 nm.
Optionally, the first high-temperature AlN buffer layer has a thickness of 100nm to 500 nm.
Optionally, the second high-temperature AlN buffer layer has a thickness of 1000nm to 2000 nm.
On the other hand, the embodiment of the present disclosure further provides a preparation method of an epitaxial wafer of a light emitting diode, where the preparation method includes:
providing a substrate;
and sequentially epitaxially growing a first high-temperature AlN buffer layer, a superlattice layer, a second high-temperature AlN buffer layer, an AlGaN transition layer, an n-type AlGaN layer, a multi-quantum well layer and a p-type layer on the substrate, wherein the superlattice layer comprises a plurality of AlN layers and a plurality of SiN layers which are alternately stacked.
Optionally, the growth temperature of the first high-temperature AlN buffer layer is 1200 ℃ to 1300 ℃, and the growth pressure is 30mbar to 70 mbar.
Optionally, the growth temperature of the superlattice layer is 1300-1400 ℃, and the growth pressure is 30-70 mbar.
Optionally, the growth temperature of the second high-temperature AlN buffer layer is 1300 ℃ to 1400 ℃, and the growth pressure is 30mbar to 70 mbar.
Optionally, the growth pressure of the first high-temperature AlN buffer layer, the superlattice layer, and the second high-temperature AlN buffer layer are the same.
The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure at least comprise:
the first high-temperature AlN buffer layer, the superlattice layer and the second high-temperature AlN buffer layer are stacked on the surface of the substrate, the superlattice layer comprises a plurality of AlN layers and a plurality of SiN layers which are stacked alternately, the SiN layers can play a role in blocking threading dislocation, the AlN layers and the SiN layers which are stacked alternately can enable dislocation extending from the first high-temperature AlN buffer layer to bend, the probability that dislocation is annihilated mutually is increased, the crystal quality of AlN is better and better in the stacking direction of each layer, the integral crystal quality of the epitaxial wafer is favorably improved, the tensile stress in the AlN material can be relieved by the superlattice layer, cracks caused by overlarge tensile stress of the AlN material are avoided, the integral crystal quality of the epitaxial wafer is further improved, and the light emitting efficiency of the ultraviolet LED is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an epitaxial wafer of a light emitting diode provided in an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 3 is a flowchart of another method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 4 is a schematic view illustrating a manufacturing process of an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 5 is a schematic view illustrating a manufacturing process of an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 6 is a schematic view illustrating a manufacturing process of an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 7 is a schematic view illustrating a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 8 is a schematic view illustrating a process for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 9 is a schematic view illustrating a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 10 is a schematic view illustrating a process for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 11 is a schematic view illustrating a process for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 12 is a schematic view of a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an epitaxial wafer of a light emitting diode provided in an embodiment of the present disclosure. As shown in fig. 1, the epitaxial wafer includes a substrate 10, and a first high-temperature AlN buffer layer 20, a superlattice layer 30, a second high-temperature AlN buffer layer 40, an AlGaN transition layer 50, an n-type AlGaN layer 60, a multiple quantum well layer 70, and a p-type layer 80, which are sequentially formed on the substrate 10. The superlattice layer 30 includes a plurality of AlN layers 31 and a plurality of SiN layers 32 alternately stacked.
The first high-temperature AlN buffer layer, the superlattice layer and the second high-temperature AlN buffer layer are stacked on the surface of the substrate, the superlattice layer comprises a plurality of AlN layers and a plurality of SiN layers which are stacked alternately, the SiN layers can play a role in blocking threading dislocation, the AlN layers and the SiN layers which are stacked alternately can enable dislocation extending from the first high-temperature AlN buffer layer to bend, the probability that dislocation is annihilated mutually is increased, the crystal quality of AlN is better and better in the stacking direction of each layer, the integral crystal quality of the epitaxial wafer is favorably improved, the tensile stress in the AlN material can be relieved by the superlattice layer, cracks caused by overlarge tensile stress of the AlN material are avoided, the integral crystal quality of the epitaxial wafer is further improved, and the light emitting efficiency of the ultraviolet LED is improved.
Illustratively, the substrate 10 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate 10 may be a flat substrate or a patterned substrate.
As an example, in the embodiments of the present disclosure, the substrate 10 is a sapphire substrate. The sapphire substrate is a common substrate, the technology is mature, and the cost is low. The substrate can be a patterned sapphire substrate or a sapphire flat sheet substrate.
Optionally, the thickness of the first high-temperature AlN buffer layer 20 may be 100nm to 500nm, the thicknesses of the grown first high-temperature AlN buffer layers 20 are different, and the quality of the finally formed epitaxial layers is also different, if the thickness of the first high-temperature AlN buffer layer 20 is too thin, the surface of the first high-temperature AlN buffer layer 20 is loose and rough, and a good template cannot be provided for the growth of the subsequent structure, and along with the increase of the thickness of the first high-temperature AlN buffer layer 20, the surface of the first high-temperature AlN buffer layer 20 gradually becomes dense and flat, which is beneficial to the growth of the subsequent structure, but if the thickness of the first high-temperature AlN buffer layer 20 is too thick, the surface of the first high-temperature AlN buffer layer 20 is too dense, which is not beneficial to the growth of the subsequent structure, and cannot reduce lattice defects in the epitaxial layers.
As an example, in the embodiments of the present disclosure, the thickness of the first high-temperature AlN buffer layer 20 is 250 nm.
Optionally, the superlattice layer 30 has a thickness of 100nm to 1000 nm. The superlattice layer 30 is too thin to block extension of dislocation defects, so that the improvement effect on the light emitting efficiency of the ultraviolet LED is not obvious, and the superlattice layer 30 is too thick, so that the resistance is increased, and the absorption of the superlattice layer 30 to light rays is increased, so that the light emitting efficiency is reduced.
As an example, in the disclosed embodiment, the superlattice layer 30 has a thickness of 500 nm.
Alternatively, the number of cycles of alternately stacking the AlN layer 31 and the SiN layer 32 is 20 to 40.
The AlN layer 31 and the SiN layer 32 in a plurality of cycles gradually bend dislocations extending from the first high-temperature AlN buffer layer 20, annihilate each other, and gradually improve the crystal quality. Too few cycles of alternately stacking the AlN layer 31 and the SiN layer 32 are insufficient to obtain a crystal of good quality.
By way of example, in the disclosed embodiment, the number of cycles of superlattice layer 30 is 30.
Note that fig. 1 shows only a part of the structure of the superlattice layer 30, and is not intended to limit the number of cycles in which the AlN layer 31 and the SiN layer 32 are alternately stacked.
Alternatively, the AlN layer 31 has a thickness of 1nm to 100nm, and the SiN layer 32 has a thickness of 1nm to 100 nm.
As an example, in the embodiment of the present disclosure, the AlN layer 31 has a thickness of 10nm, the SiN layer 32 has a thickness of 7nm, and the SiN layer 32 has a thickness that is too thin to reduce dislocation defects. The AlN layer 31 may have the same or different thickness and the SiN layer 32 may have the same or different thickness in different periods. For example, the SiN layer 32 is gradually reduced in thickness.
Alternatively, the second high-temperature AlN buffer layer 40 has a thickness of 1000nm to 2000 nm.
As an example, in the presently disclosed embodiment, the thickness of the second high-temperature AlN buffer layer 40 is 1500 nm.
Optionally, the AlGaN transition layer 50 may have a thickness of 50nm to 5000nm, and in the embodiment of the present disclosure, the AlGaN transition layer 50 has a thickness of 700 nm.
Alternatively, the thickness of the n-type AlGaN layer 60 may be 600nm to 800nm, and in the embodiment of the present disclosure, the thickness of the n-type AlGaN layer 60 is 700 nm.
Optionally, the doping concentration of Si in the n-type AlGaN layer 60 is 1017cm-3～1018cm-3. Too high a doping concentration of Si may reduce crystal quality, resulting in increased defects, and too low a doping concentration of Si may reduce the conductivity of the n-type AlGaN layer 60. The doping concentration of Si is controlled to 1017cm-3～1018cm-3The n-type AlGaN layer 60 can have a good crystal quality and also have a sufficient conductivity.
As an example, in the embodiment of the present disclosure, the doping concentration of Si in the n-type AlGaN layer 60 is 5 × 1017cm-3。
Optionally, the MQW layer 70 comprises 3-8 AlxGa1-xN quantum well layer 71 and AlyGa1-yAnd the N quantum barrier layers 72, wherein x is more than 0 and less than y is less than 1. That is, the MQW layer 70 includes 3 to 8 periods of Al alternately stackedxGa1-xN quantum well layer 71 and AlyGa1-yN quantum barrier layer 72.
As an example, in the embodiment of the present disclosure, the multiple quantum well layer 70 includes 5 periods of Al alternately stackedxGa1-xN quantum well layer 71 and AlyGa1-yN quantum barrier layer 72.
Alternatively, AlxGa1-xThe thickness of the N quantum well layer 71 may be 2nm to 4 nm. Al (Al)yGa1-yThe thickness of the N quantum barrier layer 72 can be 9-14 nm.
Exemplarily, in the embodiments of the present disclosure, AlxGa1-xThe thickness of the N quantum well layer 71 was 3 nm. Al (Al)yGa1-yThe thickness of the N quantum barrier layer 72 is 11 nm.
Note that fig. 1 shows only a multiple quantum wellPartial structure in layer 70, not intended to limit AlxGa1-xN quantum well layer 71 and AlyGa1-yThe number of cycles of the N quantum barrier layers 72 alternately stacked, and Al may be grown on the N-type AlGaN layer 60 in the case of growing the multiple quantum well layer 70yGa1-yN quantum barrier layer 72.
In the embodiment of the present disclosure, the p-type layer 80 includes a p-type barrier layer 81, a p-type AlGaN layer 82, and a p-type GaN layer 83, which are sequentially stacked on the multiple quantum well layer 70. The p-type barrier layer 81, the p-type AlGaN layer 82, and the p-type GaN layer 83 are all Mg doped.
Illustratively, the p-type barrier layer 81 is a p-type AlGaN barrier layer.
The p-type AlGaN barrier layer may have a thickness of 5nm to 15 nm. As an example, in the embodiments of the present disclosure, the thickness of the p-type AlGaN barrier layer is 10 nm. If the thickness of the p-type AlGaN blocking layer is too thin, the blocking effect on electrons is reduced, and if the thickness of the p-type AlGaN blocking layer is too thick, the absorption of light by the p-type AlGaN blocking layer is increased, which reduces the light emission efficiency of the LED.
In some examples, the p-type AlGaN layer 82 has a thickness of 20nm to 30 nm. As an example, in the disclosed embodiment, the p-type AlGaN layer 82 has a thickness of 25 nm.
Alternatively, the thickness of the p-type GaN layer 83 may be 20nm to 70 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type GaN layer 83 is 50 nm.
Fig. 2 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure. The method is used to manufacture the epitaxial wafer shown in fig. 1. As shown in fig. 2, the manufacturing method includes:
s11: a substrate 10 is provided.
S12: a first high-temperature AlN buffer layer 20, a superlattice layer 30, a second high-temperature AlN buffer layer 40, an AlGaN transition layer 50, an n-type AlGaN layer 60, a multiple quantum well layer 70, and a p-type layer 80 are epitaxially grown in this order on a substrate 10.
The superlattice layer 30 includes a plurality of AlN layers 31 and a plurality of SiN layers 32 alternately stacked.
The first high-temperature AlN buffer layer, the superlattice layer and the second high-temperature AlN buffer layer are stacked on the surface of the substrate, the superlattice layer comprises a plurality of AlN layers and a plurality of SiN layers which are stacked alternately, the SiN layers can play a role in blocking threading dislocation, the AlN layers and the SiN layers which are stacked alternately can enable dislocation extending from the first high-temperature AlN buffer layer to bend, the probability that dislocation is annihilated mutually is increased, the crystal quality of AlN is better and better in the stacking direction of each layer, the integral crystal quality of the epitaxial wafer is favorably improved, the tensile stress in the AlN material can be relieved by the superlattice layer, cracks caused by overlarge tensile stress of the AlN material are avoided, the integral crystal quality of the epitaxial wafer is further improved, and the light emitting efficiency of the ultraviolet LED is improved.
Fig. 3 is a flowchart of another method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure, where the method is used for manufacturing the epitaxial wafer shown in fig. 1. The manufacturing method provided in fig. 3 will be described in detail with reference to fig. 4 to 12:
s21: a substrate 10 is provided.
Alternatively, the substrate 10 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate 10 may be a flat substrate or a patterned substrate.
As an example, in the embodiments of the present disclosure, the substrate 10 is a sapphire substrate. The sapphire substrate is a common substrate, the technology is mature, and the cost is low. The substrate can be a patterned sapphire substrate or a sapphire flat sheet substrate.
In step S21, the sapphire substrate may be pretreated, placed in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and subjected to a baking process for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the baking process was performed on the sapphire substrate for 15 minutes.
Specifically, the baking temperature can be 1000-1200 ℃, and the pressure in the MOCVD reaction chamber during baking can be 100-200 mbar.
S22: a first high temperature AlN buffer layer 20 is epitaxially grown on the substrate 10.
As shown in fig. 4, a first high-temperature AlN buffer layer 20 is grown on the substrate 10.
The thickness of the first high-temperature AlN buffer layer 20 may be 100nm to 500nm, the thicknesses of the grown first high-temperature AlN buffer layers 20 are different, the quality of the finally formed epitaxial layers is also different, if the thickness of the first high-temperature AlN buffer layer 20 is too thin, the surface of the first high-temperature AlN buffer layer 20 is loose and rough, a good template cannot be provided for the growth of the subsequent structure, along with the increase of the thickness of the first high-temperature AlN buffer layer 20, the surface of the first high-temperature AlN buffer layer 20 gradually becomes dense and smooth, which is beneficial to the growth of the subsequent structure, but if the thickness of the first high-temperature AlN buffer layer 20 is too thick, the surface of the first high-temperature AlN buffer layer 20 is too dense, which is not beneficial to the growth of the subsequent structure, and cannot reduce lattice defects in the epitaxial layers.
Optionally, the growth temperature of the first high-temperature AlN buffer layer 20 is 1200 to 1300 ℃. As an example, in the presently disclosed embodiment, the growth temperature of the first high-temperature AlN buffer layer 20 is 1250 ℃.
Optionally, the growth pressure of the first high-temperature AlN buffer layer 20 is 30mbar to 70 mbar. As an example, in the embodiments of the present disclosure, the growth pressure of the first high-temperature AlN buffer layer 20 is 50 mbar.
S23: a superlattice layer 30 is grown on the first high-temperature AlN buffer layer 20.
As shown in fig. 5, a superlattice layer 30 is grown on the first high-temperature AlN buffer layer 20.
The superlattice layer 30 includes a plurality of AlN layers 31 and a plurality of SiN layers 32 alternately stacked. Alternatively, the number of cycles of alternately stacking the AlN layer 31 and the SiN layer 32 is 20 to 40. By way of example, in the disclosed embodiment, the number of cycles of superlattice layer 30 is 30.
Note that fig. 5 shows only a part of the structure of the superlattice layer 30, and is not intended to limit the number of cycles in which the AlN layer 31 and the SiN layer 32 are alternately stacked.
In the superlattice layer 30, the growth temperatures of the AlN layer 31 and the SiN layer 32 may be the same or different. As an example, in the embodiment of the present disclosure, the growth temperatures of the AlN layer 31 and the SiN layer 32 are the same, and the AlN layer 31 and the SiN layer 32 are alternately grown at the same growth temperature, which is more convenient to operate and simpler in process.
Optionally, the growth temperature of the superlattice layer 30 is 1300-1400 ℃. As an example, in the disclosed embodiment, the growth temperature of the superlattice layer 30 is 1350 ℃.
In the superlattice layer 30, the growth pressures of the AlN layer 31 and the SiN layer 32 may be the same or different. As an example, in the embodiment of the present disclosure, the growth pressure of the AlN layer 31 and the SiN layer 32 is also the same, and the AlN layer 31 and the SiN layer 32 are alternately grown with the same growth pressure, which is more convenient to operate and simpler in process.
Optionally, the growth pressure of the superlattice layer 30 is 30mbar to 70 mbar. As an example, in embodiments of the present disclosure, the growth pressure of superlattice layer 30 is 50 mbar.
In the embodiment of the present disclosure, 30 AlN layers 31 and 30 SiN layers 32 are grown by periodically and alternately introducing TMAl and silane into the reaction chamber, so as to obtain the superlattice layer 30.
Optionally, the superlattice layer 30 has a thickness of 100nm to 1000 nm. As an example, in the disclosed embodiment, the superlattice layer 30 has a thickness of 500 nm.
Alternatively, the AlN layer 31 has a thickness of 1nm to 100nm, and the SiN layer 32 has a thickness of 1nm to 100 nm. As an example, in the embodiment of the present disclosure, the AlN layer 31 has a thickness of 10nm, and the SiN layer 32 has a thickness of 7 nm.
S24: a second high-temperature AlN buffer layer 40 is grown on the superlattice layer 30.
As shown in fig. 6, a second high-temperature AlN buffer layer 40 is grown on the superlattice layer 30.
The growth temperature of the second high-temperature AlN buffer layer 40 is higher than the growth temperature of the first high-temperature AlN buffer layer 20 and the growth temperature of the superlattice layer 30.
Optionally, the growth temperature of the second high-temperature AlN buffer layer 40 is 1300 ℃ to 1400 ℃.
As an example, in the presently disclosed embodiment, the growth temperature of the second high-temperature AlN buffer layer 40 is 1370 ℃.
Optionally, the growth pressure of the first high-temperature AlN buffer layer 20, the superlattice layer 30, and the second high-temperature AlN buffer layer 40 are all the same. The first high-temperature AlN buffer layer 20, the superlattice layer 30 and the second high-temperature AlN buffer layer 40 are grown under the same growth pressure, and the process is simpler.
Illustratively, the growth pressure of the second high-temperature AlN buffer layer 40 is 30mbar to 70 mbar. For example, in the embodiments of the present disclosure, the growth pressure of the second high-temperature AlN buffer layer 40 is 50 mbar.
In the embodiment of the present disclosure, the first high-temperature AlN buffer layer 20, the superlattice layer 30, and the second high-temperature AlN buffer layer 40 are all grown at the same growth temperature, which is more convenient for the process.
S25: an AlGaN transition layer 50 is grown on the second high-temperature AlN buffer layer 40.
As shown in fig. 7, an AlGaN transition layer 50 is grown on the second high-temperature AlN buffer layer 40.
Optionally, the growth temperature of the AlGaN transition layer 50 is 1280 ℃ to 1320 ℃.
As an example, in the embodiment of the present disclosure, the growth temperature of the AlGaN transition layer 50 is 1300 ℃.
Optionally, the growth pressure of the AlGaN transition layer 50 is 120mbar to 180 mbar. As an example, in the embodiments of the present disclosure, the growth pressure of the AlGaN transition layer 50 is 150 mbar.
Optionally, the AlGaN transition layer 50 may have a thickness of 50nm to 5000nm, and in the embodiment of the present disclosure, the AlGaN transition layer 50 has a thickness of 700 nm.
S26: an n-type AlGaN layer 60 is grown on the AlGaN transition layer 50.
As shown in fig. 8, an n-type AlGaN layer 60 is grown on the AlGaN transition layer 50.
Optionally, the growth temperature of the n-type AlGaN layer 60 is 1000 ℃ to 1100 ℃. As an example, in the embodiments of the present disclosure, the growth temperature of the n-type AlGaN layer 60 is 1060 ℃.
Alternatively, the growth pressure of the n-type AlGaN layer 60 may be 80mbar to 110 mbar. As an example, in embodiments of the present disclosure, the growth pressure of the n-type AlGaN layer 60 is 100 mbar.
When the n-type AlGaN layer 60 is grown, silane doping is performed, and the Si doping concentration in the n-type AlGaN layer 60 may be 1017cm-3～1018cm-3. As an example, the disclosure implementsIn the example, the doping concentration of Si in the n-type AlGaN layer 60 is 5X 1017cm-3。
The thickness of the n-type AlGaN layer 60 may be 600nm to 800nm, and in the embodiment of the present disclosure, the thickness of the n-type AlGaN layer 60 is 700 nm.
S27: a multiple quantum well layer 70 is grown on the n-type AlGaN layer 60.
As shown in fig. 9, a multiple quantum well layer 70 is grown on the n-type AlGaN layer 60.
In practice, the MQW layer 70 may include a plurality of layers of Al alternately stackedxGa1-xN quantum well layer 71 and multilayer AlyGa1-yAnd the N quantum barrier layers 72, wherein x is more than 0 and less than y is less than 1.
Alternatively, AlxGa1-xN quantum well layer 71 and AlyGa1-yThe number of the alternately stacked N quantum barrier layers 72 may be 3-8. Exemplarily, in the embodiments of the present disclosure, AlxGa1-xN quantum well layer 71 and AlyGa1-yThe number of cycles of the N quantum barrier layers 72 stacked alternately is 5.
Note that fig. 9 shows only a partial structure of the multiple quantum well layer 70, and is not intended to limit AlxGa1-xN quantum well layer 71 and AlyGa1-yThe number of cycles of the N quantum barrier layers 72 alternately stacked, and Al may be grown on the N-type AlGaN layer 60 in the case of growing the multiple quantum well layer 70yGa1-yN quantum barrier layer 72.
Alternatively, AlxGa1-xThe thickness of the N quantum well layer 71 may be 2nm to 4 nm. Al (Al)yGa1-yThe thickness of the N quantum barrier layer 72 can be 9-14 nm.
Exemplarily, in the embodiments of the present disclosure, AlxGa1-xThe thickness of the N quantum well layer 71 was 3 nm. Al (Al)yGa1-yThe thickness of the N quantum barrier layer 72 is 11 nm.
After the multi-quantum well layer 70 is grown, a p-type layer 80 is grown on the multi-quantum well layer 70, and in the embodiment of the present disclosure, the p-type layer 80 includes a p-type barrier layer 81, a p-type AlGaN layer 82, and a p-type GaN layer 83, which are sequentially stacked on the multi-quantum well layer 70. The p-type barrier layer 81, the p-type AlGaN layer 82, and the p-type GaN layer 83 are all Mg doped. The growth of the p-type layer 80 includes steps S28 to S30 as follows.
S28: a p-type barrier layer 81 is grown on the multiple quantum well layer 70.
As shown in fig. 10, a p-type barrier layer 81 is grown on the multiple quantum well layer 70.
Alternatively, the p-type barrier layer 81 may be a p-type AlGaN barrier layer.
Specifically, the growth temperature of the p-type barrier layer 81 may be 960 ℃ to 990 ℃, and in the embodiment of the present disclosure, the growth temperature of the p-type barrier layer 81 is 980 ℃, as an example.
Specifically, the growth pressure of the p-type barrier layer 81 may be 100mbar to 200 mbar. As an example, in the embodiments of the present disclosure, the growth pressure of the p-type barrier layer 81 is 150 mbar.
Alternatively, the p-type barrier layer 81 may have a thickness of 5nm to 15 nm. As an example, in the embodiments of the present disclosure, the thickness of the p-type barrier layer 81 is 10 nm. If the thickness of the p-type blocking layer 81 is too thin, the blocking effect on electrons is reduced, and if the thickness of the p-type blocking layer 81 is too thick, the absorption of light by the p-type blocking layer 81 is increased, thereby reducing the light emission efficiency of the LED.
S29: a p-type AlGaN layer 82 is grown on the p-type barrier layer 81.
As shown in fig. 11, a p-type AlGaN layer 82 is grown on the p-type barrier layer 81.
Specifically, the growth temperature of the p-type AlGaN layer 82 may be 880 ℃ to 920 ℃, and as an example, in the embodiment of the present disclosure, the growth temperature of the p-type AlGaN layer 82 is 900 ℃.
Specifically, the growth pressure of the p-type AlGaN layer 82 may be 180mbar to 220 mbar. As an example, in the disclosed embodiment, the growth pressure of p-type AlGaN layer 82 is 200 mbar.
Alternatively, the thickness of the p-type AlGaN layer 82 may be 20nm to 30 nm. As an example, in the disclosed embodiment, the p-type AlGaN layer 82 has a thickness of 25 nm.
S30: a p-type GaN layer 83 is grown on the p-type AlGaN layer 82.
As shown in fig. 12, a p-type GaN layer 83 is grown on the p-type AlGaN layer 82.
Alternatively, the growth temperature of the p-type GaN layer 83 may be 800 deg.C to 900 deg.C. As an example, in the embodiment of the present disclosure, the growth temperature of the p-type GaN layer 83 is 850 ℃.
Alternatively, the growth pressure of the p-type GaN layer 83 may be 250mbar to 350 mbar. As an example, in the embodiments of the present disclosure, the growth pressure of the p-type GaN layer 83 is 300 mbar.
Alternatively, the thickness of the p-type GaN layer 83 may be 20nm to 70 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type GaN layer 83 is 50 nm.
When the p-type barrier layer 81, the p-type AlGaN layer 82, and the p-type GaN layer 83 are grown, Mg doping is performed using cyclopentadienyl magnesium with trimethyl gallium or triethyl gallium as a gallium source.
S31: and annealing the epitaxial wafer.
Alternatively, the annealing may be performed for 30 minutes under nitrogen gas atmosphere to end the growth of the epitaxial wafer. And then the heating system and the gas supply system are closed, and the temperature of the reaction cavity is reduced to room temperature.
Annealing the epitaxial wafer, and performing subsequent processing on the epitaxial wafer to prepare the LED.
In particular implementations, embodiments of the present disclosure may employ high purity H2Or/and N2As carrier gas, TEGa or TMGa is used as Ga source, TMIn is used as In source, SiH4As n-type dopant TMAl as aluminium source, Cp2Mg as a p-type dopant.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims (10)

1. An epitaxial wafer of a light emitting diode, characterized in that the epitaxial wafer comprises a substrate (10) and a first high-temperature AlN buffer layer (20), a superlattice layer (30), a second high-temperature AlN buffer layer (40), an AlGaN transition layer (50), an n-type AlGaN layer (60), a multiple quantum well layer (70), and a p-type layer (80) which are sequentially formed on the substrate (10), wherein the superlattice layer (30) comprises a plurality of AlN layers (31) and a plurality of SiN layers (32) which are alternately stacked.
2. The epitaxial wafer according to claim 1, wherein the number of cycles of the AlN layers (31) and the SiN layers (32) alternately stacked is 20 to 40.
3. Epitaxial wafer according to claim 1 or 2, characterized in that the AlN layer (31) has a thickness of 1nm to 100nm and the SiN layer (32) has a thickness of 1nm to 100 nm.
4. An epitaxial wafer according to claim 1 or 2, characterised in that the thickness of the first high temperature AlN buffer layer (20) is between 100nm and 500 nm.
5. Epitaxial wafer according to claim 1 or 2, characterized in that the thickness of the second high temperature AlN buffer layer (40) is 1000nm to 2000 nm.
6. A preparation method of an epitaxial wafer of a light-emitting diode is characterized by comprising the following steps:
providing a substrate (10);
and epitaxially growing a first high-temperature AlN buffer layer (20), a superlattice layer (30), a second high-temperature AlN buffer layer (40), an AlGaN transition layer (50), an n-type AlGaN layer (60), a multi-quantum well layer (70) and a p-type layer (80) on the substrate (10) in sequence, wherein the superlattice layer (30) comprises a plurality of AlN layers (31) and a plurality of SiN layers (32) which are alternately stacked.
7. The production method according to claim 6, wherein the first high-temperature AlN buffer layer (20) has a growth temperature of 1200 to 1300 ℃ and a growth pressure of 30 to 70 mbar.
8. The production method according to claim 6 or 7, characterized in that the growth temperature of the superlattice layer (30) is 1300 ℃ to 1400 ℃, and the growth pressure is 30mbar to 70 mbar.
9. The production method according to claim 6 or 7, wherein the second high-temperature AlN buffer layer (40) has a growth temperature of 1300 ℃ to 1400 ℃ and a growth pressure of 30mbar to 70 mbar.
10. The production method according to claim 6 or 7, wherein the growth pressures of the first high-temperature AlN buffer layer (20), the superlattice layer (30), and the second high-temperature AlN buffer layer (40) are the same.
CN202011623709.9A 2020-12-31 2020-12-31 Epitaxial wafer of light-emitting diode and preparation method thereof Active CN112786746B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011623709.9A CN112786746B (en) 2020-12-31 2020-12-31 Epitaxial wafer of light-emitting diode and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011623709.9A CN112786746B (en) 2020-12-31 2020-12-31 Epitaxial wafer of light-emitting diode and preparation method thereof

Publications (2)

Publication Number Publication Date
CN112786746A true CN112786746A (en) 2021-05-11
CN112786746B CN112786746B (en) 2024-02-13

Family

ID=75754395

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011623709.9A Active CN112786746B (en) 2020-12-31 2020-12-31 Epitaxial wafer of light-emitting diode and preparation method thereof

Country Status (1)

Country Link
CN (1) CN112786746B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116093221A (en) * 2023-04-10 2023-05-09 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847046B1 (en) * 2003-10-31 2005-01-25 Epitech Corporation, Ltd. Light-emitting device and method for manufacturing the same
CN101645480A (en) * 2009-06-22 2010-02-10 武汉华灿光电有限公司 Method for enhancing antistatic ability of GaN-based light-emitting diode
CN104300047A (en) * 2014-10-11 2015-01-21 北京工业大学 Si-based GaN LED structure and manufacturing method thereof
CN106601883A (en) * 2016-11-26 2017-04-26 华灿光电（浙江）有限公司 Epitaxial wafer of light emitting diode and preparation method
CN106684139A (en) * 2015-11-11 2017-05-17 中国科学院苏州纳米技术与纳米仿生研究所 Si substrate-based GaN epitaxial structure and preparation method therefor
CN106784216A (en) * 2016-11-26 2017-05-31 华灿光电（浙江）有限公司 Epitaxial wafer of GaN-based light emitting diode and growth method thereof
CN107895753A (en) * 2017-11-14 2018-04-10 厦门乾照光电股份有限公司 A kind of Si substrate LEDs and preparation method
CN111564538A (en) * 2020-06-01 2020-08-21 江西新正耀光学研究院有限公司 Ultraviolet light emitting diode epitaxial structure and preparation method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105742428A (en) * 2016-02-03 2016-07-06 华灿光电(苏州）有限公司 Light-emitting diode epitaxial wafer and preparation method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847046B1 (en) * 2003-10-31 2005-01-25 Epitech Corporation, Ltd. Light-emitting device and method for manufacturing the same
CN101645480A (en) * 2009-06-22 2010-02-10 武汉华灿光电有限公司 Method for enhancing antistatic ability of GaN-based light-emitting diode
CN104300047A (en) * 2014-10-11 2015-01-21 北京工业大学 Si-based GaN LED structure and manufacturing method thereof
CN106684139A (en) * 2015-11-11 2017-05-17 中国科学院苏州纳米技术与纳米仿生研究所 Si substrate-based GaN epitaxial structure and preparation method therefor
CN106601883A (en) * 2016-11-26 2017-04-26 华灿光电（浙江）有限公司 Epitaxial wafer of light emitting diode and preparation method
CN106784216A (en) * 2016-11-26 2017-05-31 华灿光电（浙江）有限公司 Epitaxial wafer of GaN-based light emitting diode and growth method thereof
CN107895753A (en) * 2017-11-14 2018-04-10 厦门乾照光电股份有限公司 A kind of Si substrate LEDs and preparation method
CN111564538A (en) * 2020-06-01 2020-08-21 江西新正耀光学研究院有限公司 Ultraviolet light emitting diode epitaxial structure and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116093221A (en) * 2023-04-10 2023-05-09 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Also Published As

Publication number Publication date
CN112786746B (en) 2024-02-13

Similar Documents

Publication Publication Date Title
CN109119515B (en) Light emitting diode epitaxial wafer and manufacturing method thereof
CN112582508B (en) Epitaxial wafer of light emitting diode and preparation method thereof
CN108336203A (en) A kind of gallium nitride based LED epitaxial slice and its manufacturing method
CN116072780B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN113690350B (en) Micro light-emitting diode epitaxial wafer and manufacturing method thereof
CN113571616B (en) AlGaN-based deep ultraviolet light-emitting diode epitaxial wafer and preparation method thereof
CN113284994B (en) Epitaxial wafer of deep ultraviolet light-emitting diode and preparation method thereof
CN109994580B (en) Epitaxial wafer of light emitting diode and manufacturing method thereof
CN112802929A (en) Epitaxial wafer of light emitting diode and preparation method thereof
CN113161453B (en) Light emitting diode epitaxial wafer and manufacturing method thereof
CN112786746B (en) Epitaxial wafer of light-emitting diode and preparation method thereof
CN112802931A (en) Epitaxial wafer of light emitting diode and preparation method thereof
CN114784150A (en) Epitaxial wafer of deep ultraviolet light-emitting diode and preparation method thereof
CN113571617B (en) Epitaxial wafer of deep ultraviolet light-emitting diode and preparation method thereof
CN112768575A (en) Epitaxial wafer of light emitting diode and preparation method thereof
CN113113518B (en) Light emitting diode epitaxial wafer and preparation method thereof
CN113571615B (en) Light emitting diode epitaxial wafer for improving ohmic contact and manufacturing method thereof
CN113013299B (en) Light emitting diode epitaxial wafer and growth method thereof
CN112466999B (en) Epitaxial wafer of light emitting diode and manufacturing method thereof
CN113161462B (en) Light emitting diode epitaxial wafer and manufacturing method thereof
CN113571607B (en) High-luminous-efficiency light-emitting diode epitaxial wafer and manufacturing method thereof
CN113284995A (en) Epitaxial wafer of deep ultraviolet light-emitting diode and preparation method thereof
CN114824001A (en) Epitaxial wafer, epitaxial wafer preparation method and light emitting diode
CN114203871A (en) Ultraviolet light-emitting diode epitaxial wafer and preparation method thereof
CN112786745B (en) Epitaxial wafer of light emitting diode and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP03 Change of name, title or address

Address after: No.233, Sufu Road, Suxi Town, Yiwu City, Jinhua City, Zhejiang Province

Patentee after: BOE Huacan Optoelectronics (Zhejiang) Co.,Ltd.

Country or region after: China

Address before: No.233, Sufu Road, Suxi Town, Yiwu City, Jinhua City, Zhejiang Province

Patentee before: HC SEMITEK (ZHEJIANG) Co.,Ltd.

Country or region before: China

CP03 Change of name, title or address