CN112751393A - Equalization chip of series battery pack and battery management system - Google Patents
Equalization chip of series battery pack and battery management system Download PDFInfo
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- CN112751393A CN112751393A CN202110135445.0A CN202110135445A CN112751393A CN 112751393 A CN112751393 A CN 112751393A CN 202110135445 A CN202110135445 A CN 202110135445A CN 112751393 A CN112751393 A CN 112751393A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
- H02J7/0019—Circuits for equalisation of charge between batteries using switched or multiplexed charge circuits
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Abstract
The present disclosure provides an equalizing chip of a series battery, the equalizing chip includes: the first end of the ith control switch of the i control switches is connected with the positive electrode end of the ith battery through a balancing resistor, and the second end of the ith control switch is connected with the positive electrode end of the (i-1) th battery; and i first resistors, a first end of an ith first resistor of the i first resistors being connected to a second end of the ith control switch, and a second end of the ith first resistor being connected to a control end of the ith control switch, the ith control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is larger than the current threshold value, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current equalization on the ith battery, wherein 1 < i ≦ N. The present disclosure also provides a battery management system.
Description
Technical Field
The disclosure relates to an equalization chip of a series battery pack and a battery management system.
Background
A rechargeable battery such as a lithium battery has a high charging and discharging requirement, and when overcharge, overdischarge, overcurrent, short circuit, and the like occur, the pressure and heat inside the lithium battery are greatly increased, and sparks, combustion, and even explosion are easily generated, so that overcharge and overdischarge protection of the lithium battery pack is necessary.
As the batteries are used, the performance of the batteries may not be consistent, and an imbalance may occur, such as during charging and discharging, for example, some batteries may be fully charged, some batteries may not be fully charged, or some batteries may be overcharged. The same is true for the discharge process.
Due to the inconsistency of the individual cells, it is required to take necessary equalization measures during charging to ensure the safety and stability thereof.
In addition, in the prior art, a circuit for equalization control is provided on a printed circuit board, which is not in line with the trend of miniaturization and integration.
Disclosure of Invention
In order to solve one of the above technical problems, the present disclosure provides an equalizing chip and a battery management system for a series battery pack.
According to an embodiment of the present disclosure, an equalizing chip of a series battery pack, the series battery pack including N series-connected cells, where N > 1, the equalizing chip includes:
the first end of the ith control switch of the i control switches is connected with the positive electrode end of the ith battery through a balancing resistor, and the second end of the ith control switch is connected with the positive electrode end of the (i-1) th battery; and
i first resistors, a first terminal of an ith first resistor of the i first resistors being connected to a second terminal of the ith control switch, and a second terminal of the ith first resistor being connected to a control terminal of the ith control switch,
the ith control switch is controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is larger than a current threshold value, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to balance the current of the ith battery, wherein 1 < i ≦ N.
According to the equalizing chip of at least one embodiment of the present disclosure, the i control switches are NMOS transistors, first ends of the i control switches are drains, second ends of the i control switches are sources, and control ends of the i control switches are gates; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
According to at least one embodiment of the present disclosure, the equalizing chip further includes i second resistors, a first end of an ith second resistor of the i second resistors is connected to a control end of the ith control switch, and a second end of the ith second resistor is connected to a second end of the ith first resistor.
The equalizing chip according to at least one embodiment of the present disclosure further includes i first diodes, an anode of an ith first diode of the i first diodes is connected to the first end of the ith control switch, and a cathode of the ith first diode is grounded.
The equalizing chip according to at least one embodiment of the present disclosure further includes i second diodes, an anode of an ith second diode of the i second diodes is connected to the second end of the control switch, and a cathode of the ith second diode is connected to the control end of the control switch.
According to at least one embodiment of this disclosure, the equalizing chip further includes i third diodes, an anode of an ith second triode of the i second triodes is connected to a second end of the (i + 1) th first resistor, and a cathode of the ith second triode is connected to a second end of the ith first resistor.
According to the equalizing chip of at least one embodiment of the present disclosure, a current flowing from the positive terminal of the ith cell to the positive terminal of the (i-1) th cell is controlled by turning on and off the ith first switch of the i first switches, and when the ith first switch is turned on, a current flows from the positive terminal of the ith cell to the positive terminal of the (i-1) th cell.
According to the equalizing chip of at least one embodiment of the present disclosure, the i first switches are integrated in the equalizing chip.
The equalizing chip according to at least one embodiment of the present disclosure further includes i current control circuits, wherein a first end of an ith current control circuit of the i current control circuits is connected to a second end of the (i + 1) th first resistor, and a second end of the ith current control circuit is connected to a second end of the ith first resistor.
According to the equalizing chip of at least one embodiment of the present disclosure, the current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the nth cell and the voltage of the positive terminal of the i-1 st cell.
According to the equalizing chip of at least one embodiment of the present disclosure, when equalizing control needs to be performed on the ith battery, the ith current control circuit operates.
According to the equalizing chip of at least one embodiment of the present disclosure, the i current control circuits respectively include a mirror circuit and a current source that generates a current based on a voltage of the positive terminal of the nth battery and generates a current flowing into the second terminal of the i-th first resistor via the mirror current.
According to the equalizing chip of at least one embodiment of the present disclosure, the current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the i-th cell and the voltage of the positive terminal of the i-1 th cell.
According to the equalizing chip of at least one embodiment of the present disclosure, when equalizing control needs to be performed on the ith battery, the ith current control circuit operates.
According to the equalizing chip of at least one embodiment of the present disclosure, the i current control circuits respectively include a mirror circuit and a current source that generates a current based on a voltage of the positive terminal of the i-th battery and generates a current flowing into the second terminal of the i-th first resistor via the mirror current.
According to another embodiment of the present disclosure, a battery management system includes:
an equalization circuit as described above; and
a battery management chip that measures a voltage of an ith battery via at least the equalization circuit.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.
Fig. 1 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Fig. 2 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Fig. 3 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Fig. 4 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Fig. 5 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Detailed Description
The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.
The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.
When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.
For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.
According to an embodiment of the present disclosure, there is provided an equalizing chip of a series battery pack, the series battery pack including N series-connected batteries, where N > 1, the equalizing chip including: the first end of the ith control switch of the i control switches is connected with the positive electrode end of the ith battery through a balancing resistor, and the second end of the ith control switch is connected with the positive electrode end of the (i-1) th battery; and i first resistors, a first end of an ith first resistor of the i first resistors being connected to a second end of the ith control switch, and a second end of the ith first resistor being connected to a control end of the ith control switch, the ith control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is larger than the current threshold value, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current equalization on the ith battery, wherein 1 < i ≦ N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The control circuit also comprises i second resistors, wherein the first end of the ith second resistor of the i second resistors is connected with the control end of the ith control switch, and the second end of the ith second resistor is connected with the second end of the ith first resistor.
The power supply also comprises i first diodes, wherein the anode of the ith first diode of the i first diodes is connected to the first end of the ith control switch, and the cathode of the ith first diode is grounded.
The control circuit also comprises i second diodes, wherein the anode of the ith second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the ith second diode is connected with the control end of the control switch.
The power supply also comprises i third diodes, wherein the anode of the ith second triode of the i second triodes is connected with the second end of the (i + 1) th first resistor, and the cathode of the ith second triode is connected with the second end of the ith first resistor.
The current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is controlled by turning on and off the ith first switch of the i first switches, and when the ith first switch is turned on, the current flows from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery.
The i first switches are integrated in the equalization chip.
The current control circuit further comprises i current control circuits, wherein the first end of the ith current control circuit of the i current control circuits is connected to the second end of the (i + 1) th first resistor, and the second end of the ith current control circuit is connected to the second end of the ith first resistor.
The current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the nth battery and the voltage of the positive terminal of the i-1 st battery.
And when the ith battery needs to be subjected to balance control, the ith current control circuit works.
The i current control circuits each include a mirror circuit and a current source that generates a current based on a voltage of the positive terminal of the nth battery and generates a current flowing into the second terminal of the i-th first resistor via the mirror current.
The current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the i-th battery and the voltage of the positive terminal of the i-1 th battery.
And when the ith battery needs to be subjected to balance control, the ith current control circuit works.
The i current control circuits each include a mirror circuit and a current source that generates a current based on a voltage of the positive terminal of the i-th battery and generates a current flowing into the second terminal of the i-th first resistor via the mirror current.
The technical solution of the present disclosure will be explained below with reference to the accompanying drawings.
< first embodiment >
Fig. 1 shows an equalization chip according to a first embodiment of the present disclosure. The series battery pack 100 includes N batteries 101, 102, … …, 10N connected in series.
The equalizing chip 200 includes: the first end of the ith control switch of the i control switches 211, 212 and … … 21n is connected with the positive terminal of the ith battery through equalizing resistors 401, 402, … … and 40n, and the second end of the ith control switch is connected with the positive terminal of the (i-1) th battery; and i first resistors 231, 232, … …, 23n, a first terminal of an ith first resistor of the i first resistors being connected to a second terminal of the ith control switch, and a second terminal of the ith first resistor being connected to a control terminal of the ith control switch, the ith control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is larger than the current threshold value, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current equalization on the ith battery, wherein 1 < i ≦ N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The contents of the 2 nd cell will be taken as an example and the control switch will be set to be an NMOS transistor.
The drain of the NMOS transistor 212 is connected to the positive terminal of the 2 nd cell through the equalizing resistor 402 by a pin, and the source of the NMOS transistor 212 is connected to the positive terminal of the 1 st cell via a pin. The gate of the NMOS transistor 212 is connected to the second resistor 222, and the first resistor 232 is connected between the source of the NMOS transistor 212 and the second resistor 222. When the battery is unbalanced, a current is formed from the positive terminal of the battery 102 through the resistor 23n and the resistor 232, the voltage formed by the resistor 222 and the resistor 232 forms the gate-source voltage of the NMOS transistor 212, when the gate-source voltage is greater than the threshold turn-on voltage, the NMOS transistor 212 is turned on, and an equalizing current flows from the resistor 402 through the NMOS transistor 212, so that the battery 102 is equalized. When no current flows, the gate-source voltage of the NMOS transistor 212 is zero, and the NMOS transistor 212 is turned off, and then the equalization control is not performed.
In addition, i first diodes 251, 252, … …, 25n are also included, wherein the anode of the ith first diode of the i first diodes is connected to the first end of the ith control switch, and the cathode of the ith first diode is grounded. For example, the diode 252 has an anode connected to the drain of the control switch 212 and a cathode connected to ground for protecting the drain of the control switch 212.
And the control circuit further comprises i second diodes 241, 242 and … … 24n, wherein the anode of the ith second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the ith second diode is connected with the control end of the control switch. For example, diode 242 has an anode connected to the gate of transistor 212 and a cathode connected to the source of transistor 212 for protecting the gate oxide of transistor 212.
The first diode further comprises i third diodes 261, 262, … … and 26n, wherein the anode of the ith second triode of the i second triodes is connected with the second end of the (i + 1) th first resistor, and the cathode of the ith second triode is connected with the second end of the ith first resistor. For example, a diode 262 is connected between the resistors 232 and 23n for protecting the transistor 212.
In addition, the equalization chip 200 is connected to the BMS chip 300 through pins, and the voltage of each battery, etc., may be measured through the BMS chip 300, for example.
< second embodiment >
Fig. 2 shows an equalization chip according to a second embodiment of the present disclosure. The series battery pack 100 includes N batteries 101, 102, … …, 10N connected in series.
The equalizing chip 200 includes: the first end of the ith control switch of the i control switches 211, 212 and … … 21n is connected with the positive terminal of the ith battery through equalizing resistors 401, 402, … … and 40n, and the second end of the ith control switch is connected with the positive terminal of the (i-1) th battery; and i first resistors 231, 232, … …, 23n, a first terminal of an ith first resistor of the i first resistors being connected to a second terminal of the ith control switch, and a second terminal of the ith first resistor being connected to a control terminal of the ith control switch, the ith control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is larger than the current threshold value, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current equalization on the ith battery, wherein 1 < i ≦ N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The contents of the 2 nd cell will be taken as an example and the control switch will be set to be an NMOS transistor.
The drain of the NMOS transistor 212 is connected to the positive terminal of the 2 nd cell through the equalizing resistor 402 by a pin, and the source of the NMOS transistor 212 is connected to the positive terminal of the 1 st cell via a pin. The gate of the NMOS transistor 212 is connected to the second resistor 222, and the first resistor 232 is connected between the source of the NMOS transistor 212 and the second resistor 222. When the battery is unbalanced, a current is formed from the positive terminal of the battery 102 through the resistor 23n and the resistor 232, the voltage formed by the resistor 222 and the resistor 232 forms the gate-source voltage of the NMOS transistor 212, when the gate-source voltage is greater than the threshold turn-on voltage, the NMOS transistor 212 is turned on, and an equalizing current flows from the resistor 402 through the NMOS transistor 212, so that the battery 102 is equalized. When no current flows, the gate-source voltage of the NMOS transistor 212 is zero, and the NMOS transistor 212 is turned off, and then the equalization control is not performed.
In addition, i first diodes 251, 252, … …, 25n are also included, wherein the anode of the ith first diode of the i first diodes is connected to the first end of the ith control switch, and the cathode of the ith first diode is grounded. For example, the diode 252 has an anode connected to the drain of the control switch 212 and a cathode connected to ground for protecting the drain of the control switch 212.
And the control circuit further comprises i second diodes 241, 242 and … … 24n, wherein the anode of the ith second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the ith second diode is connected with the control end of the control switch. For example, diode 242 has an anode connected to the gate of transistor 212 and a cathode connected to the source of transistor 212 for protecting the gate oxide of transistor 212.
The first diode further comprises i third diodes 261, 262, … … and 26n, wherein the anode of the ith second triode of the i second triodes is connected with the second end of the (i + 1) th first resistor, and the cathode of the ith second triode is connected with the second end of the ith first resistor. For example, a diode 262 is connected between the resistors 232 and 23n for protecting the transistor 212.
The second embodiment differs from the first embodiment mainly in that N first switches 311, 312, … …, 31N are added in the second embodiment.
The current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is controlled by turning on and off the ith first switch of the i first switches, and when the ith first switch is turned on, the current flows from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery.
For example, when the 2 nd cell 102 is equalized, the switch 312 is turned on to generate a current, and the transistor 212 is turned on to perform equalization.
As shown in fig. 2, the first switches 311, 312, … …, 31n may be integrated in the BMS chip 300.
In addition, the equalization chip 200 is connected to the BMS chip 300 through pins, and the voltage of each battery, etc., may be measured through the BMS chip 300, for example.
< third embodiment >
Fig. 3 shows an equalization chip according to a third embodiment of the present disclosure. The series battery pack 100 includes N batteries 101, 102, … …, 10N connected in series.
The equalizing chip 200 includes: the first end of the ith control switch of the i control switches 211, 212 and … … 21n is connected with the positive terminal of the ith battery through equalizing resistors 401, 402, … … and 40n, and the second end of the ith control switch is connected with the positive terminal of the (i-1) th battery; and i first resistors 231, 232, … …, 23n, a first terminal of an ith first resistor of the i first resistors being connected to a second terminal of the ith control switch, and a second terminal of the ith first resistor being connected to a control terminal of the ith control switch, the ith control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is larger than the current threshold value, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current equalization on the ith battery, wherein 1 < i ≦ N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The contents of the 2 nd cell will be taken as an example and the control switch will be set to be an NMOS transistor.
The drain of the NMOS transistor 212 is connected to the positive terminal of the 2 nd cell through the equalizing resistor 402 by a pin, and the source of the NMOS transistor 212 is connected to the positive terminal of the 1 st cell via a pin. The gate of the NMOS transistor 212 is connected to the second resistor 222, and the first resistor 232 is connected between the source of the NMOS transistor 212 and the second resistor 222. When the battery is unbalanced, a current is formed from the positive terminal of the battery 102 through the resistor 23n and the resistor 232, the voltage formed by the resistor 222 and the resistor 232 forms the gate-source voltage of the NMOS transistor 212, when the gate-source voltage is greater than the threshold turn-on voltage, the NMOS transistor 212 is turned on, and an equalizing current flows from the resistor 402 through the NMOS transistor 212, so that the battery 102 is equalized. When no current flows, the gate-source voltage of the NMOS transistor 212 is zero, and the NMOS transistor 212 is turned off, and then the equalization control is not performed.
In addition, i first diodes 251, 252, … …, 25n are also included, wherein the anode of the ith first diode of the i first diodes is connected to the first end of the ith control switch, and the cathode of the ith first diode is grounded. For example, the diode 252 has an anode connected to the drain of the control switch 212 and a cathode connected to ground for protecting the drain of the control switch 212.
And the control circuit further comprises i second diodes 241, 242 and … … 24n, wherein the anode of the ith second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the ith second diode is connected with the control end of the control switch. For example, diode 242 has an anode connected to the gate of transistor 212 and a cathode connected to the source of transistor 212 for protecting the gate oxide of transistor 212.
The first diode further comprises i third diodes 261, 262, … … and 26n, wherein the anode of the ith second triode of the i second triodes is connected with the second end of the (i + 1) th first resistor, and the cathode of the ith second triode is connected with the second end of the ith first resistor. For example, a diode 262 is connected between the resistors 232 and 23n for protecting the transistor 212.
The third embodiment differs from the second embodiment mainly in that N first switches 311, 312, … …, 31N are integrated in the equalization chip 200.
The current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is controlled by turning on and off the ith first switch of the i first switches, and when the ith first switch is turned on, the current flows from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery.
For example, when the 2 nd cell 102 is equalized, the switch 312 is turned on to generate a current, and the transistor 212 is turned on to perform equalization.
In addition, the equalization chip 200 is connected to the BMS chip 300 through pins, and the voltage of each battery, etc., may be measured through the BMS chip 300, for example.
< fourth embodiment >
Fig. 4 shows an equalizing chip according to a fourth embodiment of the present disclosure. The series battery pack 100 includes N batteries 101, 102, … …, 10N connected in series.
The equalizing chip 200 includes: the first end of the ith control switch of the i control switches 211, 212 and … … 21n is connected with the positive terminal of the ith battery through equalizing resistors 401, 402, … … and 40n, and the second end of the ith control switch is connected with the positive terminal of the (i-1) th battery; and i first resistors 231, 232, … …, 23n, a first terminal of an ith first resistor of the i first resistors being connected to a second terminal of the ith control switch, and a second terminal of the ith first resistor being connected to a control terminal of the ith control switch, the ith control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is larger than the current threshold value, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current equalization on the ith battery, wherein 1 < i ≦ N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The contents of the 2 nd cell will be taken as an example and the control switch will be set to be an NMOS transistor.
The drain of the NMOS transistor 212 is connected to the positive terminal of the 2 nd cell through the equalizing resistor 402 by a pin, and the source of the NMOS transistor 212 is connected to the positive terminal of the 1 st cell via a pin. The gate of the NMOS transistor 212 is connected to the second resistor 222, and the first resistor 232 is connected between the source of the NMOS transistor 212 and the second resistor 222. When the battery is unbalanced, a current is formed from the positive terminal of the battery 102 through the resistor 23n and the resistor 232, the voltage formed by the resistor 222 and the resistor 232 forms the gate-source voltage of the NMOS transistor 212, when the gate-source voltage is greater than the threshold turn-on voltage, the NMOS transistor 212 is turned on, and an equalizing current flows from the resistor 402 through the NMOS transistor 212, so that the battery 102 is equalized. When no current flows, the gate-source voltage of the NMOS transistor 212 is zero, and the NMOS transistor 212 is turned off, and then the equalization control is not performed.
In addition, i first diodes 251, 252, … …, 25n are also included, wherein the anode of the ith first diode of the i first diodes is connected to the first end of the ith control switch, and the cathode of the ith first diode is grounded. For example, the diode 252 has an anode connected to the drain of the control switch 212 and a cathode connected to ground for protecting the drain of the control switch 212.
And the control circuit further comprises i second diodes 241, 242 and … … 24n, wherein the anode of the ith second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the ith second diode is connected with the control end of the control switch. For example, diode 242 has an anode connected to the gate of transistor 212 and a cathode connected to the source of transistor 212 for protecting the gate oxide of transistor 212.
As shown in fig. 4, the current control circuit further includes i current control circuits, a first terminal of an ith current control circuit of the i current control circuits is connected to a second terminal of the i +1 th first resistor, and a second terminal of the ith current control circuit is connected to a second terminal of the ith first resistor. The current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the nth battery and the voltage of the positive terminal of the i-1 st battery. And when the ith battery needs to be subjected to balance control, the ith current control circuit works.
The i current control circuits include mirror circuits and current sources 2831, 2832, … …, 283N, respectively, which generate currents based on the voltage of the positive terminal of the nth battery and generate currents flowing into the second terminal of the i first resistor via the mirror currents. The mirror circuit may include NMOS transistors 2811 and 2821, 2812 and 2822, … …, 281n and 282 n. The current sources are all connected to the highest voltage of the Nth battery.
In addition, when i current control circuits are required to operate, the i current control circuits can be realized by the conduction of the switches 2841, 2842, … … and 284 n.
For example, the 2 nd battery 102 will be described as an example. Switch 2842 is turned on and current source 2832 generates a first current based on the highest voltage, which likewise generates the same first current on the source side of transistor 2812, which will turn transistor 212 on, thereby equalizing cell 2 102.
In addition, the equalization chip 200 is connected to the BMS chip 300 through pins, and the voltage of each battery, etc., may be measured through the BMS chip 300, for example.
< fifth embodiment >
Fig. 5 shows an equalization chip according to a fifth embodiment of the present disclosure. The series battery pack 100 includes N batteries 101, 102, … …, 10N connected in series.
The equalizing chip 200 includes: the first end of the ith control switch of the i control switches 211, 212 and … … 21n is connected with the positive terminal of the ith battery through equalizing resistors 401, 402, … … and 40n, and the second end of the ith control switch is connected with the positive terminal of the (i-1) th battery; and i first resistors 231, 232, … …, 23n, a first terminal of an ith first resistor of the i first resistors being connected to a second terminal of the ith control switch, and a second terminal of the ith first resistor being connected to a control terminal of the ith control switch, the ith control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is larger than the current threshold value, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current equalization on the ith battery, wherein 1 < i ≦ N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The contents of the 2 nd cell will be taken as an example and the control switch will be set to be an NMOS transistor.
The drain of the NMOS transistor 212 is connected to the positive terminal of the 2 nd cell through the equalizing resistor 402 by a pin, and the source of the NMOS transistor 212 is connected to the positive terminal of the 1 st cell via a pin. The gate of the NMOS transistor 212 is connected to the second resistor 222, and the first resistor 232 is connected between the source of the NMOS transistor 212 and the second resistor 222. When the battery is unbalanced, a current is formed from the positive terminal of the battery 102 through the resistor 23n and the resistor 232, the voltage formed by the resistor 222 and the resistor 232 forms the gate-source voltage of the NMOS transistor 212, when the gate-source voltage is greater than the threshold turn-on voltage, the NMOS transistor 212 is turned on, and an equalizing current flows from the resistor 402 through the NMOS transistor 212, so that the battery 102 is equalized. When no current flows, the gate-source voltage of the NMOS transistor 212 is zero, and the NMOS transistor 212 is turned off, and then the equalization control is not performed.
In addition, i first diodes 251, 252, … …, 25n are also included, wherein the anode of the ith first diode of the i first diodes is connected to the first end of the ith control switch, and the cathode of the ith first diode is grounded. For example, the diode 252 has an anode connected to the drain of the control switch 212 and a cathode connected to ground for protecting the drain of the control switch 212.
And the control circuit further comprises i second diodes 241, 242 and … … 24n, wherein the anode of the ith second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the ith second diode is connected with the control end of the control switch. For example, diode 242 has an anode connected to the gate of transistor 212 and a cathode connected to the source of transistor 212 for protecting the gate oxide of transistor 212.
As shown in fig. 5, the current control circuit further includes i current control circuits, a first terminal of an ith current control circuit of the i current control circuits is connected to a second terminal of the i +1 th first resistor, and a second terminal of the ith current control circuit is connected to a second terminal of the ith first resistor. The current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the i-th battery and the voltage of the positive terminal of the i-1 th battery. And when the ith battery needs to be subjected to balance control, the ith current control circuit works.
The i current control circuits include mirror circuits and current sources 2831, 2832, … …, 283n, respectively, which generate currents based on the voltage of the positive terminal of the i-th cell and the voltage of the positive terminal of the i-1 th cell, and generate a current flowing into the second terminal of the i-th first resistor via the mirror currents. The mirror circuit may include NMOS transistors 2811 and 2821, 2812 and 2822, … …, 281n and 282 n.
In addition, when i current control circuits are required to operate, the i current control circuits can be realized by the conduction of the switches 2841, 2842, … … and 284 n.
For example, the 2 nd battery 102 will be described as an example. Switch 2842 is turned on and current source 2832 generates a first current based on the voltage at the positive terminal of battery 2, which similarly generates a similar first current at the source side of transistor 2812, which turns on transistor 212, thereby equalizing battery 2.
This embodiment differs from the embodiment shown in fig. 4 in that each current source used in the ith cell is based on the positive terminal voltage of the ith cell itself, thus avoiding the effect of the battery imbalance factor caused by using the highest voltage. Since the highest voltage is the total voltage of each cell, it is bound to contain the imbalance information of the cells.
In addition, the equalization chip 200 is connected to the BMS chip 300 through pins, and the voltage of each battery, etc., may be measured through the BMS chip 300, for example.
In the present disclosure, equalization control is implemented by using the voltages of the positive terminals of two adjacent batteries, so that a better equalization effect can be obtained, and interference from the currents of other batteries can be avoided. In the present disclosure, by integrating the equalizer circuit into a semiconductor chip, miniaturization and integration can be achieved.
In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.
Claims (10)
1. An equalizing chip for a series battery comprising N cells connected in series, where N > 1, the equalizing chip comprising:
the first end of the ith control switch of the i control switches is connected with the positive electrode end of the ith battery through a balancing resistor, and the second end of the ith control switch is connected with the positive electrode end of the (i-1) th battery; and
i first resistors, a first terminal of an ith first resistor of the i first resistors being connected to a second terminal of the ith control switch, and a second terminal of the ith first resistor being connected to a control terminal of the ith control switch,
the ith control switch is controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is larger than a current threshold value, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to balance the current of the ith battery, wherein 1 < i ≦ N.
2. The equalization chip of claim 1,
the i control switches are NMOS transistors, first ends of the i control switches are drain electrodes, second ends of the i control switches are source electrodes, and control ends of the i control switches are grid electrodes; or
The control circuit comprises i control switches, a base electrode and a base electrode, wherein the i control switches are triodes, the first ends of the i control switches are collecting electrodes, the second ends of the i control switches are emitting electrodes, and the control ends of the i control switches are base electrodes.
3. The equalizing chip of claim 2, further comprising i second resistors, wherein a first terminal of an ith second resistor of said i second resistors is connected to a control terminal of said ith control switch, and a second terminal of said ith second resistor is connected to a second terminal of said ith first resistor.
4. The equalizing chip of claim 2, further comprising i first diodes, wherein an anode of an ith first diode of said i first diodes is connected to the first terminal of said ith control switch, and wherein a cathode of said ith first diode is grounded.
5. The equalizing chip of claim 2, further comprising i second diodes, wherein an anode of an ith second diode of the i second diodes is connected to the second terminal of the control switch, and a cathode of the ith second diode is connected to the control terminal of the control switch;
or;
the diode also comprises i third diodes, wherein the anode of the ith second triode of the i second triodes is connected with the second end of the (i + 1) th first resistor, and the cathode of the ith second triode is connected with the second end of the ith first resistor;
or;
and when the ith first switch is switched on, the current flows from the positive electrode terminal of the ith battery to the positive electrode terminal of the (i-1) th battery.
6. The equalization chip of claim 5, wherein the i first switches are integrated in the equalization chip.
7. The equalizing chip of any one of claims 1 to 6, further comprising i current control circuits, wherein a first terminal of an ith current control circuit of the i current control circuits is connected to a second terminal of the (i + 1) th first resistor, and a second terminal of the ith current control circuit is connected to a second terminal of the ith first resistor.
8. The equalizing chip according to claim 7, wherein the current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the nth cell and the voltage of the positive terminal of the i-1 st cell;
or;
when the balance control is needed to be carried out on the ith battery, the ith current control circuit works;
or;
the i current control circuits each include a mirror circuit and a current source that generates a current based on a voltage of the positive terminal of the nth battery and generates a current flowing into the second terminal of the i first resistor via the mirror current.
9. The equalizing chip of claim 7, wherein the current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the i-th cell and the voltage of the positive terminal of the i-1 th cell;
or;
when the balance control is needed to be carried out on the ith battery, the ith current control circuit works;
or;
the i current control circuits each include a mirror circuit and a current source that generates a current based on a voltage of the positive terminal of the i-th battery and generates a current flowing into the second terminal of the i-th first resistor via the mirror current.
10. A battery management system, comprising:
the equalization chip of any of claims 1 to 9; and
a battery management chip that measures a voltage of an ith battery via at least the equalization circuit.
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