CN112750706A - 集成电路器件和形成集成电路封装件的方法 - Google Patents

集成电路器件和形成集成电路封装件的方法 Download PDF

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CN112750706A
CN112750706A CN202011196697.6A CN202011196697A CN112750706A CN 112750706 A CN112750706 A CN 112750706A CN 202011196697 A CN202011196697 A CN 202011196697A CN 112750706 A CN112750706 A CN 112750706A
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layer
die
conductive material
hardness
integrated circuit
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CN112750706B (zh
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郭宏瑞
汪嘉伟
蔡惠榕
张育慈
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在实施例中，集成电路器件包括：半导体衬底；接触焊盘，位于半导体衬底上；钝化层，位于接触焊盘和半导体衬底上；管芯连接件，延伸穿过钝化层，管芯连接件物理耦接和电耦接至接触焊盘，管芯连接件包括第一导电材料，第一导电材料是具有第一酸硬度/软度指数的路易斯酸；介电层，位于管芯连接件和钝化层上；以及保护层，设置在介电层和管芯连接件之间，保护层围绕管芯连接件，保护层包括第一导电材料和唑的配位络合物，唑是具有第一配体硬度/软度指数的路易斯碱，其中，第一酸硬度/软度指数和第一配体硬度/软度指数的乘积为正。本发明的实施例还涉及形成集成电路封装件的方法。

Description

集成电路器件和形成集成电路封装件的方法
技术领域
本发明的实施例涉及集成电路器件和形成集成电路封装件的方法。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断改进，半导体工业经历了快速增长。在大多数情况下，集成密度的改进来自最小部件尺寸的迭代减小，这允许将更多组件集成到给定区域中。随着对缩小电子设备需求的增长，已经出现了对更小且更具创造性的半导体管芯封装技术的需求。这种封装***的一个实例是叠层封装(Package-on-Package，PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上，以提供高水平的集成度和组件密度。PoP技术通常使半导体器件的生产能够具有增强的功能和在印刷电路板(PCB)上小的占用面积。
发明内容
本发明的一些实施例提供了一种形成集成电路封装件的方法，包括：接收集成电路管芯，所述集成电路管芯包括：接触焊盘，位于半导体衬底上；钝化层，位于所述接触焊盘和所述半导体衬底上；管芯连接件，延伸穿过所述钝化层，所述管芯连接件物理耦接和电耦接至所述接触焊盘，所述管芯连接件包括第一导电材料，所述第一导电材料是具有第一酸硬度/软度指数的路易斯酸；和可回流焊连接件，位于所述管芯连接件上，所述可回流焊连接件包括第二导电材料，所述第二导电材料是具有第二酸硬度/软度指数的路易斯酸；以及用蚀刻溶液蚀刻所述可回流焊连接件和所述管芯连接件，所述蚀刻溶液包括用于所述第一导电材料的保护剂和用于所述第二导电材料的蚀刻剂，所述保护剂是唑，所述唑是具有第一配体硬度/软度指数的路易斯碱，其中，所述第一酸硬度/软度指数与所述第一配体硬度/软度指数的乘积为正，并且所述第二酸硬度/软度指数与所述第一配体硬度/软度指数的乘积为负。
本发明的另一些实施例提供了一种形成集成电路封装件的方法，包括：在半导体衬底上形成接触焊盘；在所述接触焊盘和所述半导体衬底上沉积钝化层；在所述钝化层中图案化暴露所述接触焊盘的开口；在所述开口中和所述接触焊盘上镀管芯连接件，所述管芯连接件包括第一导电材料；回流位于所述管芯连接件上的可回流焊连接件；以及用蚀刻溶液蚀刻所述可回流焊连接件和所述管芯连接件以去除所述可回流焊连接件，所述蚀刻溶液包括蚀刻剂和保护剂，所述保护剂是包括用于接合至第一导电材料的多个活性位点的五元杂环化合物。
本发明的又一些实施例提供了一种集成电路器件，包括：半导体衬底；接触焊盘，位于所述半导体衬底上；钝化层，位于所述接触焊盘和所述半导体衬底上；管芯连接件，延伸穿过所述钝化层，所述管芯连接件物理耦接和电耦接至所述接触焊盘，所述管芯连接件包括第一导电材料，所述第一导电材料是具有第一酸硬度/软度指数的路易斯酸；介电层，位于所述管芯连接件和所述钝化层上；以及保护层，设置在所述介电层和所述管芯连接件之间，所述保护层围绕所述管芯连接件，所述保护层包括所述第一导电材料和唑的配位络合物，所述唑是具有第一配体硬度/软度指数的路易斯碱，其中，所述第一酸硬度/软度指数和所述第一配体硬度/软度指数的乘积为正。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图5是根据一些实施例的在形成集成电路管芯的工艺期间的中间步骤的截面图。
图6A和图6B是根据各个实施例的集成电路管芯的截面图。
图7至图14示出了根据一些实施例的在形成封装组件的工艺期间的中间步骤的截面图。
图15和图16示出了根据一些实施例的器件堆叠件的形成和实施。
图17示出了根据一些其他实施例的封装组件的截面图。
图18示出了根据一些其他实施例的封装组件的截面图。
图19示出了根据一些其他实施例的封装组件的截面图。
图20示出了根据一些其他实施例的封装组件的截面图。
图21示出了根据一些其他实施例的封装组件的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。如本文使用的，在第二部件上形成第一部件是指形成与第二部件直接接触的第一部件。此外，本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个组件或部件与另一组件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据一些实施例，芯片探针附接至管芯连接件并且用于测试已知良好管芯(KGD)。芯片探针用可回流焊连接件附接。在去除芯片探针之后，通过湿蚀刻工艺去除可回流焊连接件。湿蚀刻工艺包括用具有保护剂的蚀刻溶液蚀刻可回流焊连接件。保护剂是与管芯连接件的材料形成强共价键结合的软路易斯(Lewis)碱，诸如唑化合物。从而可以在湿蚀刻工艺期间保护管芯连接件。
图1至图5是根据一些实施例的在形成集成电路管芯50的工艺期间的中间步骤的截面图。将在后续工艺中封装集成电路管芯50以形成集成电路封装件。每个集成电路管芯50可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、片上***(SoC)、应用处理器(AP)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器芯片、微机电***(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或者它们的组合。
在图1中，提供半导体衬底52。半导体衬底52可以是掺杂或未掺杂的硅，或者是绝缘体上半导体(SOI)衬底的有源层。半导体衬底52可以包括其他半导体材料，诸如：锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或其组合。也可以使用其他衬底，诸如多层衬底或梯度衬底。半导体衬底52具有有时被称为前侧的有源表面(例如，在图1中面向上的表面)；以及有时被称为后侧的无源表面(例如，在图1中面向下的表面)。器件形成在半导体衬底的有源表面处。器件可以是有源设备(例如，晶体管、二极管等)或无源设备(例如，电容器、电阻器、电感器等)。
半导体衬底52具有多个器件区域，并且集成电路管芯50形成在每个器件区域中和/或每个器件区域上。示出了第一器件区域52A和第二器件区域52B，但是应当理解，半导体衬底52可以具有任何数量的器件区域。
互连结构54形成在半导体衬底52上方。互连结构54互连半导体衬底52的器件，以在每个器件区域52A和52B中形成集成电路。例如，互连结构54可以由介电层中的金属化图案形成。金属化图案包括形成在一个或多个低k介电层中的金属线和通孔。互连结构54可以通过镶嵌工艺形成，诸如单镶嵌工艺、双镶嵌工艺等。互连结构54的金属化图案电耦接至半导体衬底52的器件。
在图2中，接触焊盘56形成在集成电路管芯50的前侧上，诸如形成在互连结构54中和/或在互连结构54上。接触焊盘56可以是与之建立外部连接的铝焊盘、铜焊盘等。在一些实施例中，接触焊盘56是互连结构54的最顶部金属化图案的部分。
在接触焊盘56和互连结构54上形成一个或多个钝化层58。钝化层58可以由合适的介电材料中的一种或多种制成，诸如氧化硅、氮化硅、低-k介电(诸如碳掺杂氧化物)、极低k介电(诸如多孔碳掺杂二氧化硅)、聚合物(例如聚酰亚胺、阻焊剂、聚苯并恶唑(PBO)、苯并环丁烯(BCB))、模塑料等或其组合。可以通过旋涂、层压、CVD等或其组合形成钝化层58。
诸如导电柱(例如，由诸如铜的金属形成)的管芯连接件60形成为延伸穿过钝化层58，以物理耦接并且电耦接至接触焊盘56。因此，管芯连接件60电耦接至集成电路管芯50的相应集成电路。管芯连接件60可以称为导电通孔。图3A至图3F是根据一些实施例的在形成管芯连接件60的工艺期间的中间步骤的截面图。特别地，更详细地示出了图2中的区域3。尽管示出了单个管芯连接件60的形成，但是应当理解，同时形成多个管芯连接件60。
在图3A中，图案化钝化层58以形成暴露接触焊盘56的部分的开口62。图案化可以通过可接受的工艺来进行，诸如当钝化层58是光敏材料时通过将钝化层58暴露于光，或者通过使用例如各向异性蚀刻的蚀刻来进行。如果钝化层58是光敏材料，则钝化层58可以在曝光之后进行显影。
在图案化钝化层58之后，晶种层64形成在钝化层58上方以及形成在暴露接触焊盘56的开口62中。在一些实施例中，晶种层64是金属层，晶种层可以是单层或者是包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层64包括钛层64A和在钛层64A上方的铜层64B。晶种层64可以使用例如PVD等来形成。晶种层64可以形成为厚度T1在约0.01μm至约2.0μm的范围内。
在图3B中，在晶种层64上形成并且图案化光刻胶66。光刻胶66可以通过旋涂等来形成，并且可以暴露于光以进行图案化。光刻胶66的图案对应于管芯连接件60。图案化形成穿过光刻胶66的开口以暴露晶种层64。
然后，在光刻胶66的开口中和在晶种层64的暴露部分上形成第一导电材料层68A。可以通过诸如电镀或化学镀等的镀来形成第一导电材料层68A。第一导电材料层68A可以包括金属，例如铜、钛、钨、铝等。在一些实施例中，第一导电材料层68A是铜。第一导电材料层68A可以形成为厚度T2在约1μm至约50μm的范围内，诸如约15μm。
第二导电材料层68B可以可选地形成在第一导电材料层68A上。第二导电材料层68B可以以类似于第一导电材料层68A的方式形成，并且可以由与第一导电材料层68A不同的材料形成。在一些实施例中，第二导电材料层68B是镍。第二导电材料层68B可以形成为厚度T3在约0.1μm至约20μm的范围内，诸如约3μm。形成镍层可以帮助保护第一导电材料层68A的铜在进一步的工艺期间免受氧化。
第三导电材料层68C可以可选地形成在第二导电材料层68B上。第三导电材料层68C可以以类似于第一导电材料层68A的方式形成，并且可以由与第一导电材料层68A类似的材料形成。在一些实施例中，第三导电材料层68C是铜。第三导电材料层68C可以形成为厚度T4在约0.1μm至约20μm的范围内，诸如约2μm。当随后在管芯连接件60上形成可回流焊连接件时，形成铜层可以帮助防止金属间化合物(IMC)形成在第二导电材料层68B中和/或第二导电材料层68B上。
开口位于光刻胶66中，并且因此导电材料层68A、68B和68C可以形成为宽度W1在约1μm至约150μm范围内。导电材料层68A、68B和68C的组合以及下面的晶种层64的部分形成管芯连接件60。
在图3C中，去除了光刻胶66和晶种层64的其上未形成导电材料层68A、68B和68C的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺来去除光刻胶66。一旦去除光刻胶66，就去除了晶种层64的暴露部分，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)。
在图3D中，可回流焊连接件70形成在管芯连接件60上。可回流焊连接件70可以包括导电材料，诸如焊料、金、银、锡等或其组合。在一些实施例中，通过蒸发、电镀、印刷、焊料转移、焊球放置等首先形成焊料层来形成可回流焊连接件70。可回流焊连接件70可以在去除光刻胶66之后形成，或者可以在去除光刻胶66之前形成在光刻胶66的开口中。一旦焊料层已经形成在管芯连接件60上，就可以可选地执行回流焊以将材料成形为期望的凸块形状。可回流焊连接件70是厚的。例如，可回流焊连接件70可以形成为厚度T5在约1μm至约50μm的范围内的，诸如约15μm。
在图3E中，通过使用芯片探针72来测试集成电路管芯50。通过使可回流焊连接件70回流将芯片探针72物理耦接和电耦接至管芯连接件60，这可以使可回流焊连接件70成形为凸块形状。可以在集成电路管芯50上执行芯片探针测试，以确定集成电路管芯50是否是已知良好管芯(KGD)。因此，仅是KGD的集成电路管芯50经历后续的工艺和封装，而未通过CP测试的集成电路管芯50不被封装。基于集成电路器件的设计，测试可以包括对各种集成电路管芯50的功能的测试，或者可以包括期望的对已知开路或已知短路的测试。
在图3F中，芯片探针72与管芯连接件60分离并且被去除。可以通过回流可回流焊连接件70来实现分离。在分离芯片探针72之后，执行蚀刻工艺74以去除可回流焊连接件70的剩余部分。蚀刻工艺74对于可回流焊连接件70的材料是选择性的，使得可回流焊连接件70的材料比管芯连接件60的材料被蚀刻得更快。
尽管蚀刻工艺74对于期望的材料(例如，可回流焊连接件70的材料)是选择性的，但是对一些不期望的材料(例如，管芯连接件60的材料)的蚀刻仍然发生。此外，不期望的材料的蚀刻可能以不同的速率发生。例如，蚀刻工艺74可以以比铜更高的速率蚀刻焊料，并且可以以比钛和镍更高的速率蚀刻铜。这样，通过蚀刻工艺74，可以减小导电材料层68A和68C和铜层64B的尺寸可察觉的量，而不减小导电材料层68B(例如，镍)和钛层64A的尺寸。在去除可回流焊连接件70之后，导电材料层68B和钛层64A可以基本保持原始宽度W1，但是导电材料层68A和68C以及铜层64B可以减小到较小的宽度W2，诸如在约0.7μm至约149μm的范围内的宽度W2。减小量R1可以在约0.0005μm至约45μm的范围内，诸如约0.1μm，减小量R1可以占原始宽度W1的约0.05％至约30％。此外，导电材料层68C的厚度可以减小到较小的厚度T6，诸如在约0.07μm至约19.99μm的范围内的厚度T6。减小量R2可以在约0.001μm至约6μm的范围内，诸如约0.1μm，减小量R2可以占原始厚度T4的约0.05％至约30％。
在一些实施例中，蚀刻工艺74是使用基于水的蚀刻溶液执行的湿蚀刻，基于水的蚀刻溶液包括用于可回流焊连接件70的材料的蚀刻剂和用于管芯连接件60的材料的保护剂。蚀刻剂与可回流焊连接件70的材料反应以将其从固相转变为液相。在一些实施例中，蚀刻剂是氧化的金属离子。例如，可以使用氧化铁(III)、氧化铜(II)等来去除可回流焊连接件70的材料。保护剂(下面进一步讨论)与管芯连接件60的材料反应以形成保护层76，保护层76减小管芯连接件60的蚀刻速率。蚀刻剂和保护剂溶解在溶剂中，溶剂可以是能够溶解蚀刻剂和保护剂的任何溶剂。示例性溶剂包括硝酸、硫酸等。蚀刻溶液中保护剂的浓度可以很小。例如，蚀刻溶液可以包括1ppm至20000ppm的保护剂，1ppm至20000ppm可以表示约0.0001％至约2％范围内的浓度。反之，蚀刻溶液可以包括浓度在约0.1％至约20％范围内的蚀刻剂，并且可以包括约0.5％至约50％范围内的溶剂。
在蚀刻工艺74期间，可以通过使用多种技术将蚀刻溶液分配在中间结构(包括管芯连接件60和可回流焊连接件70)上。在一些实施例中，将中间结构浸入蚀刻溶液的浴中。在一些实施例中，将蚀刻溶液喷涂在中间结构上。将蚀刻溶液喷涂在中间结构上可以包括旋转中间结构同时使蚀刻溶液流过中间结构上方。中间结构可以低速旋转，诸如在约100RPM至约3000RPM范围内的速度。同样，蚀刻溶液可以以高速率流动，诸如以约0.2L/min至约2L/min范围内的流速流动。无论怎样分配蚀刻溶液，蚀刻工艺74可以在低温下执行，诸如在约5℃至约50℃范围内的温度。此外，可以以任何期望的持续时间执行蚀刻工艺74，诸如约0.1分钟至约120分钟范围内的持续时间。
如上所述，蚀刻溶液中的保护剂与管芯连接件60的材料反应以形成保护层76，保护层76降低管芯连接件60的蚀刻速率。特别地，保护剂是与导电材料层68A和68C和铜层64B的材料(例如，铜)反应的有机配体，以在层的暴露表面处形成配位络合物的保护层76。配位络合物化学阻碍了蚀刻剂与裸露的铜的反应。有利地，保护层76的形成允许在蚀刻工艺74期间的减小量R1和R2很小。在一些实施例中，保护层76是在导电材料层68A和68C和铜层64B的表面处的单层。在一些实施例中，保护层76至少部分地延伸到导电材料层68A和68C以及铜层64B中，使得这些层具有包括配位络合物的外部区域和不具有配位络合物的内部区域。保护层76较薄，保护层76可以具有约
Figure BDA0002754215600000091
至约
Figure BDA0002754215600000092
范围内的厚度T7。保护层76可以在蚀刻工艺74之后被保留并且可以是所得集成电路管芯50的部分。
管芯连接件60和可回流焊连接件70的金属是路易斯(Lewis)酸，并且保护剂的配体是路易斯碱。根据Pearson的硬软酸碱(Hard Soft Acid Base，HSAB)定理，“硬”路易斯酸(例如，具有高电荷密度和小半径的那些)与“硬”路易斯碱形成强离子键，并且“软”路易斯酸(例如，具有低电荷密度和大半径的那些)与“软”路易斯碱形成强共价键。尽管路易斯酸和路易斯碱通常定性地归类为“硬”或“软”，但人们已经做出努力来量化路易斯酸和碱的精确硬度/软度。例如，Xu等的“金属阳离子和配体的化学硬度/软度的自然指数(NaturalIndices for the Chemical Hardness/Softness ofMetal Cations and Ligands)”，ACSOmega 20172(10),pp.7185-7193(其全部内容结合于此作为参考)建议形成阳离子的自由能(ΔG°f,M n+)是路易斯酸硬度/软度的自然指数。根据该定义，具有正ΔG°f,M n+值的酸是“软”路易斯酸，并且具有负ΔG°f,M n+值的酸是“硬”路易斯酸。Xu等还建议，系数α*ML可以从各种路易斯碱的实验数据中得出，并且每个系数α*ML是相应路易斯碱的硬度/软度的指数。正α*ML值指示“软”路易斯碱，并且负α*ML值指示“硬”路易斯碱。基于这些指数，可以通过计算路易斯酸和碱的硬度/软度指数的乘积来凭经验确定化合物中给定的路易斯酸和碱之间的键强度。当乘积为正值(例如，大于零)时，那么在路易斯酸和碱之间将形成强键(离子或共价)。当乘积为负值(例如，小于零)时，那么在路易斯酸和碱之间将形成弱键。
以下将“Xu等的“金属阳离子和配体的化学硬度/软度的自然指数(NaturalIndices for the Chemical Hardness/Softness of Metal Cations and Ligands)”的详细介绍如下：
对于给定的络合配体(路易斯碱)和一组等价的金属阳离子(路易斯酸)，金属-配体(ML)络合物的稳定性常数可以简单地与金属离子的已知特性[离子半径(r M n+)、吉布斯形成自由能(ΔG°f，M n+)和溶剂化能(ΔG°s，M n+)]通过2.303RT log K ML＝(α*MLΔG°f，M n+-β*ML r M n++γ*MLΔG°s，M n+-δ*ML)相关，其中，系数(α*ML、β*ML、γ*ML和截距δ*ML)通过将方程与现有实验数据拟合确定。系数β*ML和γ*ML具有相同的符号，并且在原点之间呈线性关系。阳离子形成的吉布斯自由能(ΔG°f,M n+)是金属阳离子的软度或硬度的自然指标，其中，正值对应于软酸，并且负值对应于硬酸。系数α*ML是络合配体的柔软性或硬度的指标。软度指数为零的质子(H+)是一种独特的酸，其与软碱和硬碱都具有很强的相互作用。由酸-碱相互作用产生的稳定能由项α*MLΔG°f,M n+确定；α*ML和ΔG°f,M n+的正积表示金属阳离子和络合配体之间的酸碱相互作用使络合物稳定。与金属阳离子的离子半径有关的项β*ML r M n+和γ*MLΔG°s,M n+表示阳离子的空间效应和溶剂化效应。铜是一种“软”路易斯酸(例如，具有正的ΔG°f,M n+值)。相反，锡和镍是“硬”路易斯酸(例如，具有负ΔG°f,M n+值)。根据一些实施例，蚀刻溶液中的保护剂是“软”路易斯碱(例如，具有正α*ML值)。根据Pearson的HSAB定理，保护剂将因此与铜形成强共价键，而不会与锡或镍形成强键。换句话说，保护剂将与导电材料层68A和68C和铜层64B的材料(例如，铜)反应，而基本上不与导电材料层68B、钛层64A和可回流焊连接件70的材料(例如，锡、镍)反应。
防护剂可以是任何的“软”路易斯碱，但是唑衍生物的路易斯碱可以特别理想的，因为它们具有较大的正α*ML值(例如，至少0.0794)、无毒以及与其他路易斯碱相比具有低成本。唑是含有多个氮原子的五元杂环化合物，这允许唑化合物具有与铜结合的多于一个的活性位点。可以使用若干类型的唑。例如，唑可以是吡唑化合物(例如，甲基吡唑)、咪唑化合物(例如，甲基咪唑)、***化合物(例如，苯并***)、四唑化合物(例如，苯基四唑或苯基-巯基四唑)或戊唑化合物(例如，戊唑(例如，HN5))。应当理解，实际上其他类型的唑以及其他的“软”路易斯碱也可以用作保护剂。
尽管被描述为单个工艺，但是应当理解，图3A至图3F所示的步骤可以被分成多个工艺。例如，可以执行包括图3A至图3D所示的步骤的第一工艺以获得中间结构。在从第一工艺获得或接收中间结构之后，可以执行包括图3E至图3F所示的步骤的第二工艺。
在图4中，介电层78形成在集成电路管芯50的前侧上，诸如形成在钝化层58和管芯连接件60上。介电层78横向地密封管芯连接件60。介电层78可以是：聚合物，诸如PBO、聚酰亚胺、BCB、或诸如此类；氮化物，诸如氮化硅、或诸如此类；氧化物，诸如氧化硅、PSG、BSG、BPSG、或诸如此类；诸如此类或其组合。可以例如通过旋涂、层压、化学气相沉积(CVD)等来形成介电层78。最初，介电层78可以掩埋管芯连接件60，以使得介电层78的最顶面在管芯连接件60的最顶面上方。在一些实施例中，在形成集成电路管芯50期间，通过介电层78暴露管芯连接件60。在一些实施例中，管芯连接件60保持被掩埋并且在随后的用于封装集成电路管芯50的工艺期间被暴露。
当介电层78是诸如PBO的聚合物时，在形成介电层78之前从管芯连接件60去除可回流焊连接件70可以在介电层78的固化工艺期间防止焊料润湿。此外，通过蚀刻工艺74而不是其他工艺(诸如CMP)来去除可回流焊连接件70，可以有助于减少介电层78中焊料残留物的量。最后，通过蚀刻工艺74去除可回流焊连接件70较少的损坏管芯连接件60，这可以有助于提高管芯连接件60的可靠性和电性能。
在图5中，通过沿着例如在器件区域52A和52B之间的划线区域进行锯切来执行分割工艺80。分割工艺80将器件区域52A和52B分割。因此，分割的集成电路管芯50来自器件区域52A和52B。图6A和图6B是根据各个实施例的所得的集成电路管芯50的截面图。
图6A示出了第一类型的集成电路管芯50A。第一集成电路管芯50A具有单个的半导体衬底52并且类似于关于图1至图5讨论的实施例。第一集成电路管芯50A可以是逻辑器件，诸如中央处理单元(CPU)、图形处理单元(GPU)、片上***(SoC)、微控制器等。
图6B示出了第二类型的集成电路管芯50B。第二集成电路管芯50B可以是存储器器件，诸如动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯、混合存储立方体(HMC)模块、高带宽存储器(HBM)模块等。第二集成电路管芯50B是包括多个半导体衬底52的堆叠器件。例如，第二集成电路管芯50B可以是存储器器件，诸如混合存储立方体(HMC)模块、高带宽存储器(HBM)模块、或包含多个存储器管芯的诸如此类。半导体衬底52可以通过衬底通孔(TSV)82互连，TSV82部分地延伸到半导体衬底52中或完全地延伸穿过半导体衬底52。堆叠的半导体衬底52可以共享互连结构54，或者每个半导体衬底52可以具有其自己的互连结构54。此外，可以在堆叠的半导体衬底52周围形成密封剂84。密封剂84可以是模塑料、环氧树脂等。
图7至图14示出了根据一些实施例的形成第一封装组件100工艺期间的中间步骤的截面图。第一封装组件100具有多个封装区域，并且一个或多个集成电路管芯50被封装以在每个封装区域中形成集成电路封装件。示出了第一封装区域100A和第二封装区域100B，但是应当理解，第一封装组件100可以具有任何数量的封装区域。在形成之后，分割每个封装区域中的集成电路封装件。所得的集成电路封装件也可以称为集成扇出(InFO)封装件。
在图7中，提供了载体衬底102，并且释放层104形成在载体衬底102上。载体衬底102可以是玻璃载体衬底、陶瓷载体衬底、或诸如此类。载体衬底102可以是晶圆，从而使得可以在载体衬底102上同时形成多个封装件。释放层104可以由基于聚合物的材料形成，释放层104可以与载体衬底102一起从将在后续步骤中形成的上面结构中去除。在一些实施例中，释放层104是基于环氧树脂的热释放材料，热释放材料在加热时会失去其粘合性，诸如光至热转换(LTHC)释放涂层。在其他实施例中，释放层104可以是紫外线(UV)胶，UV胶当被暴露于UV光时会失去其粘合特性。释放层104可以以液体的形式被分配和固化、可以是层压在载体衬底102上的层压膜等。释放层104的顶面可以是水平的并且可以具有高度的平面度。
在图8中，背侧再分布结构106可以形成在释放层104上。在所示的实施例中，背侧再分布结构106包括介电层108、金属化图案110(有时称为再分布层或再分布线)和介电层112。背侧再分布结构106是可选的。在一些实施例中，在释放层104上形成不具有金属化图案的介电层来代替背侧再分布结构106。
介电层108可以形成在释放层104上。介电层108的底面可以与释放层104的顶面接触。在一些实施例中，介电层108由聚合物形成，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。在其他实施例中，介电层108由：氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；等。介电层108可以通过任何可接受的沉积工艺形成，诸如旋涂、CVD、层压等或其组合。
金属化图案110可以形成在介电层108上。作为形成金属化图案110的示例，在介电层108上形成晶种层。在一些实施例中，晶种层是金属层，晶种层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。晶种层可以使用例如物理气相沉积(PVD)等来形成。然后在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等来形成，并且可以被曝光以进行图案化。光刻胶的图案对应于金属化图案110。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，例如铜、钛、钨、铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺来去除光刻胶。一旦去除光刻胶，则去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)。晶种层的剩余部分和导电材料形成金属化图案110。
介电层112可以形成在金属化图案110和介电层108上。在一些实施例中，介电层112由可以使用光刻掩模将其图案化的聚合物形成，聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中，介电层112由：氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。介电层112可以通过旋涂、层压、CVD等或其组合来形成。
应当理解，背侧再分布结构106可以包括任何数量的介电层和金属化图案。如果要形成更多的介电层和金属化图案，则可以重复上述步骤和工艺。金属化图案可以包括导线和导电通孔。导电通孔可以在金属化图案的形成期间，通过在下面的介电层的开口中形成金属化图案的晶种层和导电材料来形成。因此，导电通孔可以互连并电耦接各个导线。
接下来，形成通孔116，通孔116穿过并且远离背侧再分布结构106的最顶部介电层(例如，介电层112)延伸。通孔116是可选的，并且如下面进一步讨论的，可以省略。例如，在省略了背侧再分布结构106的实施例中，可以(或者可以不)省略通孔116。作为形成通孔116的示例，可以图案化介电层112以形成暴露金属化图案110的部分的开口。图案化可以通过可接受的工艺来形成，诸如通过当介电层112是光敏材料时将介电层112暴露于光，或者通过使用例如各向异性蚀刻的蚀刻。如果介电层112是光敏材料，则介电层112可以在曝光之后被显影。然后，在介电层112和由开口暴露的金属化图案110的部分上方形成晶种层。在一些实施例中，晶种层是金属层，晶种层可以是单层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层和位于钛层上方的铜层。晶种层可以使用例如PVD等来形成。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等来形成，并且可以被曝光以进行图案化。光刻胶的图案对应于导电通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，例如铜、钛、钨、铝等。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺来去除光刻胶。一旦去除光刻胶，则去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)。晶种层的剩余部分和导电材料形成通孔116。
在图9中，通过粘合剂128将集成电路管芯50粘附到介电层112。在每个封装区域100A和100B中粘附期望类型和数量的集成电路管芯50。在所示的实施例中，诸如第一集成电路管芯50A和第二集成电路管芯50B的多个集成电路管芯50彼此相邻地粘附在每个封装区域中。粘合剂128位于集成电路管芯50A和50B的背侧上，并且将集成电路管芯50A和50B粘附到背侧再分布结构106，诸如粘附到介电层112上。粘合剂128可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。可以将粘合剂128施加到集成电路管芯50A和50B的背侧、或者可以施加到载体衬底102的表面上方。例如，在执行分割工艺80(见图5)之前，可以将粘合剂128施加到集成电路管芯50A和50B的背侧。
在图10中，密封剂130形成在多个组件上和多个组件周围。在形成之后，密封剂130密封通孔116和集成电路管芯50。密封剂130可以是模塑料、环氧树脂等。密封剂130可以通过压缩模制、转移模制等来施加并且可以形成在载体衬底102上方，从而使得通孔116和/或集成电路管芯50被掩埋或覆盖。密封剂130还形成在集成电路管芯50之间的间隙区域中(如果存在)。密封剂130可以以液体或半液体形式来施加并且然后随后被固化。
可以对密封剂130执行平坦化工艺以暴露通孔116和管芯连接件60。平坦化工艺可以去除通孔116、介电层78和/或管芯连接件60的材料，直到暴露管芯连接件60和通孔116。在平坦化工艺之后，通孔116、管芯连接件60、介电层78和密封剂130的顶面共面。平坦化工艺可以例如是化学机械抛光(CMP)、研磨工艺等。在平坦化工艺期间，抛光连接件60的顶面，这可以去除第二导电材料层68B和/或第三导电材料层68C(见图3F)。在执行平坦化工艺之前用蚀刻工艺74去除可回流焊连接件70，可以帮助减少介电层78中的焊料残留物的量。
在图11中，前侧再分布结构140形成在密封剂130、通孔116和集成电路管芯50上方。前侧再分布结构140包括介电层142、146、150和154；以及金属化图案144、148和152。金属化图案也可以被称为再分布层或再分布线。所示的前侧再分布结构140作为具有三层金属化图案的示例。更多或更少的介电层和金属化图案可以形成在前侧再分布结构140中。如果要形成更少的介电层和金属化图案，则可以省略下面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复下面讨论的步骤和工艺。
作为形成前侧再分布结构140的示例，介电层142可以沉积在密封剂130、通孔116和管芯连接件60上。在一些实施例中，由可以使用光刻掩模将其图案化的聚合物来形成，聚合物可以是诸如PBO、聚酰亚胺、BCB、等的光敏材料。介电层142可以通过旋涂、层压、CVD等或其组合来形成。然后，图案化介电层142。图案形成暴露通孔116和管芯连接件60的部分的开口。图案化可以通过可接受的工艺来形成，诸如通过当介电层142是光敏材料时将介电层142暴露于光，或者通过使用例如各向异性蚀刻的蚀刻。如果介电层142是光敏材料，则介电层142可以在曝光之后被显影。
然后形成金属化图案144。金属化图案144包括在介电层142的主表面上并且沿着介电层142的主表面延伸的线部分(也称为导线)。金属化图案144还包括延伸穿过介电层142以物理耦接和电耦接通孔116和集成电路管芯50的通孔部分(也称为导电通孔)。作为形成金属化图案144的示例，在介电层142上方和延伸穿过介电层142的开口中形成晶种层。晶种层是金属层，晶种层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。晶种层可以使用例如PVD等来形成。然后在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等来形成，并且可以被曝光以进行图案化。光刻胶的图案对应于金属化图案144。图案形成穿过光刻胶的开口以暴露晶种层。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，例如铜，钛，钨，铝等。导电材料和下面的晶种层的部分的组合形成金属化图案144。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺来去除光刻胶。一旦去除光刻胶，则去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)。
然后，介电层146可以沉积在金属化图案144和介电层142上。介电层146可以以类似于介电层142的方式形成，并且可以由与介电层142类似的材料形成。
然后形成金属化图案148。金属化图案148包括在介电层146的主表面上并沿着介电层146的主表面延伸的线部分。金属化图案148还包括延伸穿过介电层146以物理耦接和电耦接金属化图案144的通孔部分。金属化图案148可以是以与金属化图案144类似的方式和类似的材料形成。在一些实施例中，金属化图案148具有与金属化图案144不同的尺寸。例如，金属化图案148的导线和/或通孔可以比金属化图案144的导线和/或通孔更宽或更厚。此外，金属化图案148可以形成为比金属化图案144更大的间距。
然后，介电层150沉积在金属化图案148和介电层146上。介电层150可以以类似于介电层142的方式形成，并且可以由与介电层142类似的材料形成。
然后形成金属化图案152。金属化图案152包括在介电层150的主表面上并沿着介电层150的主表面延伸的线部分。金属化图案152还包括延伸通过介电层150以物理耦接和电耦接金属化图案148的通孔部分。金属化图案152可以是以与金属化图案144类似的方式和类似的材料形成。金属化图案152是前侧再分布结构140的最顶部金属化图案。因此，前侧再分布结构的所有中间金属化图案140(例如，金属化图案144和148)设置在金属化图案152和集成电路管芯50之间。在一些实施例中，金属化图案152具有与金属化图案144和148不同的尺寸。例如，金属化图案152的导线和/或通孔可以比金属化图案144和148的导线和/或通孔更宽或更厚。此外，金属化图案152可以形成为比金属化图案148更大的间距。
然后，介电层154沉积在金属化图案152和介电层150上。介电层154可以以类似于介电层142的方式形成，并且可以由与介电层142类似的材料形成。
在图12中，形成用于外部连接到前侧再分布结构140的凸块下金属(UBM)156。UBM156具有在介电层154的主表面上并且沿着介电层154的主表面延伸的凸块部分，并且具有延伸穿过介电层154以物理耦接和电耦接金属化图案152的通孔部分。因此，UBM 156电耦接至通孔116和集成电路管芯50。UBM156可以由与金属化图案144相同的材料形成。在一些实施例中，UBM 156具有与金属化图案144、148和152不同的尺寸。
接下来，导电连接件158形成在UBM 156上。导电连接件158可以是球栅阵列(BGA)连接件、焊料球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯-浸金技术(ENEPIG)形成的凸块等。导电连接件158可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合。在一些实施例中，导电连接件158通过蒸发、电镀、印刷、焊料转移、焊球放置等首先形成焊料层来形成。一旦在结构上形成焊料层就可以执行回流焊以将材料成形为所需的凸块形状。在另一实施例中，导电连接件158包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本上垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属覆盖层。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，并且可以通过镀工艺来形成。
在图13中，执行载体衬底去接合以将载体衬底102与背侧再分布结构106(例如，介电层108)分离(或“去接合”)。根据一些实施例，去接合包括在释放层104上投射诸如激光或UV光的光，以使得释放层104在光的热量下分解并且载体衬底102可以被去除。然后将结构翻转并放置在带上。
在图14中，形成延伸穿过介电层108以接触金属化图案110的导电连接件160。形成穿过介电层108以暴露金属化图案110的部分的开口。例如，可以使用激光钻孔、蚀刻等来形成开口。导电连接件160形成在开口中。在一些实施例中，导电连接件160包括助熔剂并且在助熔剂浸渍工艺中形成。在一些实施例中，导电连接件160包括诸如焊料膏、银膏等的导电膏，并且在印刷工艺中被分配。在一些实施例中，导电连接件160以与导电连接件158类似的方式形成，并且可以由与导电连接件158类似的材料形成。
图15和图16示出了根据一些实施例的器件堆叠件的形成和实施。器件堆叠件由形成在第一封装组件100中的集成电路封装件形成。器件堆叠件也可以被称为叠层封装(PoP)结构。
在图15中，第二封装组件200耦接至第一封装组件100。第二封装组件200中的一个耦接在每个封装区域100A和100B中，以在每个封装区域中形成集成电路器件堆叠件。
第二封装组件200包括衬底202和耦接至衬底202的一个或多个管芯。在所示的实施例中，管芯包括堆叠的管芯204A和204B。在一些实施例中，管芯(或管芯堆叠件)可以设置为并排耦接至衬底202的相同表面。衬底202可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟等及其组合的复合材料。另外，衬底202可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料的层，诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或其组合。在一个可选实施例中，衬底202基于绝缘芯，诸如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。可选的，芯材料的替代材料包括双马来酰亚胺三嗪BT树脂、或者其他印刷电路板(PCB)材料或膜。诸如味之素(Ajinomoto)积聚膜(ABF)或其他层压的积聚膜可以用于衬底202。
衬底202可以包括有源器件和无源器件(未示出)。可以使用诸如晶体管、电容器、电阻器、其组合等的各种器件，来生成用于第二封装组件200的设计的结构和功能要求。器件可以使用任何合适的方法来形成。
衬底202还可以包括金属化层(未示出)和导电通孔206。金属化层可以形成在有源器件和无源器件上方并且被设计为连接各种器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，具有将导电材料层互连的通孔，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双重镶嵌等)形成。在一些实施例中，衬底202基本上不具有有源器件和无源器件。
衬底202可以具有位于衬底202的第一侧上以耦接至堆叠的管芯204A和204B的接合焊盘208，和位于衬底202的第二侧上以耦接至导电连接件160的接合焊盘210，衬底202的第二侧与第一侧相对。在一些实施例中，通过在衬底202的第一侧和第二侧上形成至介电层中的凹槽来形成接合焊盘208和210。凹槽可以形成为允许接合焊盘208和210嵌入到介电层中。在其他实施例中，由于可以在介电层上形成接合焊盘208和210，因此省略了凹槽。在一些实施例中，接合焊盘208和210包括由铜、钛、镍、金、钯等或其组合制成的薄晶种层。接合焊盘208和210的导电材料可以沉积在薄晶种层上方。可以通过电化学镀工艺、化学镀工艺、CVD、原子层沉积(ALD)、PVD等或其组合来形成导电材料。在实施例中，接合焊盘208和210的导电材料是铜、钨、铝、银、金等或其组合。
在一个实施例中，接合焊盘208和210是包括三个导电材料层的UBM，其，诸如钛层、铜层和镍层。材料和层的其他布置可以用于形成接合焊盘208和210，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置、或铜/镍/金的布置。可以用于接合焊盘208和210的任何合适的材料或材料层完全旨在包括在本申请的范围内。在一些实施例中，导电通孔206延伸穿过衬底202，并且将接合焊盘208中的至少一个耦接至接合焊盘210中的至少一个。
在所示的实施例中，堆叠的管芯204A和204B通过引线接合212耦接至衬底202，但是可以使用诸如导电凸块的其他连接。在一个实施例中，堆叠的管芯204A和204B是堆叠的存储器管芯。例如，堆叠的管芯204A和204B可以是存储器管芯，诸如低功率(LP)双倍数据速率(DDR)存储器模块(诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4)等的存储器模块。
可以通过模制材料214密封堆叠的管芯204A和204B以及引线接合212。例如，可以使用压缩模制将模制材料214模制在堆叠的管芯204A和204B以及引线接合212上。在一些实施例中，模制材料214是模塑料、聚合物、环氧树脂、氧化硅填充材料等或其组合。可以执行固化工艺以固化模制材料214；固化工艺可以是热固化、UV固化等或其组合。
在一些实施例中，堆叠的管芯204A和204B以及引线接合212被掩埋在模制材料214中，并且在固化模制材料214之后，执行诸如研磨的平坦化步骤，以去除模制材料214的多余部分并为第二封装组件200提供基本上平坦的表面。
在形成第二封装组件200之后，通过导电连接件160、接合焊盘208和210以及背侧再分布结构106的金属化图案，将第二封装组件200机械接合和电接合到第一封装组件100。在一些实施例中，通过引线接合212、接合焊盘208和210、导电通孔206、导电连接件160、背侧再分布结构106、通孔116和前侧再分布结构140，可以将堆叠的管芯204A和204B耦接至集成电路管芯50。
在一些实施例中，在衬底202的与堆叠的管芯204A和204B相对的一侧上形成阻焊剂。导电连接件160可以设置在阻焊剂中的开口中，以电耦接和机械耦接至衬底202中的导电部件(例如，接合焊盘210)。阻焊剂可以用于保护衬底202的区域免受外部损坏。
在一些实施例中，导电连接件160可以具有形成在其上的环氧树脂助焊剂(未示出)，然后回流在将第二封装组件200附接至第一封装组件400之后剩余的环氧树脂助焊剂的至少一些环氧树脂部分。
在一些实施例中，底部填充物形成在第一封装组件100和第二封装组件200之间，围绕导电连接件160。底部填充物可以减小应力并且保护由回流导电连接件160产生的接头。底部填充物可以在附接第二封装组件200之后通过毛细管流工艺来形成，或者可以在附接第二封装组件200之前通过适当的沉积方法来形成。在形成环氧助焊剂的实施例中，环氧助焊剂可以用作底部填充物。
在图16中，通过沿着例如第一封装区域100A和第二封装区域100B之间的划线区域进行锯切来执行分割工艺。锯切将第一封装区域100A与第二封装区域100B分割。因此，分割的器件堆叠件来自第一封装区域100A或第二封装区域100B中的一个。在示出的实施例中，在第二封装组件200耦接至第一封装组件100之后执行分割工艺。在其他实施例中，在第二封装组件200耦接至第一封装组件100之前执行分割工艺，诸如在载体衬底102被去接合以及形成导电连接件160之后。
然后，使用导电连接件158将从第一封装组件100分割的每个集成电路封装件安装至封装衬底300。封装衬底300包括衬底芯302和在衬底芯302上的接合焊盘304。衬底芯302可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化铟镓、其组合等的化合物材料。另外，衬底芯302可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或其组合的半导体材料的层。在一个可选实施例中，衬底芯302是基于诸如玻璃纤维增强树脂芯的绝缘芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。芯材料的替代材料包括双马来酰亚胺三嗪BT树脂、或者其他PCB材料或膜。诸如ABF或其他层压的积聚膜可以用于衬底芯302。
衬底芯302可以包括有源器件和无源器件(未示出)。如本领域的普通技术人员将认识到的，可以使用诸如晶体管、电容器、电阻器、其组合、等的各种器件，来生成用于器件堆叠件的设计的结构和功能要求。器件可以使用任何合适的方法来形成。
衬底芯302还可以包括金属化层和通孔(未示出)，接合焊盘304物理耦接和/或电耦接至金属化层和通孔。金属化层可以形成在有源器件和无源器件上方，并且被设计为连接各种器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，具有将导电材料层互连的通孔，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双重镶嵌等)形成。在一些实施例中，衬底芯302基本上不具有有源器件和无源器件。
在一些实施例中，回流导电连接件158以将第一封装组件100附接到接合焊盘304。导电连接件158将包括衬底芯302中的金属化层的封装衬底300电耦接和/或物理耦接至第一封装组件100。在第一实施例中，阻焊剂306形成在第一封装组件100上。在一些实施例中，阻焊剂306形成在衬底芯302上。导电连接件158可以设置在阻焊剂306中的开口中，以电耦接和机械耦接至接合焊盘304。阻焊剂306可用于保护衬底202的区域免受外部损坏。
导电连接件158可以具有在其上形成的环氧树脂助焊剂，然后回流在将第一封装组件100附接至封装衬底300之后剩余的环氧树脂助焊剂的至少一些环氧树脂部分。剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由回流导电连接件158产生的接头。在一些实施例中，底部填充物308可以形成在第一封装组件100和封装衬底300之间并且围绕导电连接件158。底部填充物308可以在附接第一封装组件100之后通过毛细管流工艺来形成，或者可以在附接第一封装组件100之前通过适当的沉积方法来形成。
在一些实施例中，可以将无源器件(例如，表面安装器件(SMD)，未示出)附接到第一封装组件100(例如，附接到UBM 156)或者附接到封装衬底300(例如，附接到接合焊盘304)。例如，无源器件可以与导电连接件158接合到第一封装组件100或封装衬底300的相同表面。无源器件可以在第一封装组件100被安装在封装衬底300上之前附接到第一封装组件100，或者可以在第一封装组件100被安装在封装衬底300上之前或之后附接到封装衬底300。
应当理解，可以在其他器件堆叠件中实施第一封装组件100。示出了PoP结构，但是例如也可以在倒装芯片球栅阵列(FCBGA)封装件中实施第一封装组件100。在这样的实施例中，第一封装组件100被安装到诸如封装衬底300的衬底，但是第二封装组件200被省略。替代地，可以将盖或散热器附接到第一封装组件100。当省略第二封装组件200时，也可以省略背侧再分布结构106和通孔116。
也可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装或3DIC器件的验证测试。例如，测试结构可以包括形成在再分布层中或衬底上的测试焊盘，这允许使用探针和/或探针卡等测试3D封装或3DIC。可以在中间结构以及最终结构上执行验证测试。另外，本文公开的结构和方法可以与结合了已知良管芯的中间验证的测试方法结合使用，以增加良率并降低成本。
图17示出了根据一些其他实施例的第一封装组件100的截面图。该实施例类似于图12的实施例，但是省略了通孔116和背侧再分布结构106。该实施例的第一封装组件100可以在随后的工艺中被分割并且用于实施诸如关于图15和图16所描述的那些器件堆叠件。
图18示出了根据一些其他实施例的第一封装组件100的截面图。在该实施例中，前侧再分布结构140具有细部件部分140A和粗部件部分140B。再分布结构140的细部件部分140A包括介电层142、146、150和154；以及金属化图案144、148和152。再分布结构140的粗部件部分140B包括介电层162、166和170；以及金属化图案164、166和168。再分布结构140的细部件部分140A和粗部件部分140B包括不同尺寸的金属化图案和介电层。例如，介电层142、146、150和154形成为小于介电层162、166和170的厚度，并且金属化图案144、148和152形成为小于金属化图案164、166和168的厚度。介电层162、166和170可以以类似于介电层142、146、150和154的方式形成，并且可以由与介电层142、146、150和154类似的材料形成。可选地，介电层162、166和170可以由与介电层142、146、150和154不同的材料形成。在一些实施例中，介电层142、146、150和154包括诸如PBO、聚酰亚胺、BCB等的光敏材料，并且介电层162、166和170包括模塑料、环氧树脂等。该实施例的第一封装组件100可以在随后的工艺中被分割并且用于实施诸如关于图15和图16所描述的那些器件堆叠件。
图19示出了根据一些其他实施例的第一封装组件100的截面图。该实施例类似于图18的实施例，但是省略了通孔116和背侧再分布结构106。该实施例的第一封装组件100可以在随后的工艺中被分割并且用于实施诸如关于图15和图16所描述的那些器件堆叠件。
图20示出了根据一些其他实施例的第一封装组件100的截面图。在该实施例中，前侧再分布结构140包括金属化图案172、174、176和178，金属化图案172、174、176和178使用与金属化图案144、148和152不同的技术形成。金属化图案172仅包括延伸穿过介电层142的通孔部分，并且不包括沿着介电层142的主表面延伸的线部分。金属化图案174和176包括分别沿着介电层142和146的主表面延伸的线部分，并且还包括分别延伸穿过介电层146和150的通孔部分。每个金属化图案174和176的形成可以包括使用多个掩模。例如，可以使用第一掩模来镀线部分，并且可以使用第二掩模来镀通孔部分。金属化图案178仅包括沿着介电层154的主表面延伸的线部分，并且不包括延伸穿过介电层150的通孔部分。UBM156形成为延伸穿过介电层154以耦接金属化图案178。该实施例的第一封装组件100可以在随后的工艺中被分割并且用于实施诸如关于图15和图16所描述的那些器件堆叠件。
图21示出了根据一些其他实施例的第一封装组件100的截面图。该实施例类似于图20的实施例，但是省略了通孔116和背侧再分布结构106。该实施例的第一封装组件100可以在随后的工艺中被分割并且用于实施诸如关于图15和图16所描述的那些器件堆叠件。
实施例可以实现许多优势。在形成介电层78之前从管芯连接件60去除可回流焊连接件70，可以在介电层78的固化工艺期间防止焊料润湿。此外，通过蚀刻工艺74而不是通过CMP来去除可回流焊连接件70，可以帮助减少集成电路管芯50中残留的焊料的量。
在实施例中，方法包括：接收集成电路管芯，集成电路管芯包括：接触焊盘，位于半导体衬底上；钝化层，位于接触焊盘和半导体衬底上；管芯连接件，延伸穿过钝化层，管芯连接件物理耦接和电耦接至接触焊盘，管芯连接件包括第一导电材料，第一导电材料是具有第一酸硬度/软度指数的路易斯酸；可回流焊连接件，位于管芯连接件上，可回流焊连接件包括第二导电材料，第二导电材料是具有第二酸硬度/软度指数的路易斯酸；以及用蚀刻溶液蚀刻可回流焊连接件和管芯连接件，蚀刻溶液包括用于第一导电材料的保护剂和用于第二导电材料的蚀刻剂，保护剂是唑，唑是具有第一配体硬度/软度指数的路易斯碱，其中，第一酸硬度/软度指数与第一配体硬度/软度指数的乘积为正，并且第二酸硬度/软度指数与第一配体硬度/软度指数的乘积为负。
在方法的一些实施例中，唑是包括多个氮原子的五元杂环化合物。在方法的一些实施例中，五元杂环化合物是包括甲基吡唑的吡唑化合物。在方法的一些实施例中，五元杂环化合物是包含甲基咪唑的咪唑化合物。在方法的一些实施例中，五元杂环化合物是包括苯并***的***化合物。在方法的一些实施例中，五元杂环化合物是包括苯基四唑或苯基巯基四唑的四唑化合物。在方法的一些实施例中，五元杂环化合物是包括戊唑(HN5)的戊唑化合物。在方法的一些实施例中，管芯连接件包括：第一导电层，包括第一导电材料；以及第二导电层，位于第一导电层上，第二导电层包括第三导电材料，第三导电材料是具有第三酸硬度/软度指数的路易斯酸，其中，第三酸硬度/软度指数与第一配体硬度/软度指数的乘积为负，其中，蚀刻可回流焊连接件将第一导电层的第一宽度减小0.05％至30％的范围，以及其中，蚀刻可回流焊连接件不减小第二导电层的第二宽度。在一些实施例中，方法还包括：在蚀刻可回流焊连接件和管芯连接件之前，测试集成电路管芯。在一些实施例中，方法还包括：在蚀刻可回流焊连接件和管芯连接件之后，在管芯连接件和钝化层上沉积介电层。
在实施例中，方法包括：在半导体衬底上形成接触焊盘；在接触焊盘和半导体衬底上沉积钝化层；在钝化层中图案化暴露接触焊盘的开口；在开口中和接触焊盘上镀管芯连接件，管芯连接件包括第一导电材料；回流位于管芯连接件上的可回流焊连接件；以及用蚀刻溶液蚀刻可回流焊连接件和管芯连接件以去除可回流焊连接件，蚀刻溶液包括蚀刻剂和保护剂，保护剂是包括用于接合至第一导电材料的多个活性位点的五元杂环化合物。
在方法的一些实施例中，蚀刻可回流焊连接件和管芯连接件包括：将可回流焊连接件和管芯连接件浸入蚀刻溶液的浴中。在方法的一些实施例中，蚀刻可回流焊连接件和管芯连接件包括：将蚀刻溶液喷涂在可回流焊连接件和管芯连接件上。在方法的一些实施例中，喷涂蚀刻溶液包括：以100RPM至3000RPM范围内的速度旋转半导体衬底，同时以0.2L/min至2L/min范围内的流速使蚀刻溶液流过半导体衬底上方。在方法的一些实施例中，蚀刻可回流焊连接件和管芯连接件包括：在5℃至50℃范围内的温度下蚀刻可回流焊连接件和管芯连接件0.1分钟至120分钟范围内的持续时间。在方法的一些实施例中，蚀刻溶液包括浓度在0.0001％至2％范围内的保护剂、浓度在0.1％至20％范围内的蚀刻剂和0.5％至50％范围内的溶剂。在方法的一些实施例中，蚀刻剂是铁(III)或铜(II)，并且溶剂是硝酸或硫酸。
在实施例中，器件包括：半导体衬底；接触焊盘，位于半导体衬底上；钝化层，位于接触焊盘和半导体衬底上；管芯连接件，延伸穿过钝化层，管芯连接件物理耦接和电耦接至接触焊盘，管芯连接件包括第一导电材料，第一导电材料是具有第一酸硬度/软度指数的路易斯酸；介电层，位于管芯连接件和钝化层上；以及保护层，设置在介电层和管芯连接件之间，保护层围绕管芯连接件，保护层包括第一导电材料和唑的配位络合物，唑是具有第一配体硬度/软度指数的路易斯碱，其中，第一酸硬度/软度指数和第一配体硬度/软度指数的乘积为正。
在器件的一些实施例中，管芯连接件具有：外部区域，包括第一导电材料和配位络合物的化合物；以及内部区域，不具有配位络合物。在器件的一些实施例中，保护层具有在
Figure BDA0002754215600000271
至
Figure BDA0002754215600000272
范围内的厚度。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基底来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并且不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成集成电路封装件的方法，包括：
接收集成电路管芯，所述集成电路管芯包括：
接触焊盘，位于半导体衬底上；
钝化层，位于所述接触焊盘和所述半导体衬底上；
管芯连接件，延伸穿过所述钝化层，所述管芯连接件物理耦接和电耦接至所述接触焊盘，所述管芯连接件包括第一导电材料，所述第一导电材料是具有第一酸硬度/软度指数的路易斯酸；和
可回流焊连接件，位于所述管芯连接件上，所述可回流焊连接件包括第二导电材料，所述第二导电材料是具有第二酸硬度/软度指数的路易斯酸；以及
用蚀刻溶液蚀刻所述可回流焊连接件和所述管芯连接件，所述蚀刻溶液包括用于所述第一导电材料的保护剂和用于所述第二导电材料的蚀刻剂，所述保护剂是唑，所述唑是具有第一配体硬度/软度指数的路易斯碱，
其中，所述第一酸硬度/软度指数与所述第一配体硬度/软度指数的乘积为正，并且所述第二酸硬度/软度指数与所述第一配体硬度/软度指数的乘积为负。
2.根据权利要求1所述的方法，其中，所述唑是包括多个氮原子的五元杂环化合物。
3.根据权利要求2所述的方法，其中，所述五元杂环化合物是包括甲基吡唑的吡唑化合物。
4.根据权利要求2所述的方法，其中，所述五元杂环化合物是包含甲基咪唑的咪唑化合物。
5.根据权利要求2所述的方法，其中，所述五元杂环化合物是包括苯并***的***化合物。
6.根据权利要求2所述的方法，其中，所述五元杂环化合物是包括苯基四唑或苯基巯基四唑的四唑化合物。
7.根据权利要求2所述的方法，其中，所述五元杂环化合物是包括戊唑(HN5)的戊唑化合物。
8.根据权利要求1所述的方法，其中，所述管芯连接件包括：
第一导电层，包括所述第一导电材料；以及
第二导电层，位于所述第一导电层上，所述第二导电层包括第三导电材料，所述第三导电材料是具有第三酸硬度/软度指数的路易斯酸，
其中，所述第三酸硬度/软度指数与所述第一配体硬度/软度指数的乘积为负，
其中，所述蚀刻所述可回流焊连接件将所述第一导电层的第一宽度减小0.05％至30％的范围，以及
其中，所述蚀刻所述可回流焊连接件不减小所述第二导电层的第二宽度。
9.一种形成集成电路封装件的方法，包括：
在半导体衬底上形成接触焊盘；
在所述接触焊盘和所述半导体衬底上沉积钝化层；
在所述钝化层中图案化暴露所述接触焊盘的开口；
在所述开口中和所述接触焊盘上镀管芯连接件，所述管芯连接件包括第一导电材料；
回流位于所述管芯连接件上的可回流焊连接件；以及
用蚀刻溶液蚀刻所述可回流焊连接件和所述管芯连接件以去除所述可回流焊连接件，所述蚀刻溶液包括蚀刻剂和保护剂，所述保护剂是包括用于接合至第一导电材料的多个活性位点的五元杂环化合物。
10.一种集成电路器件，包括：
半导体衬底；
接触焊盘，位于所述半导体衬底上；
钝化层，位于所述接触焊盘和所述半导体衬底上；
管芯连接件，延伸穿过所述钝化层，所述管芯连接件物理耦接和电耦接至所述接触焊盘，所述管芯连接件包括第一导电材料，所述第一导电材料是具有第一酸硬度/软度指数的路易斯酸；
介电层，位于所述管芯连接件和所述钝化层上；以及
保护层，设置在所述介电层和所述管芯连接件之间，所述保护层围绕所述管芯连接件，所述保护层包括所述第一导电材料和唑的配位络合物，所述唑是具有第一配体硬度/软度指数的路易斯碱，
其中，所述第一酸硬度/软度指数和所述第一配体硬度/软度指数的乘积为正。
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