CN112750402A - Display panel, array substrate and driving method thereof - Google Patents
Display panel, array substrate and driving method thereof Download PDFInfo
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- CN112750402A CN112750402A CN201911037232.3A CN201911037232A CN112750402A CN 112750402 A CN112750402 A CN 112750402A CN 201911037232 A CN201911037232 A CN 201911037232A CN 112750402 A CN112750402 A CN 112750402A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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Abstract
The invention provides a display panel, an array substrate and a driving method thereof. The array substrate includes: the display device comprises a first display area and a second display area, wherein the first display area comprises a plurality of first pixel units arranged in an array; the second display area is positioned on at least one side of the first display area; the second display area comprises a plurality of second pixel units which are arranged in an array, the second pixel units are divided into a first sub-pixel unit and a second sub-pixel unit, and the arrangement density of the sub-pixel units in the second display area is greater than that of the first pixel units in the first display area; each first sub-pixel unit and each second sub-pixel unit are respectively connected to a first grid line and a second grid line; the first grid driving circuit is connected to the first sub-pixel unit through the first grid line; and a second gate driving circuit connected to the second sub-pixel unit through the second gate line. The invention can improve the burn-in phenomenon of a static display area which needs to keep the same display strength for a long time in the display and prolong the service life of the OLED device.
Description
Technical Field
The invention relates to the field of display panels, in particular to a display panel, an array substrate and a driving method of the array substrate.
Background
With the development of society and the continuous progress of science and technology, the requirements of people on display screens are higher and higher. AMOLED (Active-matrix organic light-emitting diode) is a trend of next generation display screen development. The burn-in phenomenon is a common problem of the AMOLED display device, and is usually manifested in that the decay rate of the lifetime of the OLED device is higher than that of other areas due to the fact that the pixels maintain the same display intensity for a long time, and the decay rate is often generated in a static display area of the display. This problem is currently mainly ameliorated by switching to longer-lived OLED materials.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present invention and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a display panel, an array substrate and a driving method thereof, which are used for improving the screen burning phenomenon of a static display area which needs to keep the same display strength for a long time in a display and prolonging the service life of an OLED device.
According to an aspect of the present invention, there is provided an array substrate including:
the display device comprises a first display area and a second display area, wherein the first display area comprises a plurality of first pixel units arranged in an array;
the second display area is positioned on at least one side of the first display area; the second display area comprises a plurality of second pixel units arranged in an array, each second pixel unit is divided into a first sub-pixel unit and a second sub-pixel unit, and the arrangement density of the sub-pixel units in the second display area is greater than that of the first pixel units in the first display area; each first sub-pixel unit and each second sub-pixel unit are respectively electrically connected to a first grid line and a second grid line;
a first gate driving circuit electrically connected to the first sub-pixel unit through the first gate line; and
and the second grid driving circuit is electrically connected to the second sub-pixel unit through the second grid line.
In an embodiment of the present invention, an area of the first sub-pixel unit is larger than an area of the second sub-pixel unit, and the areas of the first sub-pixel unit and the second sub-pixel unit are both smaller than the area of the first pixel unit.
In an embodiment of the present invention, an area ratio of the light-transmitting region in the first sub-pixel unit and an area ratio of the light-transmitting region in the second sub-pixel unit are both greater than an area ratio of the light-transmitting region in the first pixel unit.
In an embodiment of the invention, the first sub-pixel unit and the second sub-pixel unit constituting the same second pixel unit are electrically connected to the same data line.
In an embodiment of the invention, the first sub-pixel unit and the second sub-pixel unit constituting the same second pixel unit are electrically connected to a first data line and a second data line, respectively.
In an embodiment of the invention, the first gate driving circuit and the second gate driving circuit are disposed on two opposite sides of the array substrate.
In an embodiment of the invention, in at least one first direction, two adjacent first sub-pixel units are separated by one second sub-pixel unit.
In an embodiment of the present invention, the first sub-pixel unit includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the second sub-pixel unit includes a fourth color sub-pixel.
According to another aspect of the present invention, there is provided a display panel including the array substrate as described above.
According to still another aspect of the present invention, there is provided a driving method applied to the array substrate, the driving method including:
providing a first gate signal to the first sub-pixel unit through the first gate driving circuit;
providing a second gate signal to the second sub-pixel unit through the second gate driving circuit;
and controlling the voltages of the first gate signal and the second gate signal at the same time to control the first sub-pixel unit and the second sub-pixel unit to display simultaneously or separately.
According to still another aspect of the present invention, there is provided a display device including the display panel as described above.
According to the invention, each second pixel unit in a second display area is divided into a first sub-pixel unit and a second sub-pixel unit, and the arrangement density of the sub-pixel units in the second display area is greater than that of the first pixel units in the first display area; each first sub-pixel unit is electrically connected to the first grid drive circuit through a first grid line; each second sub-pixel unit is electrically connected to the first grid driving circuit through a second grid line. Based on the above, the voltages of the first gate signal and the second gate signal at the same time can be controlled according to requirements, so as to control the first sub-pixel unit and the second sub-pixel unit to display at the same time or separately. Furthermore, by controlling the first sub-pixel unit and the second sub-pixel unit to switch and display at different time, the burn-in phenomenon of a static display area in the display, which needs to keep the same display intensity for a long time, can be improved, and the service life of the OLED device is prolonged. In addition, the resolution or the brightness of the second display area can be improved by controlling the first sub-pixel unit and the second sub-pixel unit to display simultaneously.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention, and further features, objects, and advantages of the invention will become apparent from a reading of the following detailed description of non-limiting embodiments with reference to the drawings. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention.
Fig. 2 is an enlarged schematic view of a second pixel unit in the array substrate shown in fig. 1.
Fig. 3 is a schematic structural diagram of an array substrate according to another embodiment of the invention.
Fig. 4 is an enlarged schematic view of a second pixel unit in the array substrate shown in fig. 3.
FIG. 5 is a diagram of a shift register according to an embodiment of the present invention. And
fig. 6 is a driving timing diagram of the shift register shown in fig. 5.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention. Fig. 2 is an enlarged schematic view of a second pixel unit in the array substrate shown in fig. 1. Fig. 3 is a schematic structural diagram of an array substrate according to another embodiment of the invention. Fig. 4 is an enlarged schematic view of a second pixel unit in the array substrate shown in fig. 3. FIG. 5 is a diagram of a shift register according to an embodiment of the present invention. And FIG. 6 is a timing diagram of driving the shift register shown in FIG. 5.
According to an aspect of the present invention, there is provided an array substrate, as shown in fig. 1 to 4, the array substrate including: a first display region, a second display region, a first gate driving circuit 110, and a second gate driving circuit 120. The first display area comprises a plurality of first pixel units P arranged in an array; the second display area is positioned on at least one side of the first display area; the second display area comprises a plurality of second pixel units arranged in an array, each second pixel unit is divided into a first sub-pixel unit P1 and a second sub-pixel unit P2, and the arrangement density of the sub-pixel units in the second display area is greater than that of the first pixel units P in the first display area; each of the first sub-pixel unit P1 and the second sub-pixel unit P2 are electrically connected to a first gate line G1 and a second gate line G2, respectively; the first gate driving circuit 110 is electrically connected to the first sub-pixel unit P1 through the first gate line G1; and the second gate driving circuit 120 is electrically connected to the second sub-pixel unit P2 through the second gate line G2.
According to the invention, each second pixel unit in the second display area is divided into a first sub-pixel unit P1 and a second sub-pixel unit P2, and the arrangement density of the sub-pixel units in the second display area is greater than that of the first pixel units P in the first display area; each of the first sub-pixel units P1 is electrically connected to the first gate driving circuit 110 through a first gate line G1; each of the second sub-pixel units P2 is electrically connected to the first gate driving circuit 110 through a second gate line G2. Based on this, the voltages of the first gate signal and the second gate signal at the same time can be controlled according to requirements to control the first sub-pixel unit P1 and the second sub-pixel unit P2 to display at the same time or separately. Further, by controlling the first sub-pixel unit P1 and the second sub-pixel unit P2 to switch the display at different times, the burn-in phenomenon in a static display area of the display, which needs to maintain the same display intensity for a long time, can be improved, and the lifetime of the OLED device can be increased. In addition, the resolution or brightness of the second display region may also be improved by controlling the first sub-pixel unit P1 to be displayed simultaneously with the second sub-pixel unit P2.
In one embodiment of the present invention, the area of the first sub-pixel unit P1 is larger than that of the second sub-pixel unit P2, and the areas of the first sub-pixel unit P1 and the second sub-pixel unit P2 are smaller than that of the first pixel unit P. Therefore, the arrangement density of the sub-pixel units in the second display area is larger than that of the first pixel units P in the first display area. Whereby the brightness or resolution of the second display area can be increased. As shown in fig. 1 and 2, in an embodiment of the present invention, the first sub-pixel unit P1 and the second sub-pixel unit P2 constituting the same second pixel unit are electrically connected to the same first data line DL1, so that not only the brightness of the second display area can be improved, but also the number of data lines can be reduced, thereby reducing the difficulty in routing the data lines. In another embodiment of the present invention, as shown in fig. 3 and 4, the first sub-pixel unit P1 and the second sub-pixel unit P2 constituting the same second pixel unit are electrically connected to a first data line DL1 and a second data line DL2, respectively. That is, the data voltages of the first sub-pixel unit P1 and the second sub-pixel unit P2 may be provided by the independent first data line DL1 and the independent second data line DL2, respectively, so that the independent data voltages may be accurately input to the sub-pixel units, the mutual influence between the first sub-pixel unit P1 and the first sub-pixel unit P1 may be avoided, and the resolution of the second display region may be improved.
Further, the area ratio of the light-transmitting region in the first sub-pixel unit P1 and the area ratio of the light-transmitting region in the second sub-pixel unit P2 are both greater than the area ratio of the light-transmitting region in the first pixel unit P. That is, the aperture ratio of the first sub-pixel P1 and the aperture ratio of the second sub-pixel P2 are both greater than the aperture ratio of the first pixel P. Taking the second display area as an example of a static display area of a display that needs to maintain the same display intensity for a long time, the increase of the aperture ratio of the first sub-pixel unit P1 and the second sub-pixel unit P2 can reduce the writing of data voltage under the same brightness, thereby reducing the aging speed of each sub-pixel, improving the burn-in phenomenon of the display, and increasing the lifetime of the OLED device.
Optionally, in at least a first direction, two adjacent first sub-pixel units P1 are separated by one second sub-pixel unit P2. Further, the first sub-pixel unit P1 may include a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the second sub-pixel unit P2 includes a fourth color sub-pixel. The first color sub-pixel, the second color sub-pixel, the third color sub-pixel and the fourth color sub-pixel may be a red sub-pixel, a blue sub-pixel, a green sub-pixel and a white sub-pixel, respectively. Of course, the first sub-pixel unit P1 may also include a fourth color sub-pixel, i.e. a white sub-pixel; the second sub-pixel unit P2 may further include a red sub-pixel, a blue sub-pixel, and a green sub-pixel. The sub-pixels included in each sub-pixel unit can be set according to actual requirements, and are not limited thereto.
With reference to fig. 1 and 3, in the present embodiment, the first gate driving circuit 110 and the second gate driving circuit 120 are disposed on two opposite sides of the array substrate. The first gate driving circuit 110 has a plurality of signal output terminals, each of which is connected to a first gate line G1, and each of the first gate lines G1 is connected to the first pixel units P in the same row. The second gate driving circuit 120 also has a plurality of signal output terminals, each of which is connected to a second gate line G2, and each of the second gate lines G2 is connected to second pixel units in the same row. The first gate driving circuit 110 and the second gate driving circuit 120 may operate simultaneously, that is, high level signals are input to the gate lines connected thereto through the respective signal output terminals, and the first sub-pixel unit P1 and the second sub-pixel unit P2 are scanned simultaneously, so that simultaneous display of the first sub-pixel unit P1 and the second sub-pixel unit P2 is realized. Of course, it is also possible to operate only one of the first and second sub-pixel units P1 and P2 as necessary, thereby implementing separate display of the first and second sub-pixel units P1 and P2. In the present embodiment, the first gate driving circuit 110 controls all the first sub-pixel units P1, and the second gate driving circuit 120 controls all the second sub-pixel units P2, so that the number of gate driving circuits can be reduced, thereby reducing the process difficulty of the array substrate and saving the manufacturing cost. Of course, the present invention may further include independently disposing a third gate driving circuit 130, a plurality of third gate lines G3 and a plurality of third data lines DL 3. The third gate driving circuit 130 is electrically connected to the first pixel unit P through the third gate line G3, and the plurality of third data lines DL3 are respectively connected to one of the first pixel units P. In addition, the specific structure and arrangement of the first pixel unit P, the third gate driving circuit 130, the third gate line G3 and the third data line DL3 can be implemented by the prior art, and the invention is not limited herein.
In this embodiment, the first gate driving circuit 110 may include a plurality of cascaded first shift registers, and the second gate driving circuit 120 includes a plurality of cascaded second shift registers. The output end OUT of each first shift register is connected to a first gate line G1G1, and the output end OUT of each second shift register is connected to a second gate line G2G 2. The array substrate further comprises a first clock generator and a second clock generator. The first clock generator is configured to provide a first clock signal to clock signal terminals of the first shift registers, each of the first shift registers being configured to output a first gate signal to a corresponding first gate line G1G1 in response to a first clock signal CK 1; the second clock generator is configured to provide a second clock signal to clock signal terminals of the second shift registers, each of which is configured to output a second gate signal to a corresponding second gate line G2G2 in response to the second clock signal CK 2. It can be understood by those skilled in the art that, if the timings of the clock signals obtained by the shift registers with the same structure are the same, the output gate signals are also the same, and the same timing of the two clock signals means that the voltages of the two signals at the same time are the same.
In this embodiment, both the first shift register and the second shift register can be implemented by the shift register shown in fig. 5, and certainly, the structures of the first shift register and the second shift register are not limited thereto, and other circuits may be further provided as needed. Specifically, the shift register includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, and a storage capacitor Cst. A first pole of the first transistor T1 is connected to the input terminal IN, a gate of the first transistor T1 is connected to the input terminal IN, and a second pole of the first transistor T1 is connected to the pull-up node PU. A first pole of the second transistor T2 is connected to the pull-up node PU, a gate of the second transistor T2 is connected to the reset terminal RE, and a second pole of the second transistor T2 is connected to the first power source terminal VGL. A first pole of the third transistor T3 is connected to the clock signal terminal CLK, a gate of the third transistor T3 is connected to the pull-up node PU, and a second pole of the third transistor T3 is connected to the output terminal OUT. A first pole of the fourth transistor T4 is connected to the output terminal OUT, a gate of the fourth transistor T4 is connected to the pull-down node PD, and a second pole of the fourth transistor T4 is connected to the first power source terminal VGL. A first pole of the fifth transistor T5 is connected to the second power source terminal VDD, a gate of the fifth transistor T5 is connected to the second power source terminal VDD, and a second pole of the fifth transistor T5 is connected to the pull-down node PD; a first pole of the sixth transistor T6 is connected to the pull-down node PD, a gate of the sixth transistor T6 is connected to the pull-up node PU, and a second pole of the sixth transistor T6 is connected to the first power source terminal VGL. A first terminal of the storage capacitor Cst is connected to the pull-up node PU, and a second terminal of the storage capacitor Cst is connected to the output terminal OUT. The first power voltage provided by the first power terminal VGL may be a low level voltage; the second power voltage supplied from the second power terminal VDD may be a high level voltage. The transistors used in this embodiment may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the present embodiment, in order to distinguish two poles of the transistor except for the gate, one of them is directly described as a first pole, and the other is directly described as a second pole, so that the first pole and the second pole of all or part of the transistors in the present embodiment can be interchanged as necessary. For example, the first electrode of the transistor in this embodiment may be a source, and the second electrode may be a drain; alternatively, the first pole of the transistor is the drain and the second pole is the source. Further, the transistors may be classified into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low level voltage (e.g., 0V) and the turn-off voltage is a high level voltage (e.g., 5V); when the transistor is an N-type transistor, the turn-on voltage is a high level voltage (e.g., 5V) and the turn-off voltage is a low level voltage (e.g., 0V). In the present embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all N-type transistors. The working principle of the shift register in this embodiment is described below with reference to fig. 5 and 6:
IN the first period T1, the input terminal IN receives a high-level input signal, the first transistor T1 inputs the high-level signal to the pull-up node PU, the third transistor T3 is turned on, the sixth transistor T6 is turned on, the sixth transistor T6 inputs a low-level voltage of the first power source terminal VGL to the pull-down node PD, and the second transistor T2 and the fourth transistor T4 are turned off.
In the second period T2, the clock signal terminal CLK receives a clock signal of a high level, and the third transistor T3 transmits the high level signal to the output terminal OUT; due to the bootstrap action of the storage capacitor Cst, the voltage of the pull-up node PU is further raised, so that the third transistor T3 is turned on more sufficiently, and the clock signal of the high level is output to the output terminal OUT through the third transistor T3.
In the third period T3, the reset terminal RE receives a high-level signal, the second transistor T2 is turned on, the second transistor T2 transfers the first power voltage supplied from the first power source terminal VGL of a low level to the pull-up node PU, the sixth transistor T6 is turned off, the fifth transistor T5 transfers the second power voltage supplied from the second power source terminal VDD of a high level to the pull-down node PD, the fourth transistor T4 is turned on, and the fourth transistor T4 transfers the first power voltage supplied from the first power source terminal VGL of a low level to the output terminal OUT.
In summary, the first gate signal output by the first gate driving circuit 110 can be adjusted by adjusting the first clock signal, the second gate signal output by the second gate driving circuit 120 can be adjusted by adjusting the second clock signal, and then the display time of the first sub-pixel P1 and the display time of the second sub-pixel P2 can be switched as required, or the two sub-pixel P1 and the second sub-pixel P2 can be controlled to display simultaneously. Specifically, the second pixel units in the second display area are divided into a first sub-pixel unit P1 and a second sub-pixel unit P2, respectively, and the arrangement density of the sub-pixel units in the second display area is greater than that of the first pixel units P in the first display area; each of the first sub-pixel units P1 is electrically connected to the first gate driving circuit 110 through a first gate line G1; each of the second sub-pixel units P2 is electrically connected to the first gate driving circuit 110 through a second gate line G2. Based on this, the voltages of the first gate signal and the second gate signal at the same time can be controlled according to requirements to control the first sub-pixel unit P1 and the second sub-pixel unit P2 to display at the same time or separately. Further, by controlling the first sub-pixel unit P1 and the second sub-pixel unit P2 to switch the display at different times, the burn-in phenomenon in a static display area of the display, which needs to maintain the same display intensity for a long time, can be improved, and the lifetime of the OLED device can be increased. In addition, the resolution or brightness of the second display region may also be improved by controlling the first sub-pixel unit P1 to be displayed simultaneously with the second sub-pixel unit P2.
According to another aspect of the present invention, there is provided a display panel including the array substrate as described above. In summary, the present invention can improve the burn-in phenomenon of the static display area in the display device that needs to maintain the same display intensity for a long time by controlling the first sub-pixel unit P1 and the second sub-pixel unit P2 to switch the display at different times, thereby increasing the lifetime of the OLED device. In addition, the resolution or brightness of the second display region may also be improved by controlling the first sub-pixel unit P1 to be displayed simultaneously with the second sub-pixel unit P2.
According to still another aspect of the present invention, there is provided a driving method applied to the array substrate, the driving method including:
providing a first gate signal to the first sub-pixel cell P1 through the first gate drive circuit 110;
providing a second gate signal to the second sub-pixel cell P2 through the second gate driving circuit 120;
controlling the first sub-pixel cell P1 and the second sub-pixel cell P2 to display simultaneously or separately by controlling the voltages of the first gate signal and the second gate signal at the same time.
The driving principle of the array substrate is described above and will not be described herein.
In summary, the present invention can improve the burn-in phenomenon of the static display area in the display device that needs to maintain the same display intensity for a long time by controlling the first sub-pixel unit P1 and the second sub-pixel unit P2 to switch the display at different times, thereby increasing the lifetime of the OLED device. In addition, the resolution or brightness of the second display region may also be improved by controlling the first sub-pixel unit P1 to be displayed simultaneously with the second sub-pixel unit P2.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. At least one unit or means recited in the apparatus claims may also be implemented by one unit or means in software or hardware. It is to be understood that the terms "lower" or "upper", "downward" or "upward" and the like are used to describe features of the exemplary embodiments with reference to the positions of such features as displayed in the figures; the terms first, second, etc. are used to denote names, but not any particular order.
Claims (10)
1. An array substrate, comprising:
the display device comprises a first display area and a second display area, wherein the first display area comprises a plurality of first pixel units arranged in an array;
the second display area is positioned on at least one side of the first display area; the second display area comprises a plurality of second pixel units arranged in an array, each second pixel unit is divided into a first sub-pixel unit and a second sub-pixel unit, and the arrangement density of the sub-pixel units in the second display area is greater than that of the first pixel units in the first display area; each first sub-pixel unit and each second sub-pixel unit are respectively connected to a first grid line and a second grid line;
the first grid driving circuit is connected to the first sub-pixel unit through the first grid line; and
and the second grid driving circuit is connected to the second sub-pixel unit through the second grid line.
2. The array substrate of claim 1, wherein the area of the first sub-pixel unit is larger than the area of the second sub-pixel unit, and the areas of the first sub-pixel unit and the second sub-pixel unit are smaller than the area of the first pixel unit.
3. The array substrate of claim 2, wherein the area ratio of the light-transmissive region in the first sub-pixel unit and the area ratio of the light-transmissive region in the second sub-pixel unit are both greater than the area ratio of the light-transmissive region in the first pixel unit.
4. The array substrate of claim 1, wherein a first sub-pixel unit and a second sub-pixel unit constituting the same second pixel unit are connected to the same data line.
5. The array substrate of claim 1, wherein a first sub-pixel unit and a second sub-pixel unit constituting the same second pixel unit are respectively connected to a first data line and a second data line.
6. The array substrate of claim 1, wherein the first gate driving circuit and the second gate driving circuit are disposed on opposite sides of the array substrate.
7. The array substrate of claim 1, wherein two adjacent first sub-pixel units are separated by one second sub-pixel unit in at least one first direction.
8. The array substrate of claim 7, wherein the first sub-pixel unit comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the second sub-pixel unit comprises a fourth color sub-pixel.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. A driving method applied to the array substrate according to any one of claims 1 to 8, comprising:
providing a first gate signal to the first sub-pixel unit through the first gate driving circuit;
providing a second gate signal to the second sub-pixel unit through the second gate driving circuit;
and controlling the voltages of the first gate signal and the second gate signal at the same time to control the first sub-pixel unit and the second sub-pixel unit to display simultaneously or separately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911037232.3A CN112750402A (en) | 2019-10-29 | 2019-10-29 | Display panel, array substrate and driving method thereof |
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