CN112731775B - Photoetching process method for ultra-high depth-to-width ratio graph - Google Patents

Photoetching process method for ultra-high depth-to-width ratio graph Download PDF

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CN112731775B
CN112731775B CN202110011356.5A CN202110011356A CN112731775B CN 112731775 B CN112731775 B CN 112731775B CN 202110011356 A CN202110011356 A CN 202110011356A CN 112731775 B CN112731775 B CN 112731775B
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exposure
ultra
pattern
technology
width ratio
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CN112731775A (en
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程宇
纪明岐
朱至渊
李玉华
吴长明
姚振海
金乐群
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/7045—Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a photoetching process method for ultra-high depth-to-width ratio patterns, which is characterized in that the photoetching patterns are based on a double exposure technology, and simultaneously, the patterns are exposed by adopting a single exposure focusing enhancement technology, and finally, the ultra-high depth-to-width ratio patterns are formed. The invention combines the superposition effect of double exposure technology and single exposure focusing enhancement technology and strong post exposure baking to superpose the projections of the two exposures together, and finally forms the photoetching pattern with ultra-high depth-to-width ratio.

Description

Photoetching process method for ultra-high depth-to-width ratio graph
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to a photoetching process method for an ultra-high aspect ratio pattern.
Background
The contact image sensor (Contact image sensor, abbreviated as CIS) is an emerging image sensor composed of a row of photoelectric sensor arrays, LED light source arrays, lenticular lens arrays, etc. which have the same width as the scanned original. The components are all integrated in a strip square box, no additional optical accessory is needed, and the problems of light path adjustment, depth of field and the like are avoided. In some applications, CIS sensors have an incomparable advantage over CCD or COMS sensors. The light is sensed by a contact type photosensitive element (photosensitive sensor), 300-600 red, green and blue LED (light emitting diode) sensors are tightly arranged at the position of 1-2 mm below a scanning platform to generate a white light source, and the complex mechanisms of a CCD (charge coupled device) array, a lens, a fluorescent tube, a cold cathode ray tube and the like in a CCD scanner are replaced, so that the light, the machine and the electricity of the CCD scanner are integrated into the machine and the electricity of the CIS scanner. The method is widely applied to the fields of fax machines, scanners, banknote sorting and dispensing zero and the like.
The aspect ratio requirement of the layer for pixel region isolation in the CIS process often exceeds 10:1, as shown in fig. 1, is a microscopic image of the deep trench formed in a certain CIS process. The aspect ratio of the level PXHP (P-type high-voltage isolation well) in the CIS of the 90nm node process is 8:1, and the aspect ratio in the CIS of the 65nm node process is already improved to 12:1, as shown in FIG. 2, the depth and width of the CIS are required to reach 15:1 or higher as the CIS process is continuously developed.
And the limit of the process window of the aerial image is limited, the limit of the aspect ratio of single exposure of the common photoresist is 4:1, and the limit of the aspect ratio of single exposure of the CIS photoresist is 8:1.
CIS adopts DET (Double Exposure Technique, double exposure technology), and the DET can break through the limitation of DOF of the depth of field of one exposure, as shown in figure 3, the DOF is enlarged, the process window is increased, and the theoretical maximum aspect ratio limit is 16:1.
The excessive exposure times can affect the throughput on the production line, reduce the production efficiency, and theoretically, three exposure times are not adopted.
Single exposure Focus enhancement EFESE (Enabling Focus Enhancement With Single Exposure) technology is enabled for DOF (Depth of Focus) enhancement, but at the same time EL (Exposure latitude ) is sacrificed and the equipment is also required to be equipped with this function.
The wafer table is tilted about the X-axis, corresponding to an elongated projection, while sacrificing contrast.
The larger the EFESE FR (Focus range, diagonal range), the larger the DOF, the smaller the EL, while the MEEF (mask error enhancement factor, mask Error Enhancement Factor, defined as the slope of the photoresist line width (CD wafer) on the wafer as a function of the pattern line width (CD mask) on the mask) also increases.
Another method is to use the shrink material of merck, germany, as shown in fig. 4, to make a pattern with a certain depth-to-width ratio, then to apply a shrink material coating, and bake PEB after exposure to remove the excess material, so as to obtain a pattern with a higher depth-to-width ratio, and obtain a gap CD exceeding the process limit of the current condition. This method also requires the equipment to be equipped with a separate unit and considers the compatibility with other materials in the same layer and drain region.
In another method, the high-strength flushing material is used for flushing after development, the high-strength flushing material is used for flushing and deionized water is used for flushing, so that the surface tension is reduced, the collapse process window of the pattern is increased, and a machine is required to be provided with a separate unit.
Disclosure of Invention
The invention aims to solve the technical problem of providing a photoetching process method for patterns with ultra-high depth-to-width ratio, which utilizes the existing machine equipment to form the patterns with high depth-to-width ratio.
In order to solve the above problems, the invention provides a lithography process method for ultra-high aspect ratio patterns, comprising:
the photolithography pattern is based on a double exposure technology, and simultaneously, the pattern is exposed by adopting a single exposure focusing enhancement technology, and finally, the pattern with the ultra-high depth-to-width ratio is formed.
The further improvement is that the double exposure technology is used for projecting in two steps, and the aspect ratio of the finally formed graph is the superposition of the two projections.
The double exposure technology is overlapped with the single exposure focusing enhancement technology, the double exposure technology is carried out in two steps, each step is based on the double exposure technology, and the single exposure focusing enhancement technology is overlapped on the double exposure technology of each step, so that each projected pattern of the double exposure technology is elongated again on the basis of the parameter characteristics of the projected pattern.
Further, the method further comprises the step of baking the PEB after exposure after the photoetching pattern is exposed.
The baking is further improved, and the single exposure focusing enhancement technology EFESE function of the machine is combined, namely the wafer bearing platform is inclined around the X axis, twice inclined tilt-X exposure is carried out, and the two projections are fused together through a powerful post-exposure baking process, so that the pattern with the ultra-high depth-to-width ratio is finally obtained.
The further improvement is that the formed pattern with the ultra-high depth-to-width ratio is a pattern with the depth-to-width ratio not smaller than 20:1.
According to the photoetching process method for the ultra-high depth-to-width ratio graph, through the superposition effect of the double exposure technology and the single exposure focusing enhancement technology and combining the strong post exposure baking, the projections of the two exposures are superposed together, and finally the ultra-high depth-to-width ratio photoetching graph is formed.
Drawings
Fig. 1 is a cross-sectional micrograph of a high aspect ratio pattern in a CIS process.
FIG. 2 is a schematic diagram of the larger aspect ratio at different process nodes.
Fig. 3 is a schematic diagram of the double exposure technique DET.
FIG. 4 is a schematic illustration of ultra-high aspect ratio patterns obtained using a shrink material.
FIG. 5 is a schematic diagram illustrating the operation of the present invention for performing a pattern exposure using the dual exposure technique DET in combination with the single exposure focus enhancement EFESE technique.
FIG. 6 is a schematic block diagram of the present invention for pattern exposure using the dual exposure technique DET integrated single exposure focus enhancement EFESE technique.
Detailed Description
The double exposure technique refers to performing two exposures on a photoresist covered wafer, respectively. The two exposures were performed on the same photoresist, but using different reticles. After the two exposures, the wafer is baked and developed. The technological process is abbreviated as: photoresist spin-exposure 1-exposure 2-development-etching. Therefore, double exposure is to expose the same layer of photoresist twice, and the superposition of the light intensities of the two exposures produces the required pattern.
For example, double exposure is used to achieve 50nm 1:1 lines: grooves realized by first exposure (period 200 nm); the same pattern was exposed a second time, but the exposure pattern was shifted 100nm overall. After baking and development, a dense pattern of 50n/50nm will be obtained. The scheme has the advantages that each exposure only needs to distinguish patterns with the period of 200nm, and the illumination condition of each exposure can be optimized according to the mask pattern; moreover, the same photoresist layer is used twice, and the process is simple. Since the wafer does not move on the stage between the two exposures, the alignment error between the two exposures is small. However, double exposure has the disadvantage that if the spatial contrast of the image of the double exposure is low or the scattered light (flare) is very strong, then for areas not requiring exposure, the total light intensity it receives will likely be above the protection threshold E0 of the photoresist, resulting in all the photoresist being developed away. Thus, exposure systems are required to provide higher aerial image contrast. In addition, the photoresist must be highly nonlinear in response to exposure energy, with the additive effect being almost zero, i.e., the loss of photoresist is almost zero when the exposure energy is less than a certain value.
The double exposure technique enables a maximum aspect ratio of 16:1 pattern.
Single exposure focus enhancement EFESE techniques are used to increase depth of field DOF, but at the same time sacrifice exposure latitude.
The photoetching process method for the ultra-high depth-to-width ratio pattern, as shown in fig. 5 and 6, adopts a double exposure technology as a basis for photoetching patterns, adopts a single exposure focusing enhancement technology to expose the patterns, and finally forms the ultra-high depth-to-width ratio pattern.
And the double exposure technology is used for projecting in two steps, the double exposure technology and the single exposure focusing enhancement technology in each step are overlapped, each step is based on the double exposure technology, and the single exposure focusing enhancement technology is overlapped on the double exposure technology in each step, so that each projected pattern of the double exposure technology is elongated again on the basis of the technical parameter characteristics of the double exposure itself. The aspect ratio of the finally formed pattern is the superposition of the two projections.
And after the photoetching pattern is exposed twice, carrying out a post-exposure baking step. And the baking is performed, namely, the wafer bearing platform is inclined around the X axis by combining the single exposure focusing enhancement technology EFESE function of the machine, the twice inclined tilt-X exposure is performed, and the twice projections are fused together by a powerful post-exposure baking process, so that the pattern with the ultra-high depth-to-width ratio of not less than 20:1 can be finally obtained.
The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (5)

1. A photoetching process method for an ultra-high aspect ratio graph is characterized by comprising the following steps: the photoetching pattern is based on a double exposure technology, and simultaneously, the pattern is exposed by adopting a single exposure focusing enhancement technology, and finally, the pattern with the ultra-high depth-to-width ratio is formed;
the double exposure technology and the single exposure focusing enhancement technology are overlapped, the double exposure technology is carried out in two steps, each step is based on the double exposure technology, the single exposure focusing enhancement technology is overlapped on the double exposure technology of each step, and each projection graph of the double exposure technology is elongated again on the basis of the parameter characteristics of the projection graph.
2. The method of claim 1, wherein the ultra-high aspect ratio pattern lithography process is characterized by: in the double exposure technology, the projection is performed in two steps, and the aspect ratio of the finally formed pattern is the superposition of the two projections.
3. The method of claim 1, wherein the ultra-high aspect ratio pattern lithography process is characterized by: the photoetching pattern further comprises a step of baking after exposure.
4. The method for photolithography of ultra-high aspect ratio patterns according to claim 3, wherein: and the baking is combined with the single exposure focusing enhancement technology EFESE function of the machine, namely the wafer bearing platform is inclined around the X axis, twice inclined tilt-X exposure is carried out, and the two projections are fused together through a powerful post-exposure baking process, so that the pattern with the ultra-high depth-to-width ratio is finally obtained.
5. The method for lithography process of ultra-high aspect ratio patterns according to any one of claims 1 to 4, wherein: the formed pattern with the ultra-high depth-to-width ratio is a pattern with the depth-to-width ratio not smaller than 20:1.
CN202110011356.5A 2021-01-06 2021-01-06 Photoetching process method for ultra-high depth-to-width ratio graph Active CN112731775B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246177A (en) * 1996-03-11 1997-09-19 Canon Inc Projection aligner
US5706077A (en) * 1994-04-22 1998-01-06 Canon Kabushiki Kaisha Scan type projection exposure apparatus and microdevice manufacturing method using the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3102025B2 (en) * 1990-10-31 2000-10-23 日本電気株式会社 Reduction projection exposure method
JP3123548B2 (en) * 1998-06-30 2001-01-15 キヤノン株式会社 Exposure method and exposure apparatus
KR20070101907A (en) * 2006-04-12 2007-10-18 주식회사 하이닉스반도체 Method for fabricating pattern using double exposure
CN107731663A (en) * 2017-10-20 2018-02-23 上海华力微电子有限公司 A kind of increase high-aspect-ratio level lithographic process window simultaneously reduces the method for line width
CN107731664A (en) * 2017-10-20 2018-02-23 上海华力微电子有限公司 A kind of method for increasing high-aspect-ratio lithographic process window by double-pattern technology
CN110632829A (en) * 2019-10-31 2019-12-31 上海华力集成电路制造有限公司 Photoetching process method
CN111799156A (en) * 2020-07-16 2020-10-20 上海华力微电子有限公司 Method for forming high aspect ratio pattern

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5706077A (en) * 1994-04-22 1998-01-06 Canon Kabushiki Kaisha Scan type projection exposure apparatus and microdevice manufacturing method using the same
JPH09246177A (en) * 1996-03-11 1997-09-19 Canon Inc Projection aligner

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Address after: 214028 No.30 Xinzhou Road, Xinwu District, Wuxi City, Jiangsu Province

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