CN111799156A - Method for forming high aspect ratio pattern - Google Patents
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- CN111799156A CN111799156A CN202010687576.5A CN202010687576A CN111799156A CN 111799156 A CN111799156 A CN 111799156A CN 202010687576 A CN202010687576 A CN 202010687576A CN 111799156 A CN111799156 A CN 111799156A
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 230
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 238000011161 development Methods 0.000 claims abstract description 18
- 238000012546 transfer Methods 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 6
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052753 mercury Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 11
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 238000002955 isolation Methods 0.000 description 5
- 229930192627 Naphthoquinone Natural products 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000003504 photosensitizing agent Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
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Abstract
The invention provides a method for forming a high-aspect-ratio pattern. The forming method comprises the following steps: forming a first photoresist layer and a second photoresist layer on the first photoresist layer on a semiconductor substrate; carrying out exposure and development processes on the second photoresist layer to transfer a target pattern on the photomask to the second photoresist layer to form a patterned second photoresist layer; and taking the patterned second photoresist layer as a mask layer, and carrying out exposure and development processes on the first photoresist layer so as to transfer the pattern on the second photoresist layer to the first photoresist layer. According to the invention, the first photoresist layer with a preset thickness is formed on the semiconductor substrate, the second photoresist layer with the thickness smaller than that of the first photoresist layer is formed on the first photoresist layer, and then different light sources are adopted to respectively expose and develop the first photoresist layer and the second photoresist layer, so that the problem of small depth of field of the photoresist layer formed on the substrate caused by insufficient exposure and development of the photoresist layer is solved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming a high-aspect-ratio pattern.
Background
In a CMOS (Complementary Metal Oxide Semiconductor) image sensor chip manufacturing process, a pattern structure with a high aspect ratio is often used to meet the design requirements of the device. Currently, in order to form a high aspect ratio pattern structure (e.g., a via or an island structure), a photoresist layer with a relatively thick thickness is usually coated on a substrate surface during a photolithography process, a mask is used to perform multiple exposures on the photoresist layer to copy a pattern on the mask to the photoresist layer, a developing step is then performed to form the high aspect ratio pattern structure in the photoresist layer, and then ion implantation is performed based on the formed photoresist structure.
However, in the process of performing multiple exposures on the photoresist layer, since the photoresist layer has a relatively thick thickness, the photoresist layer having the relatively thick thickness is generally exposed by increasing the energy of the light beam to increase the exposure intensity. At this time, the higher energy light beam may cause the top of the photoresist layer to be overexposed, so that a pattern structure with a high aspect ratio of a desired shape cannot be formed in the photoresist when the subsequent developing step is performed; meanwhile, because the photoresist layer has a relatively thick thickness, the bottom of the photoresist layer is not easily exposed, which results in that the photoresist layer cannot expose the substrate after the subsequent development step is performed. This results in a small depth of field of the photoresist layer formed on the substrate, which leads to low yield and high cost of the finally manufactured semiconductor device.
Therefore, a method for forming a high aspect ratio pattern satisfying a large depth of field on the basis of a conventional dielectric thin film structure is needed to overcome the problem of a small depth of field of a photoresist layer formed on a substrate.
Disclosure of Invention
The invention aims to provide a method for forming a high-aspect-ratio pattern, which aims to solve the problem that the depth of field of a photoresist layer formed on a substrate is small in the existing method for forming the high-aspect-ratio pattern.
In order to solve the above technical problem, the present invention provides a method for forming a high aspect ratio pattern, the method comprising:
providing a semiconductor substrate;
forming a first photoresist layer and a second photoresist layer on the first photoresist layer on the semiconductor substrate;
carrying out exposure and development processes on the second photoresist layer by adopting a first exposure light source so as to transfer a target pattern on the photomask to the second photoresist layer to form a patterned second photoresist layer;
and taking the patterned second photoresist layer as a mask layer, and carrying out exposure and development processes on the first photoresist layer by adopting a second exposure light source so as to transfer the pattern on the second photoresist layer to the first photoresist layer.
Optionally, the wavelength of the first exposure light source is shorter than the wavelength of the second exposure light source.
Optionally, the first exposure light source is a deep ultraviolet DUV light source or an extreme ultraviolet EUV light source.
Optionally, the first exposure light source is KrF excimer laser, ArF excimer laser, or F2 excimer laser.
Optionally, the second exposure light source is an ultraviolet light source with a wavelength greater than 350 nm.
Optionally, the second exposure light source is a high-pressure mercury lamp with a wavelength of 365nm or 436 nm.
Optionally, the first photoresist layer and the second photoresist layer are coated by a spin coating method or a spray coating method.
Optionally, the thickness of the first photoresist is greater than that of the second photoresist.
Optionally, after the pattern on the second photoresist layer is transferred onto the first photoresist layer, the first photoresist layer and the second photoresist layer are combined into a high aspect ratio pattern, and the aspect ratio of the high aspect ratio pattern is 4-30.
Optionally, the ratio of the thickness of the first photoresist layer to the thickness of the second photoresist layer is 2-20; and/or the thickness of the first photoresist layer can be 0.5-3.5 μm, and the thickness of the second photoresist layer can be 0.2-1.5 μm.
Optionally, after transferring the pattern on the second photoresist layer onto the first photoresist layer, the method may further include: etching the semiconductor substrate by taking the first photoresist layer and the second photoresist layer as masks so as to transfer the pattern in the first photoresist layer to the semiconductor substrate;
alternatively, the method may further include: removing the second photoresist layer, and etching the semiconductor substrate by taking the first photoresist layer as a mask so as to transfer the pattern in the first photoresist layer to the semiconductor substrate;
still alternatively, the method further comprises: removing the second photoresist layer, and performing ion implantation on the semiconductor substrate by using the first photoresist layer as a mask to form an ion implantation region in the semiconductor substrate.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. according to the invention, the first photoresist layer with a preset thickness is formed on the semiconductor substrate, the second photoresist layer with the thickness smaller than that of the first photoresist layer is formed on the first photoresist layer, and then different light sources are adopted to respectively expose and develop the first photoresist layer and the second photoresist layer, so that the problem of small depth of field of the photoresist layer formed on the substrate caused by insufficient exposure and development of the photoresist layer is solved.
2. In the embodiment of the invention, a double-layer gluing mode and a respective exposure and development mode are adopted, the first photoresist layer at the lower layer is used for blocking ion implantation, and the second photoresist layer is used for generating the line width required by the process. The second photoresist layer has the characteristic of large depth of field and the first photoresist layer has the characteristics of large density and low cost, and meanwhile, a photomask is not needed when the first photoresist layer is exposed, and a pattern defined in the second photoresist layer can be transferred into the first photoresist layer by only a small amount of energy, so that the aim of forming a high-depth-to-width ratio pattern and reducing the manufacturing cost of a semiconductor device is fulfilled.
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FIG. 1 is a flow chart illustrating a method for forming a high aspect ratio pattern;
fig. 2a to 2e are schematic structural diagrams illustrating a method for forming a high aspect ratio pattern in a manufacturing process according to an embodiment of the invention.
Detailed Description
As described in the background, at present, in order to form a pattern structure satisfying a high aspect ratio required in an image sensor chip manufacturing process, when a photolithography process is performed, a photoresist layer with a relatively thick thickness is generally coated on a surface of a substrate, a photomask is used to perform multiple exposures on the photoresist layer to copy a pattern on the photomask to the photoresist layer, a developing step is performed to form the pattern structure with the high aspect ratio in the photoresist layer, and then ion implantation is performed based on the formed photoresist structure. However, in the process of performing multiple exposures on the photoresist layer, since the photoresist layer has a relatively thick thickness, the photoresist layer having the relatively thick thickness is generally exposed by increasing the energy of the light beam to increase the exposure intensity. At this time, the higher energy light beam may cause the top of the photoresist layer to be overexposed, so that a pattern structure with a high aspect ratio of a desired shape cannot be formed in the photoresist when the subsequent developing step is performed; meanwhile, because the photoresist layer has a relatively thick thickness, the bottom of the photoresist layer is not easily exposed, which results in that the photoresist layer cannot expose the substrate after the subsequent development step is performed. This results in a small depth of field of the photoresist layer formed on the substrate, which leads to low yield and high cost of the finally manufactured semiconductor device.
Therefore, the invention provides a method for forming a high-aspect-ratio pattern, which aims to solve the problem that the depth of field of a photoresist layer formed on a substrate is small in the existing method for forming the high-aspect-ratio pattern. For example, referring to fig. 1, the method for forming the high aspect ratio pattern includes the following steps:
step S100, providing a semiconductor substrate;
step 200, forming a first photoresist layer and a second photoresist layer on the first photoresist layer on the semiconductor substrate;
step S300, carrying out exposure and development processes on the second photoresist layer by adopting a first exposure light source so as to transfer a target pattern on the photomask to the second photoresist layer and form a patterned second photoresist layer;
step S400, taking the patterned second photoresist layer as a mask layer, and performing exposure and development processes on the first photoresist layer by using a second exposure light source, so as to transfer the pattern on the second photoresist layer to the first photoresist layer.
That is, in the invention, a first photoresist layer with a preset thickness is formed on a semiconductor substrate, a second photoresist layer with a thickness smaller than that of the first photoresist layer is formed on the first photoresist layer, and then different light sources are adopted to respectively expose and develop the first photoresist layer and the second photoresist layer, so that the problem of small depth of field of the photoresist layer formed on the substrate caused by insufficient exposure and development of the photoresist layer is avoided.
The method for forming a high aspect ratio pattern according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2a to 2e are schematic structural diagrams illustrating a method for forming a high aspect ratio pattern in a manufacturing process according to an embodiment of the invention.
In step S100, specifically referring to fig. 2a, a semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Illustratively, in this embodiment, the semiconductor substrate 100 is a silicon substrate.
It should be noted that the semiconductor substrate 100 may be a substrate in a front-end-of-line (FEOL) process of integrated circuit manufacturing, or a substrate entering a back-end-of-line (BEOL) process of integrated circuit manufacturing, and various corresponding structures (not shown) may also be defined in the semiconductor substrate 100 or on a surface of the semiconductor substrate 100, for example, an isolation structure may also be formed in the semiconductor substrate 100, and the isolation structure may be a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, and an active region of the semiconductor substrate is defined by the isolation structure.
With continued reference to fig. 2a, in step S200, a first photoresist layer 110 and a second photoresist layer 120 on the first photoresist layer 110 are formed on the semiconductor substrate 100.
The photoresist adopted by the first photoresist layer can be an I-line type photoresist, and the photosensitizer of the I-line type photoresist is first photosensitive resin which is sensitive to common ultraviolet I-line (the wavelength is more than 350 nm); illustratively, as an alternative embodiment of the present invention, the first photosensitive resin may include a naphthoquinone diazo type photosensitive resin having a number average molecular weight of 400 to 2000. The polymer molecules of the naphthoquinone diazo photosensitive resin contain an ortho-diazonaphthoquinone structure, and the solubility of the naphthoquinone diazo photosensitive resin is changed from oil solubility to alkali solubility after the naphthoquinone diazo photosensitive resin absorbs light energy. And the photoresist used in the second photoresist layer may be a DUV type or EUV type photoresist, and the photosensitizer in the second photoresist layer is a second photosensitive resin sensitive to deep ultraviolet DUV (wavelength 200 nm-350 nm) or extreme ultraviolet EUV (wavelength less than 200nm), illustratively, as an optional embodiment of the present invention, the second photosensitive resin includes a photoacid generator (PAG).
In this embodiment, a first photoresist layer 110 with a first thickness is formed on a semiconductor substrate 100, and then a second photoresist layer 120 with a second thickness is formed on the first photoresist layer 110.
The first photoresist layer 110 and the second photoresist layer 120 may be formed by a spin coating method or a spray coating method, for example. In the embodiment of the invention, the first photoresist layer 110 with the first thickness is formed on the semiconductor substrate, the second photoresist layer 120 with the second thickness is formed on the first photoresist layer 110, and then the two photoresist layers are respectively exposed and developed by adopting two different light sources in sequence, so that the problem of small depth of field of the photoresist layer formed on the substrate caused by insufficient exposure and development of the photoresist layer is solved.
Further, the thickness of the first photoresist layer 110 is greater than the thickness of the second photoresist layer 120, for example, the ratio of the thickness of the first photoresist layer 110 to the thickness of the second photoresist layer 120 is 2 to 20.
In this embodiment, the thickness of the first photoresist layer 110 may be 0.5 μm to 3.5 μm; the thickness of the second photoresist 120 may be 0.2 μm to 1.5 μm. It can be understood that, since the second photoresist layer 120 is a DUV type or EUV type photoresist layer and has a characteristic of large depth of field, only a thinner second photoresist layer 120 is required to produce a line width meeting the process requirement, i.e., a pattern structure with a high aspect ratio is formed; the first photoresist layer 110 having the photoresist type of I-line has a high density and a low cost. Therefore, a double-layer paste may be applied on the semiconductor substrate, and the thickness of the lower I-line type first photoresist layer is thicker than that of the upper DUV type second photoresist layer 120, thereby achieving the purpose of reducing the manufacturing cost of the semiconductor device while forming a high aspect ratio pattern.
In step S300, referring to fig. 2b specifically, the second photoresist layer 120 is exposed and developed by the first exposure light source a, so as to transfer the target pattern on the reticle onto the second photoresist layer 120, and form a patterned second photoresist layer 120'.
In this embodiment, when patterning the second photoresist layer 120, a mask (not shown) opposite to the second photoresist layer 120 may be disposed on the second photoresist layer 120, and a target pattern is disposed on the mask. The second photoresist layer 120 is irradiated by a first exposure light source a with a first wavelength through the pattern on the mask to realize exposure. After removing the reticle, the exposed second photoresist layer may be developed to form a patterned second photoresist layer 120' as shown in fig. 2 c.
Further, the first exposure light source a may be a deep ultraviolet DUV light source or an extreme ultraviolet EUV light source. The deep ultraviolet DUV light source is a light source that can generate ultraviolet light having a wavelength (first wavelength) of 200nm to 350nm, and the extreme ultraviolet EUV light source is a light source that can generate ultraviolet light having a wavelength of 200nm or less. Further, the first exposure light source a may be a KrF excimer laser, an ArF excimer laser, or a F2 excimer laser. Wherein the wavelength of KrF excimer laser is 248nm, the wavelength of ArF excimer laser is 193nm, and the wavelength of F2 excimer laser is 157 nm.
In step S400, referring to fig. 2d specifically, the patterned second photoresist layer 120 ' is used as a mask layer, and a second exposure light source B is used to perform an exposure and development process on the first photoresist layer 110, so as to transfer the pattern on the second photoresist layer 120 ' to the first photoresist layer 110, so as to form the patterned first photoresist layer 110 ' shown in fig. 2 e.
In this embodiment, since the second photoresist layer 120 'has a defined corresponding pattern, a photomask is not required when the I-line photoresist layer (the first photoresist layer 110) is exposed, and the defined pattern in the second photoresist layer 120' can be transferred to the underlying first photoresist layer 110 with a small amount of energy, thereby achieving the purpose of forming a high aspect ratio pattern and reducing the manufacturing cost of the semiconductor device.
Further, the second exposure light source B is a common ultraviolet light source with a wavelength of more than 350 nm.
Further, the second exposure light source B may be a high-pressure mercury lamp having a wavelength of 365nm or 436 nm.
It should be further noted that the wavelength of the first exposure light source a is shorter than the wavelength of the second exposure light source B, so that the first exposure light source a can be used to transfer the pattern on the reticle into the second photoresist layer 120 in a highly precise manner, thereby ensuring the downward transfer performance of the pattern in the second photoresist layer 120'.
It is understood that after the pattern on the second photoresist layer 120 ' is transferred onto the first photoresist layer 110, the formed first photoresist layer 110 ' and the second photoresist layer 120 ' are combined into a high aspect ratio pattern, and the aspect ratio of the high aspect ratio pattern may be 4-30.
In addition, the method for forming a high aspect ratio pattern according to the present invention may further include, after transferring the pattern formed on the second photoresist layer 120 'onto the first photoresist layer 110':
etching the semiconductor substrate 100 by using the first photoresist layer 110 ' and the second photoresist layer 120 ' as masks, so as to transfer the pattern in the first photoresist layer 110 ' to the semiconductor substrate 100;
or, removing the second photoresist layer 120 ' first, and then etching the semiconductor substrate 100 with the first photoresist layer 110 ' as a mask, so as to transfer the pattern in the first photoresist layer 110 ' to the semiconductor substrate 100;
or, removing the second photoresist layer 120 ', and then performing ion implantation on the semiconductor substrate 100 by using the first photoresist layer 110 ' as a mask and the first photoresist layer 110 ' as an ion implantation blocking layer, so as to form an ion implantation region in the semiconductor substrate 100. When the semiconductor substrate 100 is a substrate in the front-end of the integrated circuit fabrication process, the ion implantation region can be an active region.
In summary, in the invention, a first photoresist layer with a preset thickness is formed on a semiconductor substrate, a second photoresist layer with a thickness smaller than that of the first photoresist layer is formed on the first photoresist layer, and then the two photoresist layers are respectively exposed and developed by different light sources, so that the problem of small depth of field of the photoresist layer formed on the substrate due to insufficient exposure and development of the photoresist layer is avoided.
Furthermore, because the embodiment of the invention adopts a double-layer gluing mode and a respective exposure and development mode, the first photoresist layer at the lower layer is used for blocking ion implantation, and the second photoresist layer is used for generating the line width required by the process. The second photoresist layer has the characteristic of large depth of field and the first photoresist layer has the characteristics of large density and low cost, and meanwhile, a photomask is not needed when the first photoresist layer is exposed, and a pattern defined in the second photoresist layer can be transferred into the first photoresist layer by only a small amount of energy, so that the aim of forming a high-depth-to-width ratio pattern and reducing the manufacturing cost of a semiconductor device is fulfilled.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated. As used herein, "and/or" means either or both.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (10)
1. A method for forming a high aspect ratio pattern, the method comprising:
providing a semiconductor substrate;
forming a first photoresist layer and a second photoresist layer on the first photoresist layer on the semiconductor substrate;
carrying out exposure and development processes on the second photoresist layer by adopting a first exposure light source so as to transfer a target pattern on the photomask to the second photoresist layer to form a patterned second photoresist layer;
and taking the patterned second photoresist layer as a mask layer, and carrying out exposure and development processes on the first photoresist layer by adopting a second exposure light source so as to transfer the pattern on the second photoresist layer to the first photoresist layer.
2. The method of claim 1, wherein the first exposure light source has a shorter wavelength than the second exposure light source.
3. The method of claim 2, wherein the first exposure light source is a deep ultraviolet DUV light source or an extreme ultraviolet EUV light source.
4. The method of claim 2 or 3, wherein the first exposure light source is a KrF excimer laser, an ArF excimer laser, or an F2 excimer laser.
5. The method of claim 2, wherein the second exposure light source is an ultraviolet light source having a wavelength greater than 350 nm.
6. The method of forming a high aspect ratio pattern according to claim 2 or 5, wherein the second exposure light source is a high-pressure mercury lamp having a wavelength of 365nm or 436 nm.
7. The method of claim 1, wherein the first photoresist has a thickness greater than a thickness of the second photoresist.
8. The method of claim 1, wherein the first photoresist layer and the second photoresist layer are combined into a high aspect ratio pattern after the pattern on the second photoresist layer is transferred onto the first photoresist layer, and the aspect ratio of the high aspect ratio pattern is 4-30.
9. The method for forming a high aspect ratio pattern as claimed in claim 1, 7 or 8, wherein a ratio of a thickness of the first photoresist layer to a thickness of the second photoresist layer is 2 to 20; and/or the thickness of the first photoresist layer can be 0.5-3.5 μm, and the thickness of the second photoresist layer can be 0.2-1.5 μm.
10. The method of claim 1, further comprising, after transferring the pattern on the second photoresist layer to the first photoresist layer, forming a high aspect ratio pattern on the second photoresist layer
Etching the semiconductor substrate by taking the first photoresist layer and the second photoresist layer as masks so as to transfer the pattern in the first photoresist layer to the semiconductor substrate;
or, further comprising: removing the second photoresist layer, and etching the semiconductor substrate by taking the first photoresist layer as a mask so as to transfer the pattern in the first photoresist layer to the semiconductor substrate;
still alternatively, the method further comprises: removing the second photoresist layer, and performing ion implantation on the semiconductor substrate by using the first photoresist layer as a mask to form an ion implantation region in the semiconductor substrate.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112731775A (en) * | 2021-01-06 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Photoetching process method for pattern with ultrahigh depth-to-width ratio |
| CN115793414A (en) * | 2022-12-26 | 2023-03-14 | 有研国晶辉新材料有限公司 | Preparation method of high-aspect-ratio microstructure with adjustable height ratio |
| CN116053116A (en) * | 2023-01-28 | 2023-05-02 | 合肥晶合集成电路股份有限公司 | Method for patterning semiconductor device |
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| CN112731775A (en) * | 2021-01-06 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Photoetching process method for pattern with ultrahigh depth-to-width ratio |
| CN115793414A (en) * | 2022-12-26 | 2023-03-14 | 有研国晶辉新材料有限公司 | Preparation method of high-aspect-ratio microstructure with adjustable height ratio |
| CN116053116A (en) * | 2023-01-28 | 2023-05-02 | 合肥晶合集成电路股份有限公司 | Method for patterning semiconductor device |
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