CN112714947B - 用于制造具有受控尺寸的半导体晶片特征的***及方法 - Google Patents
用于制造具有受控尺寸的半导体晶片特征的***及方法 Download PDFInfo
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Abstract
本发明提供一种用于制造具有受控尺寸的半导体晶片特征的***及方法。在使用中,识别半导体晶片的顶面。接着,垂直地蚀刻所述半导体晶片的所述顶面的第一部分以形成从所述半导体晶片的所述顶面的第二部分向下的阶状部,所述阶状部由水平面及垂直侧壁构成。另外,跨所述阶状部的所述水平面及所述垂直侧壁均匀地沉积膜。此外,垂直地蚀刻所述半导体晶片的所述顶面的所述第二部分以曝露跨所述阶状部的所述垂直侧壁沉积的所述膜作为所述半导体晶片的特征。
Description
相关申请案
本申请案主张2018年9月7日申请的第62/728,664号美国临时专利申请案的权益,所述案的全部内容以引用的方式并入本文中。
技术领域
本发明涉及半导体晶片的制造,且更特定来说,涉及用于制造用作尺寸标准的半导体晶片的特征的过程。
背景技术
用于制造半导体晶片的现存过程涉及根据定义尺寸制造半导体晶片的特征。为产生如预期那样运作的半导体晶片,可期望将所制造半导体晶片上的实际特征尺寸尽可能紧密地对准到定义尺寸。此外,在一些特定应用中,半导体晶片经制造用于计量工具的校准或匹配,此需要这些所制造半导体晶片上的实际特征尺寸在定义尺寸的可允许容限内。因此,需要提供具有受控尺寸的晶片特征的半导体晶片制造过程。
由VSL1标准公司(VSLI Standards,Inc.)标准制成的一个现存制造过程由具有精确控制厚度(在z维度上)的膜堆叠构成,所述膜堆叠从晶片切割且接着安装于其边缘上以便使控制z维度在x/y维度上平移。此类过程的优点是生长具有均匀且控制厚度的膜比使用光刻在x/y维度上产生均匀特征更容易。然而,此现存过程的缺点是其需要昂贵且耗时的接合、切割、抛光及接着蚀刻过程,且更进一步,切割需要到另一衬底的重新安装且注意垂直地定向特征。
因此,需要解决与现有技术相关联的这些及/或其它问题。
发明内容
本发明提供一种用于制造具有受控尺寸的半导体晶片特征的***及方法。在使用中,识别半导体晶片的顶面。接着,垂直地蚀刻所述半导体晶片的所述顶面的第一部分以形成从所述半导体晶片的所述顶面的第二部分向下的阶状部,所述阶状部由水平面及垂直侧壁构成。另外,跨所述阶状部的所述水平面及所述垂直侧壁均匀地沉积膜。此外,垂直地蚀刻所述半导体晶片的所述顶面的所述第二部分以曝露跨所述阶状部的所述垂直侧壁沉积的所述膜作为所述半导体晶片的特征。
附图说明
图1A展示说明包含可在计算机***上执行以用于执行本文中描述的计算机实施方法中的一或多者的程序指令的非暂时性计算机可读媒体的一个实施例的框图。
图1B是说明经配置以检测所制造装置上的缺陷的检验***的一个实施例的侧视图的示意图。
图2展示根据实施例的用于制造具有受控尺寸的半导体晶片特征的方法。
图3A说明根据实施例的半导体晶片的顶面。
图3B说明根据实施例垂直地蚀刻图3A的半导体晶片的顶面的第一部分以形成从半导体晶片的顶面的第二部分向下的阶状部。
图3C说明根据实施例跨图3B的阶状部的水平面及垂直侧壁均匀地沉积膜。
图3D说明根据实施例垂直地蚀刻图3C的半导体晶片的顶面的第二部分以曝露跨阶状部的垂直侧壁沉积的膜作为半导体晶片的特征。
图3E说明根据实施例的图3D的特征的三维图。
图4说明根据实施例的用于制造具有受控尺寸的半导体晶片特征的***。
具体实施方式
以下描述揭示一种用于制造具有受控尺寸的半导体晶片特征的***及方法。一旦制造晶片,其便可出于各种目的使用检验***检验,例如检测缺陷、校准检验(例如,计量)***或执行不同检验(例如,计量)***之间的测量匹配。图1A到1B描述检验***的各种实施例。
如图1A中展示,计算机可读媒体100包含可在计算机***104上执行的程序指令102。程序指令102可经执行用于上文提及的各种目的,例如检测缺陷、校准检验(例如,计量)***或执行不同检验(例如,计量)***之间的测量匹配。
程序指令102可存储于计算机可读媒体100上。计算机可读媒体可为存储媒体,例如磁盘或光盘或磁带或所属领域中已知的任何其它适合非暂时性计算机可读媒体。作为选项,计算机可读媒体100可定位于计算机***104内。
程序指令可以各种方式中的任一者实施,包含基于程序的技术、基于组件的技术及/或面向对象技术等。例如,程序指令可视需要使用ActiveX控件、C++对象、JavaBeans、微软基础类别(“MFC”)或其它技术或方法实施。
计算机***104可采用各种形式,包含个人计算机***、图像计算机、主计算机***、工作站、网络设备、因特网设备,或其它装置。一般来说,术语“计算机***”可为广泛地定义为涵盖具有执行来自存储器媒体的指令的一或多个处理器的任何装置。计算机***104还可包含所属领域中已知的任何适合处理器,例如并行处理器。另外,计算机***104可包含具有高速处理及软件的计算机平台(作为独立或联网工具)。
在一个实施例中,计算机***104可为还包含检验***105的较大***的子***,如图1B中展示。***包含经配置以针对在晶片(或其它装置)上制造的特征产生输出的检验***105,其在此实施例中是如本文中进一步描述那样配置。***还包含一或多个计算机***。一或多个计算机***可经配置以执行上文描述的操作。计算机***及***还可经配置以执行本文中描述的任何其它操作,且可如本文中描述那样进一步配置。
在图1B中展示的实施例中,计算机***中的一者是电子设计自动化(EDA)工具的部分,且检验***及计算机***中的另一者并非EDA工具的部分。这些计算机***可包含(例如)上文参考图1A所描述的计算机***104。例如,如图1B中展示,计算机***中的一者可为包含于EDA工具106中的计算机***108。EDA工具106及包含于此工具中的计算机***108可包含任何市售EDA工具。
检验***105可经配置以通过使用光来扫描晶片,且在扫描期间检测来自晶片的光而针对晶片上的特征产生输出。例如,如图1B中展示,检验***105包含光源120,光源120可包含所属领域中已知的任何适合光源。可将来自光源的光引导到光束分离器118,光束分离器118可经配置以将来自光源的光引导到晶片122。光源120可被耦合到任何其它适合元件(未展示),例如一或多个聚光透镜、准直透镜、中继透镜、物镜、光圈、光谱滤波器、偏光组件及类似物。如图1B中展示,可依法向入射角将光引导到晶片122。然而,可依任何适合入射角(包含近法向入射及倾斜入射)将光引导到晶片122。另外,可依序或同时依一个以上入射角将光或多个光束引导到晶片122。检验***105可经配置以依任何适合方式使光扫描遍及晶片122。
在扫描期间可通过检验***105的一或多个通道收集及检测来自晶片122的光。例如,依相对接近于法线的角度从晶片122反射的光(即,在入射系法向时的镜面反射光)可穿过光束分离器118到透镜114。透镜114可包含折射光学元件,如图1B中展示。另外,透镜114可包含一或多个折射光学元件及/或一或多个反射光学元件。可将由透镜114收集的光聚焦到检测器112。检测器112可包含所属领域中已知的任何适合检测器,例如电荷耦合装置(CCD)或另一类型的成像检测器。检测器112经配置以产生响应于由透镜114收集的反射光的输出。因此,透镜114及检测器112形成检验***105的一个通道。检验***105的此通道可包含所属领域中已知的任何其它适合光学组件(未展示)。
由于图1B中展示的检验***经配置以检测从晶片122镜面反射的光,所以检验***105经配置为(明场)BF检验***。然而,此检验***105还可经配置用于其它类型的晶片检验。例如,图1B中展示的检验***还可包含一或多个其它通道(未展示)。其它通道可包含本文中描述的光学组件中的任一者,例如配置为散射光通道的透镜及检测器。透镜及检测器可如本文中描述那样进一步配置。以此方式,检验***105还可经配置用于(暗场)DF检验。
检验***105还可包含计算机***110。例如,上文描述的光学元件可形成检验子***105的光学子***111,检验子***105还可包含耦合到光学子***111的计算机***110。以此方式,可将在扫描期间由检测器产生的输出提供到计算机***110。例如,计算机***110可耦合到检测器112(例如,通过由图1B中的虚线展示的一或多个传输媒体,其可包含所属领域中已知的任何适合传输媒体),使得计算机***110可接收由检测器产生的输出。
检验***105的计算机***110可经配置以执行上文描述的操作中的任一者。例如,计算机***110可经配置用于从晶片识别的图案缺陷的***及随机特性化或用于测量晶片的特征。另外,计算机***中的一或多者可配置为虚拟检验器,例如2012年2月28日发布的巴斯卡尔(Bhaskar)等人的第8,126,255号美国专利中描述的虚拟检验器,所述案以宛如全文陈述引用的方式并入本文中。
检验***105的计算机***110还可耦合到并非检验***的部分的另一计算机***(例如计算机***108,其可包含于例如上文描述的EDA工具106的另一工具中),使得计算机***110可接收由计算机***108产生的输出,所述输出可包含由所述计算机***108产生的设计。例如,两个计算机***可由共享计算机可读存储媒体(例如制作数据库(fabdatabase))有效地耦合或可由传输媒体(例如上文描述的传输媒体)耦合,使得可在两个计算机***之间传输信息。
应注意,本文中提供图1B以大体上说明可如本文中描述那样利用的检验***的配置。显然,如在设计商业检验***时通常所执行那样,可更改本文中描述的检验***布置以优化检验***的性能。另外,本文中描述的***可使用例如购自KLA-Tencor的29xx/28xx系列工具的现存检验***(例如,通过将本文中描述的功能性添加到现存检验***)实施。对于一些此类***,本文中描述的方法可提供为***的任选功能性(例如,除***的其它功能性以外)。替代地,可“从头开始”设计本文中描述的***以提供全新***。
在另一实施例中,检验***105可直接或间接耦合到检视***(未展示),例如第9,293,298号美国专利中揭示的SEM检视***。SEM检视***可操作以检视由检验***105检测的缺陷以对缺陷分类,所述缺陷又可用于训练检验***105以进行更佳缺陷检测。
图2展示根据实施例的用于制造具有受控尺寸的半导体晶片特征的方法200。方法200可由具有经配置用于以所描述的方式制造半导体晶片特征的硬件组件的任何***实施。例如,方法200可由下文参考图4描述的***400实施。
如操作202中展示,识别半导体晶片的顶面。半导体晶片可为由半导体材料构成的任何晶片。因此,半导体晶片的顶面可为半导体材料的衬底。
例如,在一个实施例中,半导体晶片可为硅晶片(即,由硅材料构成)。在此实施例中,半导体晶片的顶面可为硅衬底,例如(110)硅。在另一实施例中,半导体晶片的顶面可为沉积于半导体晶片的衬底上的硬掩模。在此实施例中,硬掩模可为氮化硅。
如操作204中展示,垂直地蚀刻半导体晶片的顶面的第一部分以形成从半导体晶片的顶面的第二部分向下的阶状部。由于垂直蚀刻,阶状部包括水平面(在低于半导体晶片的顶面的第二部分的高度处)及垂直侧壁(从半导体晶片的顶面的第二部分延伸至水平面)。垂直蚀刻可包含干式蚀刻或湿式蚀刻。
在上文描述的实施例中(其中半导体晶片的顶面是沉积于半导体晶片的衬底上的硬掩模),垂直地蚀刻半导体晶片的顶面的第一部分可包含垂直地蚀刻穿过硬掩模的第一部分及硬掩模的第一部分经沉积于其上的半导体晶片的衬底(硅)的第一部分。在任何情况中,应注意,可将半导体晶片的顶面的第一部分垂直地蚀刻到任何所要深度。
另外,如操作206中展示,跨阶状部的水平面及垂直侧壁均匀地沉积膜。例如,膜可包含热氧化硅。作为另一实例,膜可包含气相生长金属。然而,当然,膜可包含任何其它膜材料,只要半导体晶片的顶面的第二部分可经垂直地蚀刻且因此从经沉积于阶状部的垂直侧壁上的膜移除即可,此原因将在下文更详细提及。
为此,在各种实施例中,可通过热氧化、化学气相沉积或能够跨阶状部的水平面及垂直侧壁均匀地沉积膜的任何其它过程来均匀地沉积膜。通过跨阶状部的水平面及垂直侧壁均匀地沉积膜,可控制沉积于阶状部的表面上的膜的宽度。例如,可控制所使用的膜沉积过程以依所要与均匀厚度来沉积膜。
此外,如操作208中展示,垂直地蚀刻半导体晶片的顶面的第二部分以曝露跨阶状部的垂直侧壁沉积的膜作为半导体晶片的特征。在一个实施例中,垂直地蚀刻半导体晶片的顶面的第二部分可包含在垂直方向上部分移除半导体晶片的顶面的第二部分。在另一实施例中,垂直地蚀刻半导体晶片的顶面的第二部分可包含在垂直方向上完全移除半导体晶片的顶面的第二部分。通过垂直地蚀刻半导体晶片的顶面的第二部分以曝露跨阶状部的垂直侧壁沉积的膜作为特征,可控制所述特征的高度。
因此,可通过跨阶状部的垂直侧壁沉积的膜的宽度特性化所述特征。以此方式,可通过控制上文描述的膜沉积及蚀刻过程而提供特征的受控尺寸(即,特征的宽度)。
应注意,可通过针对半导体晶片的顶面的不同位置重复方法200而形成半导体晶片的多个特征。方法200还可在半导体晶片的顶面的多个不同位置中同时执行。通过控制膜沉积及蚀刻过程以制造每一特征,这些特征可以控制方式在宽度、高度及形状上变化。
以上文描述的方式,方法200可为半导体晶片特征提供良好特性化且可重复的尺寸标准。此可允许这些特征用于校准如在半导体工业中的临界尺寸(CD)测量中测量小于100nm的特征的计量工具,例如临界尺寸原子力显微镜(CD-AFM)工具及临界尺寸扫描电子显微镜(CD-SEM)工具。此还可允许这些特征用于跨不同计量工具的测量匹配,例如第8,003,940号美国专利中揭示的SEM的工具匹配方法。
另外,方法200可通过消除对晶片接合、裸片抛光或至其它衬底的定向及安装的需求而为那些控制特征提供比来自现有技术的特征更简单的膜堆叠。方法200可进一步提供视需要制造具有各种形状及大小且使用不同膜材料的半导体晶片特征的能力。
现在将陈述关于各种任选架构及用途的更多说明性信息,其中根据用户需求可实施或可不实施前述方法。应注意,以下信息是出于说明性目的而陈述且不应以任何方式解释为限制性的。在排除或不排除所描述的其它特征的情况下可视情况并入以下特征中的任一者。
图3A说明根据实施例的半导体晶片的顶面。如展示,半导体晶片包含沉积于硅衬底304上的硬掩模302。硬掩模302可为氮化硅且硅衬底可为(110)硅。应注意,在不同应用中,可跨硅衬底304的整个表面或硅衬底304的一部分表面沉积且图案化硬掩模302。
图3B说明根据实施例垂直地蚀刻图3A的半导体晶片的顶面的第一部分以形成从半导体晶片的顶面的第二部分向下的阶状部。阶状部由垂直侧壁(具有等于垂直蚀刻的深度的高度)及水平面(具有等于半导体晶片的顶面的第一部分的长度的长度)构成,如展示。垂直蚀刻可使用湿式蚀刻执行,例如通过高度均匀且导致(110)硅晶片上的直线及垂直侧壁的湿各向异性过程(例如,KOH)。作为另一选项,垂直蚀刻可使用干式蚀刻执行,例如通过可改变所得阶状部的形状(以控制方式)的反应性离子蚀刻过程(例如,波希(Bosch)过程)。
作为选项,在图3B的上下文中,可执行阶状部的化学机械抛光。此可使阶状部的角度锐化以实现更尖锐所得特征,如下文更详细描述。
图3C说明根据实施例跨图3B的阶状部的水平面及垂直侧壁均匀地沉积膜。如展示,跨阶状部的水平面及垂直侧壁均匀地沉积(生长)膜306(例如热氧化硅)。除热氧化硅以外,还可使用其它膜材料,例如气相生长金属,只要半导体晶片的顶面的第二部分可从膜306蚀刻即可(如下文参考图3D描述)。气相生长金属的使用可有益于产生半导体晶片特征,因为此材料的特征可在某些检验工具中提供较大成像对比度。在任何情况中,膜306的均匀沉积导致膜306在阶状部的水平面及垂直侧壁上方的一致厚度(t)。
作为选项,在均匀地沉积膜306之后,可对半导体晶片的顶面的第二部分执行化学机械平坦化(CMP)。此可移除硬掩模302且减小阶状部高度。重要的是,此可移除硅衬底304、硬掩模302及膜306的结处的界面非化学计量组合物,否则其无法经由图3D中描述的垂直蚀刻蚀刻到干净特征中。
图3D说明根据实施例垂直地蚀刻图3C的半导体晶片的顶面的第二部分以曝露跨阶状部的垂直侧壁沉积的膜作为半导体晶片的特征。在一个实施例中,可对半导体晶片的顶面的第二部分执行垂直蚀刻(在图3B中指示),包含垂直穿过硬掩模302及硅衬底304的一部分。因此,跨阶状部的垂直侧壁沉积的膜306部分从侧壁释放,且形成半导体晶片的垂直特征,其通过膜306的宽度(t)及对应于所展示垂直蚀刻的深度的高度(h)特性化。
图3E说明根据实施例的图3D的特征的三维图。如展示,由参考图3A到D描述的制造过程导致的特征通过宽度(t)及高度(h)特性化且由沉积于硅衬底302上的膜306材料形成。
在使用椭圆偏光术特性化之后(如果透明),可在现存硅衬底302上使用半导体晶片特征。其还可经切割且安装于其它衬底(晶片或掩模)上以作为成本降低措施(一个经处理晶片可导致数千个可用特征)。通过椭圆偏光术及/或横截面透射电子显微镜(TEM),可将膜306的厚度及半导体晶片特征的所得宽度特性化为可跟踪标准,例如单晶硅的原子晶格或He-Ne激光波长。接着,特征可用于CD-AFM或CD-SEM的工具匹配或校准。
图4说明根据实施例的用于制造具有受控尺寸的半导体晶片特征的***400。***400可经实施以实施图2的方法200及/或上文参考图3A到3E描述的过程。应注意,***400不限于所展示的组件,而可包含如相关技术中所理解的额外组件。此外,***400的组件是经配置用于制造具有受控尺寸的半导体晶片特征的硬件组件。
如展示,***400包含蚀刻组件402。蚀刻组件垂直地蚀刻半导体晶片的顶面的第一部分以形成从半导体晶片的顶面的第二部分向下的阶状部,其中阶状部由水平面及垂直侧壁构成(见图2的操作204及/或图3B)。***400还包含膜沉积组件404,其跨阶状部的水平面及垂直侧壁均匀地沉积膜(见图2的操作206及/或图3C)。蚀刻组件402进一步垂直地蚀刻半导体晶片的顶面的第二部分以曝露跨阶状部的垂直侧壁沉积的膜作为半导体晶片的特征(见操作208及/或图3D)。
虽然上文已描述各种实施例,但应理解其仅通过实例呈现且非限制性。因此,优选实施例的宽度及范围不应受上述示范性实施例中的任一者限制,而应仅根据随附权利要求书及其等效物定义。
Claims (11)
1.一种方法,其包括:
识别半导体晶片的顶面,其中所述半导体晶片的所述顶面是经沉积于所述半导体晶片的衬底上的硬掩模;
将所述半导体晶片的所述顶面的第一部分垂直地蚀刻到选择深度以形成从所述半导体晶片的所述顶面的第二部分向下的阶状部,所述阶状部由比所述半导体晶片的所述顶面的所述第二部分低的高度处的水平面及从所述半导体晶片的所述顶面的所述第二部分延伸到所述水平面的垂直侧壁构成;
对所述阶状部进行化学机械抛光CMP;
在对所述阶状部进行化学机械抛光CMP之后,跨所述阶状部的所述水平面及所述垂直侧壁均匀地沉积具有选择厚度的膜;
在跨所述阶状部的所述水平面及所述垂直侧壁均匀地沉积所述膜之后,在所述半导体晶片的所述顶面的所述第二部分上进行CMP以减少所述阶状部的高度;
在所述半导体晶片的所述顶面的所述第二部分之上进行CMP以减少所述阶状部的高度之后,从所述膜将所述半导体晶片的所述顶面的所述第二部分垂直地蚀刻到选择深度,以曝露跨所述阶状部的所述垂直侧壁沉积的所述膜作为所述半导体晶片的特征,其中所述特征的尺寸是根据所述膜经沉积的所述选择厚度和所述半导体晶片的所述顶面的所述第二部分经垂直蚀刻的所述选择深度所控制。
2.根据权利要求1所述的方法,其中所述半导体晶片是硅晶片。
3.根据权利要求1所述的方法,其中所述半导体晶片的所述衬底是硅衬底。
4.根据权利要求1所述的方法,其中所述硬掩模是氮化硅。
5.根据权利要求1所述的方法,其中使用湿式蚀刻垂直地蚀刻所述半导体晶片的所述顶面的所述第一部分。
6.根据权利要求1所述的方法,其中使用干式蚀刻垂直地蚀刻所述半导体晶片的所述顶面的所述第一部分。
7.根据权利要求1所述的方法,其中通过热氧化,跨所述阶状部的所述垂直侧壁均匀地沉积具有所述选择厚度的所述膜。
8.根据权利要求1所述的方法,其中通过化学气相沉积,跨所述阶状部的所述垂直侧壁以受控宽度均匀地沉积所述膜。
9.根据权利要求1所述的方法,其中所述特征是用于计量工具的校准。
10.根据权利要求1所述的方法,其中所述特征是用于多个计量工具之间的测量匹配。
11.根据权利要求1所述的方法,其中通过针对所述半导体晶片的所述顶面的不同位置重复所述半导体晶片的所述顶面的所述第一部分的所述垂直蚀刻、所述膜的所述均匀地沉积及所述半导体晶片的所述顶面的所述第二部分的所述垂直蚀刻来形成所述半导体晶片的多个特征。
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